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Platform-independent core collection
Commit f7578270 authored by Antonin Broquet's avatar Antonin Broquet
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apply xilinx recommendation for clock domain crossing and sync reset

parent 96630ec6
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Showing with 167 additions and 293 deletions
modules/common/gc_crc_gen.vhd
View file @ f7578270
......@@ -125,7 +125,6 @@ architecture rtl of gc_crc_gen is
signal crca : fb_array;
signal da, ma : dmsb_array;
signal crc : std_logic_vector(msb downto 0);
signal arst, srst : std_logic;
signal data_i2 : std_logic_vector(g_data_width-1 downto 0);
......@@ -193,30 +192,19 @@ begin
((da(i) xor ma(i)) and p(msb downto 1));
end generate FB;
-- Reset signal
SR : if g_sync_reset = 1 generate
srst <= rst_i;
arst <= '0';
end generate SR;
AR : if g_sync_reset = 0 generate
srst <= '0';
arst <= rst_i;
end generate AR;
CRCP : process (clk_i, arst)
CRCP : process (clk_i)
begin
if arst = '1' then -- async. reset
crc <= g_init_value;
elsif rising_edge(clk_i) then
if srst = '1' then -- sync. reset
if rising_edge(clk_i) then
if rst_i = '1' then -- sync. reset
crc <= g_init_value;
elsif en_i = '1' then
if(half_i = '1' and g_dual_width = 1) then
crc <= crca(g_half_width);
else
crc <= crca(g_data_width);
else
if en_i = '1' then
if(half_i = '1' and g_dual_width = 1) then
crc <= crca(g_half_width);
else
crc <= crca(g_data_width);
end if;
end if;
end if;
end if;
......@@ -248,13 +236,10 @@ begin
gen_reg_match_output : if(g_registered_match_output) generate
match_gen : process (clk_i, arst)
match_gen : process (clk_i)
begin
if arst = '1' then -- async. reset
match_o <= '0';
en_d0 <= '0';
elsif rising_edge(clk_i) then
if srst = '1' then -- sync. reset
if rising_edge(clk_i) then
if rst_i = '1' then -- sync. reset
match_o <= '0';
en_d0 <= '0';
else
......
modules/common/gc_edge_detect.vhd
View file @ f7578270
......@@ -36,14 +36,14 @@ entity gc_edge_detect is
g_CLOCK_EDGE : string := "positive");
port(
clk_i : in std_logic; -- clock
rst_n_i : in std_logic; -- reset
rst_n_i : in std_logic := '0'; -- reset
data_i : in std_logic; -- input
pulse_o : out std_logic); -- positive edge detect output
end entity gc_edge_detect;
architecture arch of gc_edge_detect is
signal dff : std_logic;
signal dff : std_logic := '0';
begin
......@@ -58,43 +58,13 @@ begin
pulse_o <= not data_i and dff;
end generate gen_neg_pulse;
gen_async_rst : if g_ASYNC_RST = TRUE generate
sync_posedge : if g_CLOCK_EDGE = "positive" generate
process (clk_i, rst_n_i)
begin
if rst_n_i = '0' then
dff <= '0';
elsif rising_edge (clk_i) then
dff <= data_i;
end if;
end process;
end generate sync_posedge;
sync_negedge : if g_CLOCK_EDGE = "negative" generate
process (clk_i, rst_n_i)
begin
if rst_n_i = '0' then
dff <= '0';
elsif falling_edge (clk_i) then
dff <= data_i;
end if;
end process;
end generate sync_negedge;
end generate gen_async_rst;
gen_sync_rst : if g_ASYNC_RST = FALSE generate
sync_posedge : if g_CLOCK_EDGE = "positive" generate
process (clk_i)
begin
if rising_edge (clk_i) then
if rst_n_i = '0' then
dff <= '0';
else
dff <= data_i;
end if;
dff <= data_i;
end if;
end process;
end generate sync_posedge;
......@@ -103,11 +73,7 @@ begin
process (clk_i)
begin
if falling_edge (clk_i) then
if rst_n_i = '0' then
dff <= '0';
else
dff <= data_i;
end if;
dff <= data_i;
end if;
end process;
end generate sync_negedge;
......
modules/common/gc_extend_pulse.vhd
View file @ f7578270
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2009-09-01
-- Last update: 2020-03-30
-- Last update: 2021-05-31
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -50,7 +50,7 @@ entity gc_extend_pulse is
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
rst_n_i : in std_logic := '0';
-- input pulse (synchronou to clk_i)
pulse_i : in std_logic;
-- extended output pulse
......@@ -59,17 +59,14 @@ end gc_extend_pulse;
architecture rtl of gc_extend_pulse is
signal cntr : unsigned(f_log2_ceil(g_width)-1 downto 0);
signal extended_int : std_logic;
signal cntr : unsigned(f_log2_ceil(g_width)-1 downto 0) := (others => '0');
signal extended_int : std_logic := '0';
begin -- rtl
extend : process (clk_i, rst_n_i)
extend : process (clk_i)
begin -- process extend
if rst_n_i = '0' then -- asynchronous reset (active low)
extended_int <= '0';
cntr <= (others => '0');
elsif clk_i'event and clk_i = '1' then -- rising clock edge
if clk_i'event and clk_i = '1' then -- rising clock edge
if(pulse_i = '1') then
extended_int <= '1';
cntr <= to_unsigned(g_width - 2, cntr'length);
......
modules/common/gc_frequency_meter.vhd
View file @ f7578270
......@@ -94,7 +94,7 @@ begin
port map (
clk_in_i => clk_sys_i,
clk_out_i => clk_in_i,
rst_n_i => '1',
rst_n_i => '0',
d_ready_o => freq_valid_o,
d_p_i => gate_pulse,
q_p_o => gate_pulse_synced);
......@@ -107,7 +107,7 @@ begin
port map (
clk_in_i => clk_sys_i,
clk_out_i => clk_in_i,
rst_n_i => '1',
rst_n_i => '0',
d_ready_o => freq_valid_o,
d_p_i => pps_p1_i,
q_p_o => gate_pulse_synced);
......
modules/common/gc_pulse_synchronizer.vhd
View file @ f7578270
......@@ -36,7 +36,7 @@ entity gc_pulse_synchronizer is
-- pulse output clock
clk_out_i : in std_logic;
-- system reset (clk_in_i domain)
rst_n_i : in std_logic;
rst_n_i : in std_logic := '0';
-- pulse input ready (clk_in_i domain). When HI, a pulse
-- coming to d_p_i will be correctly transferred to q_p_o.
d_ready_o : out std_logic;
......
modules/common/gc_pulse_synchronizer2.vhd
View file @ f7578270
......@@ -33,10 +33,10 @@ entity gc_pulse_synchronizer2 is
port (
-- pulse input clock
clk_in_i : in std_logic;
rst_in_n_i : in std_logic;
rst_in_n_i : in std_logic := '0';
-- pulse output clock
clk_out_i : in std_logic;
rst_out_n_i : in std_logic;
rst_out_n_i : in std_logic := '0';
-- pulse input ready (clk_in_i domain). When HI, a pulse
-- coming to d_p_i will be correctly transferred to q_p_o.
d_ready_o : out std_logic;
......@@ -67,7 +67,6 @@ begin -- rtl
cmp_in2out_sync : gc_sync
port map (
clk_i => clk_out_i,
rst_n_a_i => rst_out_n_i,
d_i => in_ext,
q_o => out_ext);
......@@ -75,14 +74,12 @@ begin -- rtl
cmp_pulse_out : gc_edge_detect
port map (
clk_i => clk_out_i,
rst_n_i => rst_out_n_i,
data_i => out_ext,
pulse_o => q_p_o);
cmp_out2in_sync : gc_sync
port map (
clk_i => clk_in_i,
rst_n_a_i => rst_in_n_i,
d_i => out_ext,
q_o => out_feedback);
......
modules/common/gc_sync.vhd
View file @ f7578270
......@@ -31,7 +31,6 @@ entity gc_sync is
g_SYNC_EDGE : string := "positive");
port (
clk_i : in std_logic;
rst_n_a_i : in std_logic;
d_i : in std_logic;
q_o : out std_logic);
end gc_sync;
......@@ -41,65 +40,36 @@ end gc_sync;
architecture arch of gc_sync is
-- Use an intermediate signal with a particular name and a keep attribute
-- so that it can be referenced in the constraints in order to ignore
-- timing (TIG) on that signal.
signal gc_sync_ffs_in : std_logic;
signal sync_0ff, sync_1ff : std_logic := '0';
signal sync0, sync1 : std_logic;
attribute rloc : string;
attribute rloc of sync0 : signal is "X0Y0";
attribute rloc of sync1 : signal is "X0Y0";
attribute shreg_extract : string;
attribute shreg_extract of sync0 : signal is "no";
attribute shreg_extract of sync1 : signal is "no";
attribute keep : string;
attribute keep of gc_sync_ffs_in : signal is "true";
attribute keep of sync0 : signal is "true";
attribute keep of sync1 : signal is "true";
attribute keep_hierarchy : string;
attribute keep_hierarchy of arch : architecture is "true";
attribute async_reg : string;
attribute async_reg of sync0 : signal is "true";
attribute async_reg of sync1 : signal is "true";
attribute async_reg : string;
attribute async_reg of sync_0ff : signal is "true";
attribute async_reg of sync_1ff : signal is "true";
begin
assert g_SYNC_EDGE = "positive" or g_SYNC_EDGE = "negative" severity failure;
gc_sync_ffs_in <= d_i;
sync_posedge : if (g_SYNC_EDGE = "positive") generate
process(clk_i, rst_n_a_i)
process(clk_i)
begin
if rst_n_a_i = '0' then
sync1 <= '0';
sync0 <= '0';
elsif rising_edge(clk_i) then
sync0 <= gc_sync_ffs_in;
sync1 <= sync0;
if rising_edge(clk_i) then
sync_0ff <= d_i;
sync_1ff <= sync_0ff;
end if;
end process;
end generate sync_posedge;
sync_negedge : if(g_SYNC_EDGE = "negative") generate
process(clk_i, rst_n_a_i)
process(clk_i)
begin
if rst_n_a_i = '0' then
sync1 <= '0';
sync0 <= '0';
elsif falling_edge(clk_i) then
sync0 <= gc_sync_ffs_in;
sync1 <= sync0;
if falling_edge(clk_i) then
sync_0ff <= d_i;
sync_1ff <= sync_0ff;
end if;
end process;
end generate sync_negedge;
q_o <= sync1;
q_o <= sync_1ff;
end arch;
modules/common/gc_sync_ffs.vhd
View file @ f7578270
......@@ -32,7 +32,7 @@ entity gc_sync_ffs is
g_SYNC_EDGE : string := "positive");
port(
clk_i : in std_logic; -- clock from the destination clock domain
rst_n_i : in std_logic; -- async reset
rst_n_i : in std_logic := '0'; -- async reset
data_i : in std_logic; -- async input
synced_o : out std_logic; -- synchronized output
npulse_o : out std_logic; -- negative edge detect output
......@@ -41,7 +41,7 @@ end entity gc_sync_ffs;
architecture arch of gc_sync_ffs is
signal sync, npulse, ppulse : std_logic;
signal sync, npulse, ppulse : std_logic := '0';
begin
......@@ -50,40 +50,31 @@ begin
g_SYNC_EDGE => g_SYNC_EDGE)
port map (
clk_i => clk_i,
rst_n_a_i => rst_n_i,
d_i => data_i,
q_o => sync);
cmp_gc_posedge : entity work.gc_edge_detect
generic map (
g_ASYNC_RST => TRUE,
g_PULSE_EDGE => "positive",
g_CLOCK_EDGE => g_SYNC_EDGE)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => sync,
pulse_o => ppulse);
cmp_gc_negedge : entity work.gc_edge_detect
generic map (
g_ASYNC_RST => TRUE,
g_PULSE_EDGE => "negative",
g_CLOCK_EDGE => g_SYNC_EDGE)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => sync,
pulse_o => npulse);
sync_posedge : if (g_SYNC_EDGE = "positive") generate
process(clk_i, rst_n_i)
process(clk_i)
begin
if(rst_n_i = '0') then
synced_o <= '0';
npulse_o <= '0';
ppulse_o <= '0';
elsif rising_edge(clk_i) then
if rising_edge(clk_i) then
synced_o <= sync;
npulse_o <= npulse;
ppulse_o <= ppulse;
......@@ -92,13 +83,9 @@ begin
end generate sync_posedge;
sync_negedge : if(g_SYNC_EDGE = "negative") generate
process(clk_i, rst_n_i)
process(clk_i)
begin
if(rst_n_i = '0') then
synced_o <= '0';
npulse_o <= '0';
ppulse_o <= '0';
elsif falling_edge(clk_i) then
if falling_edge(clk_i) then
synced_o <= sync;
npulse_o <= npulse;
ppulse_o <= ppulse;
......
modules/common/gc_sync_register.vhd
View file @ f7578270
......@@ -30,7 +30,7 @@ entity gc_sync_register is
g_width : integer);
port (
clk_i : in std_logic;
rst_n_a_i : in std_logic;
rst_n_a_i : in std_logic := '0';
d_i : in std_logic_vector(g_width-1 downto 0);
q_o : out std_logic_vector(g_width-1 downto 0));
......@@ -41,41 +41,22 @@ end gc_sync_register;
architecture rtl of gc_sync_register is
signal gc_sync_register_in : std_logic_vector(g_width-1 downto 0);
signal sync0, sync1 : std_logic_vector(g_width-1 downto 0);
signal sync0, sync1 : std_logic_vector(g_width-1 downto 0) := (others => '0');
attribute shreg_extract : string;
attribute shreg_extract of gc_sync_register_in : signal is "no";
attribute shreg_extract of sync0 : signal is "no";
attribute shreg_extract of sync1 : signal is "no";
attribute keep : string;
attribute keep of gc_sync_register_in : signal is "true";
attribute keep of sync0 : signal is "true";
attribute keep of sync1 : signal is "true";
attribute keep_hierarchy : string;
attribute keep_hierarchy of rtl : architecture is "true";
attribute async_reg : string;
attribute async_reg of gc_sync_register_in : signal is "true";
attribute async_reg of sync0 : signal is "true";
attribute async_reg of sync1 : signal is "true";
attribute async_reg : string;
attribute async_reg of sync0 : signal is "true";
attribute async_reg of sync1 : signal is "true";
begin
process(clk_i, rst_n_a_i)
process(clk_i)
begin
if(rst_n_a_i = '0') then
sync1 <= (others => '0');
sync0 <= (others => '0');
elsif rising_edge(clk_i) then
sync0 <= gc_sync_register_in;
if rising_edge(clk_i) then
sync0 <= d_i;
sync1 <= sync0;
end if;
end process;
gc_sync_register_in <= d_i;
q_o <= sync1;
q_o <= sync1;
end rtl;
modules/common/gencores_pkg.vhd
View file @ f7578270
......@@ -253,7 +253,6 @@ package gencores_pkg is
g_SYNC_EDGE : string := "positive");
port (
clk_i : in std_logic;
rst_n_a_i : in std_logic;
d_i : in std_logic;
q_o : out std_logic);
end component gc_sync;
......@@ -268,7 +267,6 @@ package gencores_pkg is
g_CLOCK_EDGE : string := "positive");
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
data_i : in std_logic;
pulse_o : out std_logic);
end component gc_edge_detect;
......
modules/genrams/common/inferred_async_fifo.vhd
View file @ f7578270
......@@ -121,12 +121,12 @@ architecture syn of inferred_async_fifo is
signal rcb, wcb : t_counter_block := (others =>(others => '0'));
signal full_int, empty_int : std_logic;
signal almost_full_int, almost_empty_int : std_logic;
signal going_full : std_logic;
signal full_int, empty_int : std_logic := '0';
signal almost_full_int, almost_empty_int : std_logic := '0';
signal going_full : std_logic := '0';
signal wr_count, rd_count : t_counter;
signal rd_int, we_int : std_logic;
signal wr_count, rd_count : t_counter := (others => '0');
signal rd_int, we_int : std_logic := '0';
signal wr_empty_x : std_logic := '0';
signal rd_full_x : std_logic := '0';
......@@ -166,12 +166,9 @@ begin -- syn
wcb.bin_next <= std_logic_vector(unsigned(wcb.bin) + 1);
wcb.gray_next <= f_gray_encode(wcb.bin_next);
p_write_ptr : process(clk_wr_i, rst_n_i)
p_write_ptr : process(clk_wr_i)
begin
if rst_n_i = '0' then
wcb.bin <= (others => '0');
wcb.gray <= (others => '0');
elsif rising_edge(clk_wr_i) then
if rising_edge(clk_wr_i) then
if(we_int = '1') then
wcb.bin <= wcb.bin_next;
wcb.gray <= wcb.gray_next;
......@@ -182,12 +179,9 @@ begin -- syn
rcb.bin_next <= std_logic_vector(unsigned(rcb.bin) + 1);
rcb.gray_next <= f_gray_encode(rcb.bin_next);
p_read_ptr : process(clk_rd_i, rst_n_i)
p_read_ptr : process(clk_rd_i)
begin
if rst_n_i = '0' then
rcb.bin <= (others => '0');
rcb.gray <= (others => '0');
elsif rising_edge(clk_rd_i) then
if rising_edge(clk_rd_i) then
if(rd_int = '1') then
rcb.bin <= rcb.bin_next;
rcb.gray <= rcb.gray_next;
......@@ -216,11 +210,9 @@ begin -- syn
wcb.bin_x <= f_gray_decode(wcb.gray_x, 1);
rcb.bin_x <= f_gray_decode(rcb.gray_x, 1);
p_gen_empty : process(clk_rd_i, rst_n_i)
p_gen_empty : process(clk_rd_i)
begin
if rst_n_i = '0' then
empty_int <= '1';
elsif rising_edge (clk_rd_i) then
if rising_edge (clk_rd_i) then
if(rcb.gray = wcb.gray_x or (rd_int = '1' and (wcb.gray_x = rcb.gray_next))) then
empty_int <= '1';
else
......@@ -268,11 +260,9 @@ begin -- syn
end if;
end process p_gen_going_full;
p_register_full : process(clk_wr_i, rst_n_i)
p_register_full : process(clk_wr_i)
begin
if rst_n_i = '0' then
full_int <= '0';
elsif rising_edge (clk_wr_i) then
if rising_edge (clk_wr_i) then
full_int <= going_full;
end if;
end process p_register_full;
......@@ -280,11 +270,9 @@ begin -- syn
wr_full_o <= full_int;
rd_full_o <= rd_full_x;
p_reg_almost_full : process(clk_wr_i, rst_n_i)
p_reg_almost_full : process(clk_wr_i)
begin
if rst_n_i = '0' then
almost_full_int <= '0';
elsif rising_edge(clk_wr_i) then
if rising_edge(clk_wr_i) then
wr_count <= std_logic_vector(unsigned(wcb.bin) - unsigned(rcb.bin_x));
if (unsigned(wr_count) >= g_almost_full_threshold) then
almost_full_int <= '1';
......@@ -308,11 +296,9 @@ begin -- syn
wr_almost_full_o <= almost_full_int;
rd_almost_full_o <= almost_full_x;
p_reg_almost_empty : process(clk_rd_i, rst_n_i)
p_reg_almost_empty : process(clk_rd_i)
begin
if rst_n_i = '0' then
almost_empty_int <= '1';
elsif rising_edge(clk_rd_i) then
if rising_edge(clk_rd_i) then
rd_count <= std_logic_vector(unsigned(wcb.bin_x) - unsigned(rcb.bin));
if (unsigned(rd_count) <= g_almost_empty_threshold) then
almost_empty_int <= '1';
......
modules/wishbone/wb_lm32/Manifest.py
View file @ f7578270
......@@ -19,5 +19,9 @@ if(target == "altera"):
files.extend(["platform/generic/lm32_multiplier.v", "platform/altera/jtag_tap.v"]);
elif (target == "xilinx" and syn_device[0:4].upper()=="XC6S"): # Spartan6
files.extend(["platform/spartan6/lm32_multiplier.v", "platform/spartan6/jtag_tap.v"])
elif (target == "xilinx" and syn_device[0:4].upper()=="XC7K"): # Kintex7
files.extend(["platform/kintex7/lm32_multiplier.v", "platform/kintex7/jtag_tap.v"])
elif (target == "xilinx" and syn_device[0:4].upper()=="XC7Z"): # Zynq
files.extend(["platform/kintex7/lm32_multiplier.v", "platform/kintex7/jtag_tap.v"])
else:
files.extend(["platform/generic/lm32_multiplier.v", "platform/generic/jtag_tap.v"]);
modules/wishbone/wb_onewire_master/sockit_owm.v
View file @ f7578270
......@@ -276,7 +276,7 @@ end endgenerate
generate
if (CDR_E) begin
if (BDW==32) begin
always @ (posedge clk, posedge rst)
always @ (posedge clk)
if (rst) begin
cdr_n <= CDR_N[CDW-1:0];
cdr_o <= CDR_O[CDW-1:0];
......@@ -285,7 +285,7 @@ generate
if (bus_wen_cdr_o) cdr_o <= bus_wdt[31:16];
end
end else if (BDW==8) begin
always @ (posedge clk, posedge rst)
always @ (posedge clk)
if (rst) begin
cdr_n <= CDR_N[CDW-1:0];
cdr_o <= CDR_O[CDW-1:0];
......@@ -303,7 +303,7 @@ generate
endgenerate
// clock divider
always @ (posedge clk, posedge rst)
always @ (posedge clk)
if (rst) div <= {CDW{1'd0}};
else begin
if (bus_wen) div <= {CDW{1'd0}};
......@@ -320,19 +320,19 @@ assign pls = (div == (owr_ovd ? cdr_o : cdr_n));
// select and power register implementation
generate if (OWN>1) begin : sel_implementation
// port select
always @ (posedge clk, posedge rst)
always @ (posedge clk)
if (rst) owr_sel <= {SDW{1'b0}};
else if (bus_wen_pwr_sel) owr_sel <= bus_wdt[(BDW==32 ? 8 : 0)+:SDW];
// power delivery
always @ (posedge clk, posedge rst)
always @ (posedge clk)
if (rst) owr_pwr <= {OWN{1'b0}};
else if (bus_wen_pwr_sel) owr_pwr <= bus_wdt[(BDW==32 ? 16 : 4)+:OWN];
end else begin
// port select
initial owr_sel <= 'd0;
// power delivery
always @ (posedge clk, posedge rst)
always @ (posedge clk)
if (rst) owr_pwr <= 1'b0;
else if (bus_wen_ctl_sts) owr_pwr <= bus_wdt[4];
end endgenerate
......@@ -345,12 +345,12 @@ end endgenerate
assign bus_irq = irq_ena & irq_sts;
// interrupt enable
always @ (posedge clk, posedge rst)
always @ (posedge clk)
if (rst) irq_ena <= 1'b0;
else if (bus_wen_ctl_sts) irq_ena <= bus_wdt[7];
// transmit status (active after onewire cycle ends)
always @ (posedge clk, posedge rst)
always @ (posedge clk)
if (rst) irq_sts <= 1'b0;
else begin
if (bus_wen_ctl_sts) irq_sts <= 1'b0;
......@@ -365,17 +365,17 @@ end
assign req_ovd = OVD_E ? bus_wen_ctl_sts & bus_wdt[2] : 1'b0;
// overdrive
always @ (posedge clk, posedge rst)
always @ (posedge clk)
if (rst) owr_ovd <= 1'b0;
else if (bus_wen_ctl_sts) owr_ovd <= req_ovd;
// reset
always @ (posedge clk, posedge rst)
always @ (posedge clk)
if (rst) owr_rst <= 1'b0;
else if (bus_wen_ctl_sts) owr_rst <= bus_wdt[1];
// transmit data, reset, overdrive
always @ (posedge clk, posedge rst)
always @ (posedge clk)
if (rst) owr_dat <= 1'b0;
else begin
if (bus_wen_ctl_sts) owr_dat <= bus_wdt[0];
......@@ -383,7 +383,7 @@ else begin
end
// onewire cycle status
always @ (posedge clk, posedge rst)
always @ (posedge clk)
if (rst) owr_cyc <= 1'b0;
else begin
if (bus_wen_ctl_sts) owr_cyc <= bus_wdt[3] & ~&bus_wdt[2:0];
......@@ -391,7 +391,7 @@ else begin
end
// state counter (initial value depends whether the cycle is reset or data)
always @ (posedge clk, posedge rst)
always @ (posedge clk)
if (rst) cnt <= 0;
else begin
if (bus_wen_ctl_sts) cnt <= (&bus_wdt[1:0] ? t_idl : bus_wdt[1] ? t_rst : t_bit) - 1'd1;
......@@ -406,7 +406,7 @@ if (pls) begin
end
// output register (switch point depends whether the cycle is reset or data)
always @ (posedge clk, posedge rst)
always @ (posedge clk)
if (rst) owr_oen <= 1'b0;
else begin
if (bus_wen_ctl_sts) owr_oen <= ~&bus_wdt[1:0];
......
modules/wishbone/wb_uart/build_wb.sh
View file @ f7578270
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/wb_simple_uart.html -V simple_uart_wb.vhd -p simple_uart_pkg.vhd --cstyle struct -C wb_uart.h --hstyle record --lang vhdl simple_uart_wb.wb
wbgen2 -D ./doc/wb_simple_uart.html -V simple_uart_wb.vhd -p simple_uart_pkg.vhd --cstyle struct -C wb_uart.h --hstyle record --lang vhdl -n simple_uart_wb.wb
modules/wishbone/wb_uart/simple_uart_pkg.vhd
View file @ f7578270
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : simple_uart_pkg.vhd
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created : Tue Aug 15 10:16:30 2017
-- Created : Tue Jun 1 17:25:52 2021
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
......@@ -76,7 +76,7 @@ function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if x(i) = '1' then
if(x(i) = '1') then
tmp(i):= '1';
else
tmp(i):= '0';
......
modules/wishbone/wb_uart/simple_uart_wb.vhd
View file @ f7578270
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : simple_uart_wb.vhd
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created : Tue Aug 15 10:16:30 2017
-- Created : Tue Jun 1 17:25:52 2021
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
......@@ -29,6 +29,8 @@ entity simple_uart_wb is
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
rdr_rack_o : out std_logic;
host_rack_o : out std_logic;
......@@ -39,29 +41,25 @@ end simple_uart_wb;
architecture syn of simple_uart_wb is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0) := (others => '0');
signal rddata_reg : std_logic_vector(31 downto 0) := (others => '0');
signal wrdata_reg : std_logic_vector(31 downto 0) := (others => '0');
signal bwsel_reg : std_logic_vector(3 downto 0) := (others => '0');
signal rwaddr_reg : std_logic_vector(2 downto 0) := (others => '0');
signal ack_in_progress : std_logic := '0';
signal wr_int : std_logic := '0';
signal rd_int : std_logic := '0';
signal allones : std_logic_vector(31 downto 0) := (others => '0');
signal allzeros : std_logic_vector(31 downto 0) := (others => '0');
begin
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
process (clk_sys_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
regs_o.bcr_wr_o <= '0';
regs_o.tdr_tx_data_wr_o <= '0';
rdr_rack_o <= '0';
regs_o.host_tdr_data_wr_o <= '0';
host_rack_o <= '0';
elsif rising_edge(clk_sys_i) then
if rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
......@@ -310,6 +308,8 @@ begin
-- RX FIFO Count
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0';
wb_rty_o <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
modules/wishbone/wbgen2/wbgen2_eic.vhd
View file @ f7578270
......@@ -156,73 +156,76 @@ begin -- syn
irq_mode(31) <= g_irq1f_mode;
process(clk_i, rst_n_i)
process(clk_i)
begin
if(rst_n_i = '0') then
irq_i_d0 <= (others => '0');
irq_i_d1 <= (others => '0');
irq_i_d1 <= (others => '0');
irq_pending <= (others => '0');
irq_mask <= (others => '0');
elsif rising_edge(clk_i) then
for i in 0 to g_num_interrupts-1 loop
irq_i_d0(i) <= irq_i(i);
irq_i_d1(i) <= irq_i_d0(i);
irq_i_d2(i) <= irq_i_d1(i);
if((reg_isr_i(i) = '1' and reg_isr_wr_stb_i = '1') or irq_mask(i) = '0') then
irq_pending(i) <= '0';
irq_i_d0(i) <= '0';
irq_i_d1(i) <= '0';
irq_i_d2(i) <= '0';
else
case irq_mode(i) is
when c_IRQ_MODE_LEVEL_0 => irq_pending(i) <= not irq_i_d2(i);
when c_IRQ_MODE_LEVEL_1 => irq_pending(i) <= irq_i_d2(i);
when c_IRQ_MODE_RISING_EDGE => irq_pending(i) <= irq_pending(i) or ((not irq_i_d2(i)) and irq_i_d1(i));
when c_IRQ_MODE_FALLING_EDGE => irq_pending(i) <= irq_pending(i) or ((not irq_i_d1(i)) and irq_i_d2(i));
when others => null;
end case;
end if;
end loop; -- i
if(reg_ier_wr_stb_i = '1') then
for i in 0 to g_num_interrupts-1 loop
if(reg_ier_i(i) = '1') then
irq_mask(i) <= '1';
end if;
end loop;
end if;
if rising_edge(clk_i) then
if(rst_n_i = '0') then
irq_i_d0 <= (others => '0');
irq_i_d1 <= (others => '0');
irq_i_d1 <= (others => '0');
irq_pending <= (others => '0');
irq_mask <= (others => '0');
else
if(reg_idr_wr_stb_i = '1') then
for i in 0 to g_num_interrupts-1 loop
if(reg_idr_i(i) = '1') then
irq_mask(i) <= '0';
irq_i_d0(i) <= irq_i(i);
irq_i_d1(i) <= irq_i_d0(i);
irq_i_d2(i) <= irq_i_d1(i);
if((reg_isr_i(i) = '1' and reg_isr_wr_stb_i = '1') or irq_mask(i) = '0') then
irq_pending(i) <= '0';
irq_i_d0(i) <= '0';
irq_i_d1(i) <= '0';
irq_i_d2(i) <= '0';
else
case irq_mode(i) is
when c_IRQ_MODE_LEVEL_0 => irq_pending(i) <= not irq_i_d2(i);
when c_IRQ_MODE_LEVEL_1 => irq_pending(i) <= irq_i_d2(i);
when c_IRQ_MODE_RISING_EDGE => irq_pending(i) <= irq_pending(i) or ((not irq_i_d2(i)) and irq_i_d1(i));
when c_IRQ_MODE_FALLING_EDGE => irq_pending(i) <= irq_pending(i) or ((not irq_i_d1(i)) and irq_i_d2(i));
when others => null;
end case;
end if;
end loop;
end loop; -- i
if(reg_ier_wr_stb_i = '1') then
for i in 0 to g_num_interrupts-1 loop
if(reg_ier_i(i) = '1') then
irq_mask(i) <= '1';
end if;
end loop;
end if;
if(reg_idr_wr_stb_i = '1') then
for i in 0 to g_num_interrupts-1 loop
if(reg_idr_i(i) = '1') then
irq_mask(i) <= '0';
end if;
end loop;
end if;
end if;
end if;
end process;
-- generation of wb_irq_o
process(clk_i, rst_n_i)
process(clk_i)
begin
if(rst_n_i = '0') then
wb_irq_o <= '0';
elsif rising_edge(clk_i) then
if(irq_pending = std_logic_vector(to_unsigned(0, g_num_interrupts))) then
if rising_edge(clk_i) then
if(rst_n_i = '0') then
wb_irq_o <= '0';
else
wb_irq_o <= '1';
if(irq_pending = std_logic_vector(to_unsigned(0, g_num_interrupts))) then
wb_irq_o <= '0';
else
wb_irq_o <= '1';
end if;
end if;
end if;
end process;
......
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