wb_fine_pulse_gen: declare IDELAYCTRL component locally

e6f3af4c · Tomasz Wlostowski · d7d3372c · e6f3af4c
Commit e6f3af4c authored Aug 10, 2022 by Tomasz Wlostowski
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fine_pulse_gen_kintexultrascale_shared.vhd ...fine_pulse_gen/fine_pulse_gen_kintexultrascale_shared.vhd +13 -0

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--- a/modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale_shared.vhd
+++ b/modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale_shared.vhd
@@ -37,6 +37,19 @@ end fine_pulse_gen_kintexultrascale_shared;

 architecture rtl of fine_pulse_gen_kintexultrascale_shared is

+
+component IDELAYCTRL is
+  generic (
+    SIM_DEVICE : string := "7SERIES"
+  );
+
+  port(
+    RDY              : out std_ulogic;
+    REFCLK           : in  std_ulogic;
+    RST              : in  std_ulogic
+  );
+end component;
+
  component MMCME3_ADV
    generic (
      BANDWIDTH            : string  := "OPTIMIZED";