virtex6 fifo: (ug363) RSTREG cannot be used until EN_SYN is TRUE and DO_REG is 1

dcc7cc33 · Grzegorz Daniluk · de821c1d · dcc7cc33
Commit dcc7cc33 authored May 08, 2019 by Grzegorz Daniluk
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v6_hwfifo_wrapper.vhd modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd +1 -1

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--- a/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd
+++ b/modules/genrams/xilinx/virtex6/v6_hwfifo_wrapper.vhd
@@ -110,7 +110,7 @@ begin  -- syn

  srst <= not rst_n_i;

-  srstreg <= '0' when g_dual_clock = true else srst;
+  srstreg <= '0';
  
  gen_fifo36 : if(m.is_36 and m.d_width > 0) generate
    assert false report "generic_sync_fifo[xilinx]: using FIFO36E1 primitive." severity note;