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Platform-independent core collection
Commit cc5228b9 authored by Tristan Gingold's avatar Tristan Gingold
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gc_sync_word_*: use the same name to use the same constraints.

parent c99ecb4c
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Showing with 8 additions and 8 deletions
modules/common/gc_sync_word_rd.vhd
View file @ cc5228b9
......@@ -57,12 +57,12 @@ entity gc_sync_word_rd is
end entity;
architecture arch of gc_sync_word_rd is
signal gc_sync_word_rd_data :
signal gc_sync_word_data :
std_logic_vector (g_WIDTH - 1 downto 0) := (others => '0');
attribute keep : string;
attribute keep of gc_sync_word_rd_data : signal is "true";
attribute keep of gc_sync_word_data : signal is "true";
signal d_ready : std_logic;
signal wr_in : std_logic;
......@@ -84,7 +84,7 @@ begin
if rising_edge(clk_in_i) then
if d_ready = '1' then
-- Constantly update the data if ready
gc_sync_word_rd_data <= data_in_i;
gc_sync_word_data <= data_in_i;
end if;
end if;
end process;
......@@ -96,7 +96,7 @@ begin
ack_out_o <= '0';
elsif wr_in = '1' then
-- Data is stable.
data_out_o <= gc_sync_word_rd_data;
data_out_o <= gc_sync_word_data;
ack_out_o <= '1';
else
ack_out_o <= '0';
......
modules/common/gc_sync_word_wr.vhd
View file @ cc5228b9
......@@ -62,12 +62,12 @@ end entity;
architecture arch of gc_sync_word_wr is
signal gc_sync_word_wr_data :
signal gc_sync_word_data :
std_logic_vector (g_WIDTH - 1 downto 0) := (others => '0');
attribute keep : string;
attribute keep of gc_sync_word_wr_data : signal is "true";
attribute keep of gc_sync_word_data : signal is "true";
signal d_ready : std_logic;
signal wr_in : std_logic;
......@@ -96,7 +96,7 @@ begin
if rising_edge(clk_in_i) then
if d_ready = '1' and wr_in = '1' then
-- Write requested, save the input data
gc_sync_word_wr_data <= data_i;
gc_sync_word_data <= data_i;
end if;
end if;
end process p_writer;
......@@ -106,7 +106,7 @@ begin
if rising_edge(clk_out_i) then
if wr_out = '1' then
-- Data is stable.
dat_out <= gc_sync_word_wr_data;
dat_out <= gc_sync_word_data;
wr_o <= '1';
else
wr_o <= '0';
......
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