description = "- 1: IRQ output is active high\n- 0: IRQ output is active low";
prefix = "POL";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Emulate Edge sensitive output";
description = "- 1: Forces a low pulse of <code>EMU_LEN</code> clock cycles at each write to <code>EOIR</code>. Useful for edge-only IRQ controllers such as Gennum.\n- 0: Normal IRQ master line behavior";
prefix = "EMU_EDGE";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Emulated Edge pulse timer";
description = "Length of the delay (in <code>clk_sys_i</code> cycles) between write to <code>EOIR</code> and re-assertion of <code>irq_master_o</code>.";
prefix = "EMU_LEN";
type = SLV;
size = 16;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "Raw Interrupt Status Register";
prefix = "RISR";
field {
name = "Raw interrupt status";
description = "Each bit reflects the current state of corresponding IRQ input line.\n- read 1: interrupt line is currently active\n- read 0: interrupt line is inactive";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "Interrupt Enable Register";
prefix = "IER";
field {
name = "Enable IRQ";
description = "- write 1: enables interrupt associated with written bit\n- write 0: no effect";
type = PASS_THROUGH;
size = 32;
};
};
reg {
name = "Interrupt Disable Register";
prefix = "IDR";
field {
name = "Disable IRQ";
description = "- write 1: enables interrupt associated with written bit\n- write 0: no effect";
type = PASS_THROUGH;
size = 32;
};
};
reg {
name = "Interrupt Mask Register";
prefix = "IMR";
field {
name = "IRQ disabled/enabled";
description = "- read 1: interrupt associated with read bit is enabled\n- read 0: interrupt is disabled";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Vector Address Register";
prefix = "VAR";
field {
name = "Vector Address";
description = "Address of pending interrupt vector, read from Interrupt Vector Table";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Software Interrupt Register";
description = "Writing 1 to one of bits of this register causes a software emulation of the respective interrupt.";
prefix = "SWIR";
field {
name = "SWI interrupt mask";
type = PASS_THROUGH;
size = 32;
};
};
reg {
name = "End Of Interrupt Acknowledge Register";
prefix = "EOIR";
field {
name = "End of Interrupt";
description = "Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s) or releases the master interrupt output.";
type = PASS_THROUGH;
size = 32;
};
};
ram {
name = "Interrupt Vector Table";
description = "Vector Address Table. Word at offset N stores the vector address of IRQ N. When interrupt is requested, VIC reads it's vector address from this memory and stores it in VAR register. The contents of this table can be pre-initialized during synthesis through <code>g_init_vectors</code> generic parameter. This is used to auto-enumerate interrupts in SDB-based designs.";
Module implementing a 2 to 32-input prioritized interrupt controller with internal interrupt vector storage support.
children:
- reg:
name: CTL
address: 0x00000000
width: 32
access: rw
description: VIC Control Register
children:
- field:
name: ENABLE
range: 0
description: VIC Enable
comment: |
- 1: enables VIC operation
- 0: disables VIC operation
- field:
name: POL
range: 1
description: VIC output polarity
comment: |
- 1: IRQ output is active high
- 0: IRQ output is active low
x-hdl:
# Need a wire because it can be fixed.
type: wire
- field:
name: EMU_EDGE
range: 2
description: Emulate Edge sensitive output
comment: |
- 1: Forces a low pulse of <code>EMU_LEN</code> clock cycles at each write to <code>EOIR</code>. Deprecated.
- 0: Normal IRQ master line behavior
- field:
name: EMU_LEN
range: 18-3
description: Emulated Edge pulse timer
comment: |
Length of the delay (in <code>clk_sys_i</code> cycles) between write to <code>EOIR</code> and re-assertion of <code>irq_master_o</code>.
x-hdl:
write-strobe: True
- reg:
name: RISR
address: 0x00000004
width: 32
access: ro
description: Raw Interrupt Status Register
comment: |
Each bit reflects the current state of corresponding IRQ input line.
- read 1: interrupt line is currently active
- read 0: interrupt line is inactive
- reg:
name: IER
address: 0x00000008
width: 32
access: wo
description: Interrupt Enable Register
comment: |
- write 1: enables interrupt associated with written bit
- write 0: no effect
x-hdl:
type: wire
write-strobe: True
- reg:
name: IDR
address: 0x0000000c
width: 32
access: wo
description: Interrupt Disable Register
comment: |
- write 1: enables interrupt associated with written bit
- write 0: no effect
x-hdl:
type: wire
write-strobe: True
- reg:
name: IMR
address: 0x00000010
width: 32
access: ro
description: Interrupt Mask Register
comment: |
- read 1: interrupt associated with read bit is enabled
- read 0: interrupt is disabled
- reg:
name: VAR
address: 0x00000014
width: 32
access: ro
description: Vector Address Register
comment: |
Address of pending interrupt vector, read from Interrupt Vector Table
- reg:
name: SWIR
address: 0x00000018
width: 32
access: wo
description: Software Interrupt Register
comment: |
Writing 1 to one of bits of this register causes a software emulation of the respective interrupt.
x-hdl:
type: wire
write-strobe: True
- reg:
name: EOIR
address: 0x0000001c
width: 32
access: wo
description: End Of Interrupt Acknowledge Register
comment: |
Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s) or releases the master interrupt output.
x-hdl:
type: wire
write-strobe: True
- submap:
name: IVT_RAM
address: 0x00000080
size: 0x80
interface: sram
description: Interrupt Vector Table
comment: |
Vector Address Table. Word at offset N stores the vector address of IRQ N. When interrupt is requested, VIC reads it's vector address from this memory and stores it in VAR register. The contents of this table can be pre-initialized during synthesis through <code>g_init_vectors</code> generic parameter. This is used to auto-enumerate interrupts in SDB-based designs.
