@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{CODR}
@tab @code{0} @tab
Clear output pin(s)
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{CODR} @tab @bullet{} write 1: The output pin(s) corresponding to the bits written with one(s) are cleared. No effect for pins configured as inputs.@*@bullet{} write 0: no effect
@end multitable
@regsection @code{SODR} - Set Output Pin Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{SODR}
@tab @code{0} @tab
Set output pin(s)
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{SODR} @tab @bullet{} write 1: The output pin(s) corresponding to the bits written with one(s) are set. No effect for pins configured as inputs.@*@bullet{} write 0: no effect
@end multitable
@regsection @code{DDR} - Pin Direction Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{DDR}
@tab @code{0} @tab
Pin directions
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{DDR} @tab @bullet{} 1: The pin corresponding to the bit is configured as an output. @*@bullet{} 0: The pin corresponding to the bit is configured as an input.
@end multitable
@regsection @code{PSR} - Pin State Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{PSR}
@tab @code{X} @tab
Pin directions
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{PSR} @tab @bullet{} read 1: The input pin corresponding to the read bit is HIGH. @*@bullet{} read 0: The input pin(s) corresponding to the read bit is LOW.
@item @code{POL} @tab @bullet{} 1: IRQ output is active high@*@bullet{} 0: IRQ output is active low
@item @code{EMU_EDGE} @tab @bullet{} 1: Forces a low pulse of @code{EMU_LEN} clock cycles at each write to @code{EOIR}. Useful for edge-only IRQ controllers such as Gennum.@*@bullet{} 0: Normal IRQ master line behavior
@item @code{EMU_LEN} @tab Length of the delay (in @code{clk_sys_i} cycles) between write to @code{EOIR} and re-assertion of @code{irq_master_o}.
@end multitable
@regsection @code{RISR} - Raw Interrupt Status Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/O @tab
@code{RISR}
@tab @code{X} @tab
Raw interrupt status
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{RISR} @tab Each bit reflects the current state of corresponding IRQ input line.@*@bullet{} read 1: interrupt line is currently active@*@bullet{} read 0: interrupt line is inactive
Writing 1 to one of bits of this register causes a software emulation of the respective interrupt.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{SWIR}
@tab @code{0} @tab
SWI interrupt mask
@end multitable
@regsection @code{EOIR} - End Of Interrupt Acknowledge Register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab W/O @tab
@code{EOIR}
@tab @code{0} @tab
End of Interrupt
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{EOIR} @tab Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s) or releases the master interrupt output.