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Platform-independent core collection
Commit 844cc49d authored by Federico Vaga's avatar Federico Vaga
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Merge remote-tracking branch 'ohwr/svec-flash' into develop

parents abaab958 e57a80e9
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modules/axi/axi4_pkg.vhd
View file @ 844cc49d
......@@ -140,7 +140,7 @@ package axi4_pkg is
constant c_AXI4_RESP_SLVERR : std_logic_vector(1 downto 0) := "10";
constant c_AXI4_RESP_DECERR : std_logic_vector(1 downto 0) := "11";
function f_axi4_full_to_lite (
function f_axi4_full_to_lite (
f : t_axi4_full_master_out_32
) return t_axi4_lite_master_out_32;
......@@ -198,6 +198,50 @@ package axi4_pkg is
);
end component;
-- AXI4-Full interface, master output ports, 512 bits
type t_axi4_full_master_out_512 is record
ARVALID : std_logic;
AWVALID : std_logic;
BREADY : std_logic;
RREADY : std_logic;
WLAST : std_logic;
WVALID : std_logic;
ARID : std_logic_vector (11 downto 0);
AWID : std_logic_vector (11 downto 0);
ARBURST : std_logic_vector (1 downto 0);
ARLOCK : std_logic;
ARSIZE : std_logic_vector (2 downto 0);
AWBURST : std_logic_vector (1 downto 0);
AWLOCK : std_logic;
AWSIZE : std_logic_vector (2 downto 0);
ARPROT : std_logic_vector (2 downto 0);
AWPROT : std_logic_vector (2 downto 0);
ARADDR : std_logic_vector (31 downto 0);
AWADDR : std_logic_vector (31 downto 0);
WDATA : std_logic_vector (511 downto 0);
ARCACHE : std_logic_vector (3 downto 0);
ARLEN : std_logic_vector (7 downto 0);
ARQOS : std_logic_vector (3 downto 0);
AWCACHE : std_logic_vector (3 downto 0);
AWLEN : std_logic_vector (7 downto 0);
AWQOS : std_logic_vector (3 downto 0);
WSTRB : std_logic_vector (31 downto 0);
end record;
-- AXI4-Full interface, master input ports, 512 bits
type t_axi4_full_master_in_512 is record
ARREADY : std_logic;
AWREADY : std_logic;
BVALID : std_logic;
RLAST : std_logic;
RVALID : std_logic;
WREADY : std_logic;
BID : std_logic_vector (11 downto 0);
RID : std_logic_vector (11 downto 0);
BRESP : std_logic_vector (1 downto 0);
RRESP : std_logic_vector (1 downto 0);
RDATA : std_logic_vector (511 downto 0);
end record;
end package;
package body axi4_pkg is
......
modules/common/Manifest.py
View file @ 844cc49d
......@@ -42,4 +42,5 @@ files = [
"gc_async_counter_diff.vhd",
"gc_sync_word_wr.vhd",
"gc_sync_word_rd.vhd",
"gc_simple_spi_master.vhd"
];
modules/common/gc_arbitrated_mux.vhd
View file @ 844cc49d
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2019-09-09
-- Last update: 2020-09-18
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -38,7 +38,6 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity gc_arbitrated_mux is
......@@ -67,7 +66,7 @@ entity gc_arbitrated_mux is
q_valid_o : out std_logic;
-- Index of the input, to which came the currently outputted data word.
q_input_id_o : out std_logic_vector(f_log2_size(g_num_inputs)-1 downto 0)
q_input_id_o : out std_logic_vector(f_log2_ceil(g_num_inputs)-1 downto 0)
);
end gc_arbitrated_mux;
......@@ -130,7 +129,7 @@ begin -- rtl
if(unsigned(grant) /= 0) then
q_o <= dregs(f_onehot_decode(grant));
q_input_id_o <= std_logic_vector(to_unsigned(f_onehot_decode(grant), f_log2_size(g_num_inputs)));
q_input_id_o <= std_logic_vector(to_unsigned(f_onehot_decode(grant), f_log2_ceil(g_num_inputs)));
q_valid_o <= '1';
else
q_o <= (others => 'X');
......
modules/common/gc_big_adder.vhd
View file @ 844cc49d
......@@ -31,7 +31,6 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
-- Expects registers for inputs. Async outputs.
......
modules/common/gc_dyn_extend_pulse.vhd
View file @ 844cc49d
......@@ -29,7 +29,6 @@ use ieee.NUMERIC_STD.all;
library work;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity gc_dyn_extend_pulse is
generic
......
modules/common/gc_enc_8b10b.vhd
View file @ 844cc49d
This diff is collapsed.
modules/common/gc_fsm_watchdog.vhd
View file @ 844cc49d
......@@ -38,7 +38,7 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.gencores_pkg.all;
entity gc_fsm_watchdog is
generic
......@@ -66,7 +66,7 @@ architecture behav of gc_fsm_watchdog is
--============================================================================
-- Signal declarations
--============================================================================
signal wdt : unsigned(f_log2_size(g_wdt_max)-1 downto 0);
signal wdt : unsigned(f_log2_ceil(g_wdt_max)-1 downto 0);
--==============================================================================
-- architecture begin
......
modules/common/gc_moving_average.vhd
View file @ 844cc49d
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2009-09-01
-- Last update: 2017-10-11
-- Last update: 2020-04-07
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -46,7 +46,6 @@ use ieee.NUMERIC_STD.all;
library work;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity gc_moving_average is
......
modules/common/gc_simple_spi_master.vhd
View file @ 844cc49d
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-01-25
-- Last update: 2020-05-05
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -129,6 +129,7 @@ begin -- rtl
-- Waits for start of transfer command
when IDLE =>
sclk <= '0';
spi_mosi_o <= '0';
counter <= (others => '0');
if(start_i = '1') then
sreg <= data_i;
......
modules/common/gc_word_packer.vhd
View file @ 844cc49d
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2012-09-13
-- Last update: 2012-09-13
-- Last update: 2020-09-18
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -39,7 +39,7 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.gencores_pkg.all;
entity gc_word_packer is
......@@ -101,7 +101,7 @@ architecture rtl of gc_word_packer is
constant c_sreg_entries : integer := c_sreg_size / f_min(g_input_width, g_output_width);
signal sreg : std_logic_vector(c_sreg_size-1 downto 0);
signal count : unsigned(f_log2_size(c_sreg_entries + 1) - 1 downto 0);
signal count : unsigned(f_log2_ceil(c_sreg_entries + 1) - 1 downto 0);
signal empty : std_logic;
signal q_valid_comb, q_valid_reg, q_req_d0 : std_logic;
......
modules/genrams/common/inferred_sync_fifo.vhd
View file @ 844cc49d
......@@ -91,7 +91,7 @@ architecture syn of inferred_sync_fifo is
begin -- syn
legacy_mode_check: assert g_show_ahead = false or g_show_ahead_legacy_mode = false
report legacy_mode_check'instance_name & ": show-ahead enabled for sync FIFO in " &
report "inferred_sync_fifo: show-ahead enabled for sync FIFO in " &
"legacy mode. In this mode, the full flag is asserted at g_SIZE-1. if you want the " &
"full flag to be asserted at g_SIZE, then disable g_SHOW_AHEAD_LEGACY_MODE."
severity NOTE;
......
modules/wishbone/Manifest.py
View file @ 844cc49d
......@@ -27,6 +27,7 @@ modules = { "local" : [
"wb_split",
"wb16_to_wb32",
"wb_indirect",
"wb_fine_pulse_gen",
"wbgen2",
"wbgenplus",
"wb_xc7_fw_update",
......
modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
View file @ 844cc49d
......@@ -38,7 +38,7 @@ entity wb_axi4lite_bridge is
AWVALID : in std_logic;
BREADY : in std_logic;
RREADY : in std_logic;
WLAST : in std_logic;
WLAST : in std_logic := '1';
WVALID : in std_logic;
ARADDR : in std_logic_vector (31 downto 0);
AWADDR : in std_logic_vector (31 downto 0);
......
modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
View file @ 844cc49d
......@@ -54,7 +54,7 @@ architecture rtl of xwb_axi4lite_bridge is
signal state : t_state;
signal count : unsigned(10 downto 0);
begin
process(clk_sys_i)
......@@ -77,8 +77,8 @@ begin
axi4_slave_o.RRESP <= (others => 'X');
axi4_slave_o.RVALID <= '0';
axi4_slave_o.RLAST <= '0';
if(axi4_slave_i.AWVALID = '1') then
if (axi4_slave_i.AWVALID = '1') then
state <= ISSUE_WRITE;
wb_master_o.adr <= axi4_slave_i.AWADDR;
elsif (axi4_slave_i.ARVALID = '1') then
......@@ -87,12 +87,10 @@ begin
end if;
when ISSUE_WRITE =>
axi4_slave_o.WREADY <= '1';
wb_master_o.cyc <= '1';
wb_master_o.we <= '1';
if(axi4_slave_i.WVALID = '1') then
axi4_slave_o.WREADY <= '1';
if (axi4_slave_i.WVALID = '1') then
wb_master_o.stb <= '1';
wb_master_o.sel <= axi4_slave_i.WSTRB;
wb_master_o.dat <= axi4_slave_i.WDATA;
......@@ -100,7 +98,6 @@ begin
end if;
when ISSUE_READ =>
wb_master_o.cyc <= '1';
wb_master_o.stb <= '1';
wb_master_o.we <= '0';
......@@ -109,11 +106,11 @@ begin
state <= COMPLETE_READ;
when COMPLETE_READ =>
if(wb_master_i.stall = '0') then
if (wb_master_i.stall = '0') then
wb_master_o.stb <= '0';
if(wb_master_i.ack = '1') then
if (wb_master_i.ack = '1') then
state <= IDLE;
axi4_slave_o.RRESP <= c_AXI4_RESP_EXOKAY;
axi4_slave_o.RRESP <= c_AXI4_RESP_OKAY;
axi4_slave_o.RDATA <= wb_master_i.dat;
axi4_slave_o.RVALID <= '1';
axi4_slave_o.RLAST <= '1';
......@@ -124,13 +121,13 @@ begin
end if;
end if;
when COMPLETE_WRITE =>
if(wb_master_i.stall = '0') then
if (wb_master_i.stall = '0') then
wb_master_o.stb <= '0';
if(wb_master_i.ack = '1') then
if (wb_master_i.ack = '1') then
state <= RESPONSE_WRITE;
axi4_slave_o.BRESP <= c_AXI4_RESP_EXOKAY;
axi4_slave_o.BVALID <= '1';
axi4_slave_o.BRESP <= c_AXI4_RESP_OKAY;
wb_master_o.cyc <= '0';
else
state <= WAIT_ACK_WRITE;
......@@ -138,29 +135,30 @@ begin
end if;
end if;
when WAIT_ACK_WRITE =>
if(wb_master_i.ack = '1') then
if (wb_master_i.ack = '1') then
state <= RESPONSE_WRITE;
axi4_slave_o.BRESP <= c_AXI4_RESP_EXOKAY;
axi4_slave_o.BVALID <= '1';
axi4_slave_o.BRESP <= c_AXI4_RESP_OKAY;
wb_master_o.cyc <= '0';
elsif count = c_timeout then
state <= RESPONSE_WRITE;
axi4_slave_o.BVALID <= '1';
axi4_slave_o.BRESP <= c_AXI4_RESP_SLVERR;
wb_master_o.cyc <= '0';
end if;
count <= count + 1;
when WAIT_ACK_READ =>
if(wb_master_i.ack = '1') then
state <= IDLE;
axi4_slave_o.RRESP <= c_AXI4_RESP_EXOKAY;
if (wb_master_i.ack = '1') then
state <= RESPONSE_READ;
axi4_slave_o.RRESP <= c_AXI4_RESP_OKAY;
axi4_slave_o.RVALID <= '1';
axi4_slave_o.RLAST <= '1';
axi4_slave_o.RDATA <= wb_master_i.dat;
wb_master_o.cyc <= '0';
elsif count = c_timeout then
state <= IDLE;
state <= RESPONSE_READ;
axi4_slave_o.RRESP <= c_AXI4_RESP_SLVERR;
axi4_slave_o.RVALID <= '1';
axi4_slave_o.RLAST <= '1';
......@@ -169,23 +167,19 @@ begin
end if;
count <= count + 1;
when RESPONSE_WRITE =>
if (axi4_slave_i.BREADY = '1') then
axi4_slave_o.BVALID <= '1';
axi4_slave_o.BVALID <= '0';
state <= IDLE;
end if;
when RESPONSE_READ => null;
when RESPONSE_READ =>
if (axi4_slave_i.RREADY = '1') then
axi4_slave_o.RVALID <= '0';
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
end rtl;
modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.cheby
View file @ 844cc49d
......@@ -19,8 +19,12 @@ memory-map:
children:
- field:
name: data
description: temperature
description: temperature value
range: 15-0
- field:
name: error
description: temperature is not valid
range: 31
- reg:
name: status
description: status
......@@ -35,3 +39,7 @@ memory-map:
name: id_ok
description: Set when unique id was read, persist after reset
range: 1
- field:
name: temp_ok
description: Set when the temperature register is correctly read
range: 2
modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.vhd
View file @ 844cc49d
-- Do not edit. Generated on Wed Sep 30 11:24:49 2020 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- --gen-hdl wb_ds182x_regs.vhd -i wb_ds182x_regs.cheby
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......@@ -14,49 +19,64 @@ entity wb_ds182x_regs is
id_i : in std_logic_vector(63 downto 0);
-- temperature
-- temperature value
temperature_data_i : in std_logic_vector(15 downto 0);
-- temperature is not valid
temperature_error_i : in std_logic;
-- status
-- Set when unique id was read
status_id_read_i : in std_logic;
-- Set when unique id was read, persist after reset
status_id_ok_i : in std_logic
status_id_ok_i : in std_logic;
-- Set when the temperature register is correctly read
status_temp_ok_i : in std_logic
);
end wb_ds182x_regs;
architecture syn of wb_ds182x_regs is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal adr_int : std_logic_vector(3 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(3 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
begin
-- WB decode signals
adr_int <= wb_i.adr(3 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wb_rip <= '0';
elsif rising_edge(clk_i) then
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wb_wip <= '0';
elsif rising_edge(clk_i) then
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
......@@ -64,113 +84,97 @@ begin
wb_o.rty <= '0';
wb_o.err <= '0';
-- Assign outputs
-- pipelining for wr-in+rd-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wr_req_d0 <= '0';
else
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_adr_d0 <= adr_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
end if;
end if;
end process;
-- Register id
-- Register temperature
-- Register status
-- Process for write requests.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wr_ack_int <= '0';
elsif rising_edge(clk_i) then
wr_ack_int <= '0';
case wb_i.adr(3 downto 3) is
when "0" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register id
when "1" =>
-- Register id
when others =>
wr_ack_int <= wr_int;
end case;
when "1" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register temperature
when "1" =>
-- Register status
when others =>
wr_ack_int <= wr_int;
end case;
process (wr_adr_d0, wr_req_d0) begin
case wr_adr_d0(3 downto 3) is
when "0" =>
case wr_adr_d0(2 downto 2) is
when "0" =>
-- Reg id
wr_ack_int <= wr_req_d0;
when "1" =>
-- Reg id
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_int;
wr_ack_int <= wr_req_d0;
end case;
end if;
end process;
-- Process for registers read.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
rd_ack1_int <= '0';
reg_rdat_int <= (others => 'X');
elsif rising_edge(clk_i) then
reg_rdat_int <= (others => '0');
case wb_i.adr(3 downto 3) is
when "0" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- id
reg_rdat_int <= id_i(63 downto 32);
rd_ack1_int <= rd_int;
when "1" =>
-- id
reg_rdat_int <= id_i(31 downto 0);
rd_ack1_int <= rd_int;
when others =>
rd_ack1_int <= rd_int;
end case;
when "1" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- temperature
reg_rdat_int(15 downto 0) <= temperature_data_i;
rd_ack1_int <= rd_int;
when "1" =>
-- status
reg_rdat_int(0) <= status_id_read_i;
reg_rdat_int(1) <= status_id_ok_i;
rd_ack1_int <= rd_int;
when others =>
rd_ack1_int <= rd_int;
end case;
when "1" =>
case wr_adr_d0(2 downto 2) is
when "0" =>
-- Reg temperature
wr_ack_int <= wr_req_d0;
when "1" =>
-- Reg status
wr_ack_int <= wr_req_d0;
when others =>
rd_ack1_int <= rd_int;
wr_ack_int <= wr_req_d0;
end case;
end if;
when others =>
wr_ack_int <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
process (adr_int, rd_req_int, id_i, temperature_data_i, temperature_error_i, status_id_read_i, status_id_ok_i, status_temp_ok_i) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
case wb_i.adr(3 downto 3) is
when "0" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- id
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "1" =>
-- id
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
rd_dat_d0 <= (others => 'X');
case adr_int(3 downto 3) is
when "0" =>
case adr_int(2 downto 2) is
when "0" =>
-- Reg id
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= id_i(63 downto 32);
when "1" =>
-- Reg id
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= id_i(31 downto 0);
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
when "1" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- temperature
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "1" =>
-- status
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "1" =>
case adr_int(2 downto 2) is
when "0" =>
-- Reg temperature
rd_ack_d0 <= rd_req_int;
rd_dat_d0(15 downto 0) <= temperature_data_i;
rd_dat_d0(30 downto 16) <= (others => '0');
rd_dat_d0(31) <= temperature_error_i;
when "1" =>
-- Reg status
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= status_id_read_i;
rd_dat_d0(1) <= status_id_ok_i;
rd_dat_d0(2) <= status_temp_ok_i;
rd_dat_d0(31 downto 3) <= (others => '0');
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
end process;
end syn;
modules/wishbone/wb_ds182x_readout/xwb_ds182x_readout.vhd
View file @ 844cc49d
......@@ -48,6 +48,8 @@ architecture arch of xwb_ds182x_readout is
signal temper : std_logic_vector(15 downto 0); -- temperature value (refreshed every second)
signal id_read : std_logic; -- id_o value is valid_o
signal id_ok : std_logic; -- Same as id_read_o, but not reset with rst_n_i
signal temp_ok : std_logic;
signal temp_err : std_logic;
begin
i_readout: entity work.gc_ds182x_readout
generic map (
......@@ -60,19 +62,24 @@ begin
onewire_b => onewire_b,
id_o => id,
temper_o => temper,
temp_ok_o => temp_ok,
id_read_o => id_read,
id_ok_o => id_ok);
temp_err <= not temp_ok;
i_regs: entity work.wb_ds182x_regs
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
wb_i => wb_i,
wb_o => wb_o,
id_i => id,
temperature_data_i => temper,
temperature_error_i => temp_err,
status_id_read_i => id_read,
status_id_ok_i => id_ok
status_id_ok_i => id_ok,
status_temp_ok_i => temp_ok
);
end arch;
modules/wishbone/wb_fine_pulse_gen/Manifest.py 0 → 100644
View file @ 844cc49d
files = [
"fine_pulse_gen_kintex7_shared.vhd",
"fine_pulse_gen_kintexultrascale_shared.vhd",
"fine_pulse_gen_kintex7.vhd",
"fine_pulse_gen_kintexultrascale.vhd",
"fine_pulse_gen_wbgen2_pkg.vhd",
"fine_pulse_gen_wb.vhd",
"xwb_fine_pulse_gen.vhd"]
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintex7.vhd 0 → 100644
View file @ 844cc49d
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
library unisim;
use unisim.VCOMPONENTS.all;
entity fine_pulse_gen_kintex7 is
generic (
g_sim_delay_tap_ps : integer := 30;
g_ref_clk_freq : real := 125.0;
g_use_odelay : boolean := false
);
port
(
clk_par_i : in std_logic;
clk_serdes_i : in std_logic;
rst_serdes_i : in std_logic;
rst_sys_n_i : in std_logic;
cont_i : in std_logic;
pol_i : in std_logic;
coarse_i : in std_logic_vector(7 downto 0);
trig_p_i : in std_logic;
pulse_o : out std_logic;
dly_load_i : in std_logic;
dly_fine_i : in std_logic_vector(4 downto 0)
);
end fine_pulse_gen_kintex7;
architecture rtl of fine_pulse_gen_kintex7 is
signal par_data : std_logic_vector(7 downto 0);
signal dout_predelay, dout_prebuf, dout_nodelay : std_logic;
signal odelay_load : std_logic;
signal rst : std_logic;
signal odelay_ntaps : std_logic_vector(4 downto 0);
signal trig_d : std_logic;
-- function f_gen_bitmask (coarse : std_logic_vector; pol : std_logic; cont : std_logic) return std_logic_vector is
-- variable rv : std_logic_vector(15 downto 0);
-- begin
-- end f_gen_bitmask;
signal mask : std_logic_vector(15 downto 0);
signal flip : std_logic;
signal dly_load_d : std_logic;
begin
rst <= not rst_sys_n_i;
process(clk_par_i)
variable rv : std_logic_vector(15 downto 0);
begin
if rising_edge(clk_par_i) then
dly_load_d <= dly_load_i;
if dly_load_i = '1' then
odelay_ntaps <= dly_fine_i;
if cont_i = '1' then
case coarse_i is
when x"00" =>
rv := "1111000011110000";
when x"01" =>
rv := "0111100001111000";
when x"02" =>
rv := "0011110000111100";
when x"03" =>
rv := "0001111000011110";
when x"04" =>
rv := "0000111100001111";
when x"05" =>
rv := "1000011110000111";
when x"06" =>
rv := "1100001111000011";
when x"07" =>
rv := "1110000111100001";
when others =>
rv := (others => '0');
end case;
else
case coarse_i is
when x"00" =>
rv := "1111000000000000";
when x"01" =>
rv := "0111100000000000";
when x"02" =>
rv := "0011110000000000";
when x"03" =>
rv := "0001111000000000";
when x"04" =>
rv := "0000111100000000";
when x"05" =>
rv := "0000011110000000";
when x"06" =>
rv := "0000001111000000";
when x"07" =>
rv := "0000000111100000";
when others =>
rv := (others => '0');
end case;
end if;
if pol_i = '0' then
mask <= rv;
else
mask <= not rv;
end if;
end if;
odelay_load <= dly_load_i or dly_load_d;
trig_d <= trig_p_i;
if trig_p_i = '1' then
par_data <= mask(15 downto 8);
flip <= '0';
elsif trig_d = '1' then
par_data <= mask(7 downto 0);
else
if cont_i = '1' then
if flip = '1' then
par_data <= mask(7 downto 0);
else
par_data <= mask(15 downto 8);
end if;
else
if pol_i = '1' then
par_data <= (others => '1');
else
par_data <= (others => '0');
end if;
end if;
end if;
end if;
end process;
U_Serdes : OSERDESE2
generic map (
DATA_RATE_OQ => "SDR",
DATA_RATE_TQ => "SDR",
DATA_WIDTH => 8,
TRISTATE_WIDTH => 1,
SERDES_MODE => "MASTER")
port map (
D1 => par_data(7),
D2 => par_data(6),
D3 => par_data(5),
D4 => par_data(4),
D5 => par_data(3),
D6 => par_data(2),
D7 => par_data(1),
D8 => par_data(0),
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
OCE => '1',
CLK => clk_serdes_i,
CLKDIV => clk_par_i,
OFB => dout_predelay,
OQ => dout_nodelay,
TBYTEIN => '0',
TCE => '0',
RST => rst_serdes_i);
gen_with_odelay : if g_use_odelay generate
U_Delay : ODELAYE2
generic map (
CINVCTRL_SEL => "FALSE",
DELAY_SRC => "ODATAIN",
HIGH_PERFORMANCE_MODE => "TRUE",
ODELAY_TYPE => "VAR_LOAD",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => g_ref_clk_freq,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => dout_prebuf,
CLKIN => '0',
C => clk_par_i,
CE => '0',
INC => '0',
ODATAIN => dout_predelay,
LD => odelay_load,
REGRST => rst_serdes_i,
LDPIPEEN => '0',
CNTVALUEIN => odelay_ntaps,
CINVCTRL => '0'
);
end generate gen_with_odelay;
gen_without_odelay : if not g_use_odelay generate
dout_prebuf <= dout_nodelay;
end generate gen_without_odelay;
pulse_o <= dout_prebuf;
-- gen_output_diff : if g_use_diff_output generate
-- U_OBuf : OBUFDS
-- generic map(
-- IOSTANDARD => "LVDS_25",
-- SLEW => "FAST")
-- port map(
-- O => pulse_p_o,
-- OB => pulse_n_o,
-- I => dout_prebuf);
-- end generate gen_output_diff;
end rtl;
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintex7_shared.vhd 0 → 100644
View file @ 844cc49d
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.VCOMPONENTS.all;
entity fine_pulse_gen_kintex7_shared is
generic (
g_global_use_odelay : boolean;
g_use_external_serdes_clock : boolean
);
port (
-- PLL async reset
pll_rst_i : in std_logic;
clk_ser_ext_i : in std_logic;
-- 62.5 MHz reference
clk_ref_i : in std_logic;
-- serdes parallel clock
clk_par_o : out std_logic;
-- serdes serial clock
clk_ser_o : out std_logic;
clk_odelay_o : out std_logic;
pll_locked_o : out std_logic
);
end fine_pulse_gen_kintex7_shared;
architecture rtl of fine_pulse_gen_kintex7_shared is
signal pll_locked : std_logic;
signal clk_fb_pll, clk_fb_pll_bufg, clk_iodelay, clk_iodelay_bufg : std_logic;
begin
pll_iodelay_map : PLLE2_ADV
generic map(
BANDWIDTH => ("HIGH"),
COMPENSATION => ("ZHOLD"),
STARTUP_WAIT => ("FALSE"),
DIVCLK_DIVIDE => (1),
CLKFBOUT_MULT => (16),
CLKFBOUT_PHASE => (0.000),
CLKOUT0_DIVIDE => (5), -- 200 MHz
CLKOUT0_PHASE => (0.000),
CLKOUT0_DUTY_CYCLE => (0.500),
CLKOUT1_DIVIDE => (2), -- 500 MHz
CLKOUT1_PHASE => (0.000),
CLKOUT1_DUTY_CYCLE => (0.500),
CLKIN1_PERIOD => (16.000))
port map(
CLKFBOUT => clk_fb_pll,
CLKOUT0 => clk_iodelay,
CLKOUT1 => clk_ser_o,
-- Input clock control
CLKFBIN => clk_fb_pll_bufg,
CLKIN1 => clk_ref_i,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
PWRDWN => '0',
RST => pll_rst_i,
LOCKED => pll_locked_o
);
clk_par_o <= clk_ref_i;
int_bufg : BUFG
port map (
O => clk_fb_pll_bufg,
I => clk_fb_pll
);
gen_with_iodelay : if g_global_use_odelay generate
int_bufg_clkiodelay : BUFG
port map (
O => clk_iodelay_bufg,
I => clk_iodelay
);
IDELAYCTRL_inst : IDELAYCTRL
port map (
RDY => open, -- 1-bit output: Ready output
REFCLK => clk_iodelay_bufg, -- 1-bit input: Reference clock input
RST => '0' -- 1-bit input: Active high reset input
);
clk_odelay_o <= clk_iodelay_bufg;
end generate gen_with_iodelay;
end rtl;
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale_shared.vhd 0 → 100644
View file @ 844cc49d
library ieee;
use ieee.std_logic_1164.all;
use work.gencores_pkg.all;
library unisim;
use unisim.VCOMPONENTS.all;
entity fine_pulse_gen_kintexultrascale_shared is
generic (
g_global_use_odelay : boolean;
g_use_external_serdes_clock : boolean
);
port (
-- PLL async reset
pll_rst_i : in std_logic;
odelayctrl_rst_i : in std_logic;
clk_ser_ext_i : in std_logic;
-- 62.5 MHz reference
clk_ref_i : in std_logic;
-- serdes parallel clock
clk_par_o : out std_logic;
-- serdes serial clock
clk_ser_o : out std_logic;
clk_odelay_o : out std_logic;
pll_locked_o : out std_logic;
odelayctrl_rdy_o : out std_logic
);
end fine_pulse_gen_kintexultrascale_shared;
architecture rtl of fine_pulse_gen_kintexultrascale_shared is
component MMCME3_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT_F : real := 5.000;
CLKFBOUT_PHASE : real := 0.000;
CLKFBOUT_USE_FINE_PS : string := "FALSE";
CLKIN1_PERIOD : real := 0.000;
CLKIN2_PERIOD : real := 0.000;
CLKOUT0_DIVIDE_F : real := 1.000;
CLKOUT0_DUTY_CYCLE : real := 0.500;
CLKOUT0_PHASE : real := 0.000;
CLKOUT0_USE_FINE_PS : string := "FALSE";
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.500;
CLKOUT1_PHASE : real := 0.000;
CLKOUT1_USE_FINE_PS : string := "FALSE";
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.500;
CLKOUT2_PHASE : real := 0.000;
CLKOUT2_USE_FINE_PS : string := "FALSE";
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.500;
CLKOUT3_PHASE : real := 0.000;
CLKOUT3_USE_FINE_PS : string := "FALSE";
CLKOUT4_CASCADE : string := "FALSE";
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.500;
CLKOUT4_PHASE : real := 0.000;
CLKOUT4_USE_FINE_PS : string := "FALSE";
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.500;
CLKOUT5_PHASE : real := 0.000;
CLKOUT5_USE_FINE_PS : string := "FALSE";
CLKOUT6_DIVIDE : integer := 1;
CLKOUT6_DUTY_CYCLE : real := 0.500;
CLKOUT6_PHASE : real := 0.000;
CLKOUT6_USE_FINE_PS : string := "FALSE";
COMPENSATION : string := "AUTO";
DIVCLK_DIVIDE : integer := 1;
IS_CLKFBIN_INVERTED : bit := '0';
IS_CLKIN1_INVERTED : bit := '0';
IS_CLKIN2_INVERTED : bit := '0';
IS_CLKINSEL_INVERTED : bit := '0';
IS_PSEN_INVERTED : bit := '0';
IS_PSINCDEC_INVERTED : bit := '0';
IS_PWRDWN_INVERTED : bit := '0';
IS_RST_INVERTED : bit := '0';
REF_JITTER1 : real := 0.010;
REF_JITTER2 : real := 0.010;
SS_EN : string := "FALSE";
SS_MODE : string := "CENTER_HIGH";
SS_MOD_PERIOD : integer := 10000;
STARTUP_WAIT : string := "FALSE"
);
port (
CDDCDONE : out std_ulogic;
CLKFBOUT : out std_ulogic;
CLKFBOUTB : out std_ulogic;
CLKFBSTOPPED : out std_ulogic;
CLKINSTOPPED : out std_ulogic;
CLKOUT0 : out std_ulogic;
CLKOUT0B : out std_ulogic;
CLKOUT1 : out std_ulogic;
CLKOUT1B : out std_ulogic;
CLKOUT2 : out std_ulogic;
CLKOUT2B : out std_ulogic;
CLKOUT3 : out std_ulogic;
CLKOUT3B : out std_ulogic;
CLKOUT4 : out std_ulogic;
CLKOUT5 : out std_ulogic;
CLKOUT6 : out std_ulogic;
DO : out std_logic_vector(15 downto 0);
DRDY : out std_ulogic;
LOCKED : out std_ulogic;
PSDONE : out std_ulogic;
CDDCREQ : in std_ulogic;
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PSCLK : in std_ulogic;
PSEN : in std_ulogic;
PSINCDEC : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
component BUFG is
port (
O : out std_ulogic;
I : in std_ulogic
);
end component BUFG;
signal clk_ser_prebuf, mmcm_clk_fb_prebuf, mmcm_clk_fb : std_logic;
signal clk_odelay_prebuf, clk_odelay, clk_par_prebuf : std_logic;
begin
gen_use_odelay : if g_global_use_odelay generate
b_idelayctrl: block
attribute IODELAY_GROUP: string;
attribute IODELAY_GROUP of U_IDELAYCTRL_Fine_Pulse_Gen : label is "IODELAY_FPGen";
signal rst_synced : std_logic;
begin
U_Sync_Reset : gc_sync_ffs
port map (
clk_i => clk_odelay,
rst_n_i => '1',
data_i => odelayctrl_rst_i,
synced_o => rst_synced
);
U_IDELAYCTRL_Fine_Pulse_Gen : IDELAYCTRL
generic map (
SIM_DEVICE => "ULTRASCALE" -- Must be set to "ULTRASCALE"
)
port map (
RDY => odelayctrl_rdy_o,
REFCLK => clk_odelay,
RST => odelayctrl_rst_i
);
end block;
end generate gen_use_odelay;
gen_use_Ext_serdes_clock : if g_use_external_serdes_clock generate
-- stub for the moment
clk_ser_o <= clk_ser_ext_i;
clk_par_o <= clk_ref_i;
pll_locked_o <= '1';
end generate gen_use_Ext_serdes_clock;
gen_use_int_serdes_clock : if not g_use_external_serdes_clock generate
U_MMCM : MMCME3_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- Jitter programming (HIGH, LOW, OPTIMIZED)
COMPENSATION => "AUTO", -- AUTO, BUF_IN, EXTERNAL, INTERNAL, ZHOLD
STARTUP_WAIT => "FALSE", -- Delays DONE until MMCM is locked (FALSE, TRUE)
CLKOUT4_CASCADE => "FALSE",
-- CLKIN_PERIOD: Input clock period in ns units, ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => 16.0,
CLKFBOUT_MULT_F => 16.0, -- Multiply value for all CLKOUT (2.000-64.000)
DIVCLK_DIVIDE => 1, -- Master division value (1-106)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000)
CLKFBOUT_USE_FINE_PS => "FALSE",
CLKOUT0_DIVIDE_F => 2.0, -- clk_ser: 500 MHz
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT0_PHASE => 0.0,
CLKOUT1_DIVIDE => 8, -- clk_par: 125 MHz
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_PHASE => 0.0,
CLKOUT2_DIVIDE => 4, -- clk_odelay: 250 MHz
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT2_PHASE => 0.0,
CLKOUT0_USE_FINE_PS => "FALSE",
CLKOUT1_USE_FINE_PS => "FALSE"
)
port map (
-- Clock Inputs inputs: Clock inputs
CLKIN1 => clk_ref_i,
CLKIN2 => '0',
-- Clock Outputs outputs: User configurable clock outputs
CLKOUT0 => clk_ser_prebuf,
CLKOUT1 => clk_par_prebuf,
CLKOUT2 => clk_odelay_prebuf,
-- Feedback
CLKFBOUT => mmcm_clk_fb_prebuf,
CLKFBIN => mmcm_clk_fb,
-- Status Ports outputs: MMCM status ports
LOCKED => pll_locked_o,
CDDCREQ => '0',
-- Control Ports inputs: MMCM control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => pll_rst_i,
-- DRP Ports inputs: Dynamic reconfiguration ports
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
-- Dynamic Phase Shift Ports inputs: Ports used for dynamic phase shifting of the outputs
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0'
);
u_buf_mmcm_fb : BUFG
port map (
I => mmcm_clk_fb_prebuf,
O => mmcm_clk_fb);
u_buf_mmcm_ser : BUFG
port map (
I => clk_ser_prebuf,
O => clk_ser_o);
u_buf_mmcm_par : BUFG
port map (
I => clk_par_prebuf,
O => clk_par_o);
u_buf_mmcm_odelay : BUFG
port map (
I => clk_odelay_prebuf,
O => clk_odelay);
clk_odelay_o <= clk_odelay;
end generate gen_use_int_serdes_clock;
end rtl;
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_wb.vhd 0 → 100644
View file @ 844cc49d
This diff is collapsed.
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_wb.wb 0 → 100644
View file @ 844cc49d
This diff is collapsed.
modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd 0 → 100644
View file @ 844cc49d
This diff is collapsed.
modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
View file @ 844cc49d
......@@ -691,50 +691,6 @@ port map(
D_CYC_O => D_CYC,
D_CTI_O => D_CTI);
end generate gen_profile_full_debug;
gen_profile_wr_node: if (g_profile = "wr_node") generate
U_Wrapped_LM32: lm32_top_wr_node
generic map (
eba_reset => g_reset_vector,
sdb_address => g_sdb_address)
port map(
clk_i => clk_sys_i,
rst_i => rst,
interrupt => irq_i,
-- Pass slave responses through unmodified
I_DAT_I => strip_undefined(iwb_i.DAT),
I_ACK_I => iwb_i.ACK,
I_ERR_I => iwb_i.ERR,
I_RTY_I => iwb_i.RTY,
D_DAT_I => strip_undefined(dwb_i.DAT),
D_ACK_I => dwb_i.ACK,
D_ERR_I => dwb_i.ERR,
D_RTY_I => dwb_i.RTY,
-- Writes can only happen as a single cycle
I_DAT_O => iwb_o.DAT,
D_DAT_O => dwb_o.DAT,
I_WE_O => iwb_o.WE,
D_WE_O => dwb_o.WE,
-- SEL /= 1111 only for single cycles
I_SEL_O => iwb_o.SEL,
D_SEL_O => dwb_o.SEL,
-- We can ignore BTE as we know it's always linear burst mode
I_BTE_O => open,
D_BTE_O => open,
-- Lock is never flagged by LM32. Besides, WBv4 locks intercon on CYC.
I_LOCK_O => open,
D_LOCK_O => open,
-- The LM32 has STB=CYC always
I_STB_O => open,
D_STB_O => open,
-- We monitor these pins to direct the adapter's logic
I_ADR_O => I_ADR,
I_CYC_O => I_CYC,
I_CTI_O => I_CTI,
D_ADR_O => D_ADR,
D_CYC_O => D_CYC,
D_CTI_O => D_CTI);
end generate gen_profile_wr_node;
-- Cycle durations always match in our adapter
iwb_o.CYC <= I_CYC;
......
modules/wishbone/wb_uart/build_wb.sh
View file @ 844cc49d
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/wb_simple_uart.html -V simple_uart_wb.vhd -p simple_uart_pkg.vhd --cstyle struct -C wb_uart.h --hstyle record --lang vhdl simple_uart_wb.wb
wbgen2 -D ./doc/wb_simple_uart.html -V simple_uart_wb.vhd -p simple_uart_pkg.vhd -K ../../../testbench/wishbone/include/wb_uart_regs.vh --cstyle defines -C wb_uart.h --hstyle record --lang vhdl simple_uart_wb.wb
modules/wishbone/wb_uart/simple_uart_wb.vhd
View file @ 844cc49d
This diff is collapsed.
modules/wishbone/wb_uart/simple_uart_wb.wb
View file @ 844cc49d
......@@ -28,9 +28,84 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX FIFO supported";
description = "1: UART supports RX FIFO";
prefix = "RX_FIFO_SUPPORTED";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TX FIFO supported";
description = "1: UART supports TX FIFO";
prefix = "TX_FIFO_SUPPORTED";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX FIFO data valid";
description = "1: there's some data in the RX FIFO";
prefix = "RX_FIFO_VALID";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TX FIFO empty";
description = "1: TX FIFO is empty";
prefix = "TX_FIFO_EMPTY";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TX FIFO full";
description = "1: TX FIFO is full";
prefix = "TX_FIFO_FULL";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX FIFO overflow";
description = "1: RX FIFO overflow occured (latched bit, write 1 to clear)";
prefix = "RX_FIFO_OVERFLOW";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "RX FIFO data count";
description = "Number of bytes currently in the RX FIFO";
prefix = "RX_FIFO_BYTES";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Baudrate control register";
description = "Register controlling the UART baudrate";
......@@ -122,4 +197,28 @@ peripheral {
access_bus=READ_ONLY;
};
};
};
\ No newline at end of file
reg {
name = "UART General Control Register";
prefix = "CR";
field {
name = "RX FIFO purge";
description = "write 1: clears RX FIFO";
prefix = "RX_FIFO_PURGE";
type = MONOSTABLE;
};
field {
name = "TX FIFO purge";
description = "write 1: clears TX FIFO";
prefix = "TX_FIFO_PURGE";
type = MONOSTABLE;
};
};
};
modules/wishbone/wb_uart/wb_simple_uart.vhd
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modules/wishbone/wb_uart/xwb_simple_uart.vhd
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......@@ -39,9 +39,14 @@ entity xwb_simple_uart is
generic (
g_WITH_VIRTUAL_UART : boolean := TRUE;
g_WITH_PHYSICAL_UART : boolean := TRUE;
g_WITH_PHYSICAL_UART_FIFO : boolean := false;
g_TX_FIFO_SIZE : integer := 0;
g_RX_FIFO_SIZE : integer := 0;
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_VUART_FIFO_SIZE : integer := 1024);
g_VUART_FIFO_SIZE : integer := 1024;
g_PRESET_BCR : integer := 0
);
port (
clk_sys_i : in std_logic;
......@@ -68,7 +73,11 @@ begin -- arch
g_WITH_PHYSICAL_UART => g_WITH_PHYSICAL_UART,
g_INTERFACE_MODE => g_INTERFACE_MODE,
g_ADDRESS_GRANULARITY => g_ADDRESS_GRANULARITY,
g_VUART_FIFO_SIZE => g_VUART_FIFO_SIZE)
g_VUART_FIFO_SIZE => g_VUART_FIFO_SIZE,
g_WITH_PHYSICAL_UART_FIFO => g_WITH_PHYSICAL_UART_FIFO,
g_TX_FIFO_SIZE => g_TX_FIFO_SIZE,
g_RX_FIFO_SIZE => g_RX_FIFO_SIZE,
g_PRESET_BCR => g_PRESET_BCR)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......
modules/wishbone/wishbone_pkg.vhd
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sim/vhdl/sim_wishbone.vhd
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software/spi-ocores/drivers/spi/spi-ocores.c
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......@@ -481,6 +481,12 @@ static int spi_ocores_sw_xfer_next_init(struct spi_ocores *sp)
else
hz = sp->master->cur_msg->spi->max_speed_hz;
divider = (sp->clock_hz / (hz * 2)) - 1;
if (WARN_ON(divider == 0)) {
dev_warn(&sp->master->dev, "divider value is 0\n");
divider =1;
}
spi_ocores_hw_xfer_config(sp, ctrl, divider);
......
testbench/common/gc_ds182x_readout/Manifest.py 0 → 100644
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testbench/common/gc_ds182x_readout/gc_ds182x_readout_tb.vhd 0 → 100644
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testbench/wishbone/include/wb_fine_pulse_gen_regs.vh 0 → 100644
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testbench/wishbone/wb_fine_pulse_gen/Manifest.py 0 → 100644
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testbench/wishbone/wb_fine_pulse_gen/main.sv 0 → 100644
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testbench/wishbone/wb_spi/Manifest.py 0 → 100644
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action = "simulation"
target = "generic"
sim_top = "tb_spi"
sim_tool = "modelsim"
modules = { "local" : ["../../../", "../../../sim/vhdl"] };
files = ["tb_spi.vhd"]
testbench/wishbone/wb_spi/run.do 0 → 100644
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testbench/wishbone/wb_uart/Manifest.py 0 → 100644
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testbench/wishbone/wb_uart/main.sv 0 → 100644
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testbench/wishbone/wb_uart/run.do 0 → 100644
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testbench/wishbone/wb_uart/wave.do 0 → 100644
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tools/gen_sourceid.py
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