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Commit 78020ea3 authored by A. Hahn's avatar A. Hahn
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ftm4: removed pcie core generated files

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platform/altera/wb_pcie/arria10gx_ftm4_pcie_hip/arria10gx_ftm4_pcie_hip/altera_pcie_a10_hip_181/synth/altpcie_reset_delay_sync.v deleted 100644 → 0
View file @ 735d0f96
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
module altpcie_reset_delay_sync #(
parameter ACTIVE_RESET = 0,
parameter WIDTH_RST = 1,
parameter NODENAME = "altpcie_reset_delay_sync",// Expecting Instance name
parameter LOCK_TIME_CNT_WIDTH = 1
) (
input clk,
input async_rst,
output reg [WIDTH_RST-1:0] sync_rst /* synthesis preserve */
);
wire sync_rst_clk;
localparam SDC={"-name SDC_STATEMENT \"set_false_path -from [get_fanins -async *", NODENAME ,"*rs_meta\[*\]] -to [get_keepers *", NODENAME ,"*rs_meta\[*\]]\" "};
(* altera_attribute = SDC *)
reg [2:0] rs_meta = (ACTIVE_RESET==0)?3'b000:3'b111 /* synthesis preserve dont_replicate */;
// synthesis translate_off
initial begin
sync_rst[WIDTH_RST-1:0]={WIDTH_RST{1'b0}};
$display("INFO: altpcie_reset_delay_sync::---------------------------------------------------------------------------------------------");
$display("INFO: altpcie_reset_delay_sync:: NODENAME is %s", NODENAME);
$display("INFO: altpcie_reset_delay_sync:: SDC is %s", SDC);
rs_meta = (ACTIVE_RESET==0)?3'b000:3'b111;
end
// synthesis translate_on
always @(posedge clk) begin
sync_rst[WIDTH_RST-1:0] <= {WIDTH_RST{sync_rst_clk}};
end
generate begin : g_rstsync
if (ACTIVE_RESET==0) begin : g_rstsync
always @(posedge clk or negedge async_rst) begin
if (!async_rst) rs_meta <= 3'b000;
else rs_meta <= {rs_meta[1:0],1'b1};
end
if (LOCK_TIME_CNT_WIDTH>1) begin : g_rstsync1
wire ready_sync = rs_meta[2];
reg [LOCK_TIME_CNT_WIDTH-1:0] cntr = {LOCK_TIME_CNT_WIDTH{1'b0}} /* synthesis preserve */;
assign sync_rst_clk = cntr[LOCK_TIME_CNT_WIDTH-1];
always @(posedge clk) begin
sync_rst[WIDTH_RST-1:0] <= {WIDTH_RST{sync_rst_clk}};
end
always @(posedge clk or negedge ready_sync) begin
if (!ready_sync) cntr <= {LOCK_TIME_CNT_WIDTH{1'b0}};
else if (!sync_rst_clk) cntr <= cntr + 1'b1;
end
end
else begin : g_rstsync2
assign sync_rst_clk = rs_meta[2];
end
end
else begin : g_rstsync3 // ACTIVE_RESET=1
always @(posedge clk or posedge async_rst) begin
if (async_rst) rs_meta <= 3'b111;
else rs_meta <= {rs_meta[1:0],1'b0};
end
if (LOCK_TIME_CNT_WIDTH>1) begin : g_rstsync4
wire ready_sync = rs_meta[2];
wire sync_rst_clkn ;
reg [LOCK_TIME_CNT_WIDTH-1:0] cntr = {LOCK_TIME_CNT_WIDTH{1'b0}} /* synthesis preserve */;
assign sync_rst_clk=~sync_rst_clk;
assign sync_rst_clkn = cntr[LOCK_TIME_CNT_WIDTH-1];
always @(posedge clk or posedge ready_sync) begin
if (ready_sync) cntr <= {LOCK_TIME_CNT_WIDTH{1'b0}};
else if (!sync_rst_clkn) cntr <= cntr + 1'b1;
end
end
else begin : g_rstsync5
assign sync_rst_clk = rs_meta[2];
end
end
end
endgenerate
endmodule
platform/altera/wb_pcie/arria10gx_ftm4_pcie_hip/arria10gx_ftm4_pcie_hip/altera_pcie_a10_hip_181/synth/altpcie_rs_a10_hip.v deleted 100644 → 0
View file @ 735d0f96
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Complementary HIP reset logic (hiprst) used along with the
// HIP hard reset controller
//
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
module altpcie_rs_a10_hip (
input pld_clk,
input dlup_exit,
input hotrst_exit,
input l2_exit,
input npor_core,
input [4: 0] ltssm,
output reg hiprst
);
localparam [4:0] LTSSM_POL = 5'b00010;
localparam [4:0] LTSSM_CPL = 5'b00011;
localparam [4:0] LTSSM_DET = 5'b00000;
localparam [4:0] LTSSM_RCV = 5'b01100;
localparam [4:0] LTSSM_DIS = 5'b10000;
localparam [4:0] LTSSM_DETA = 5'b00001;
localparam [4:0] LTSSM_DETQ = 5'b00000;
reg hiprst_r;
wire npor_sync ;
reg dlup_exit_r;
reg exits_r;
reg hotrst_exit_r;
reg l2_exit_r;
reg [4: 0] rsnt_cntn;
reg [4: 0] ltssm_r;
reg [4: 0] ltssm_rr;
//reset Synchronizer
altpcie_reset_delay_sync #(
.ACTIVE_RESET (0),
.WIDTH_RST (1),
.NODENAME ("npor_sync_altpcie_reset_delay_sync_altpcie_rs_a10_hip"),
.LOCK_TIME_CNT_WIDTH (1)
) npor_sync_altpcie_reset_delay_sync_altpcie_rs_a10_hip(
.clk (pld_clk),
.async_rst (npor_core),
.sync_rst (npor_sync)
);
//Reset delay
always @(posedge pld_clk or negedge npor_sync) begin
if (npor_sync == 1'b0) begin
rsnt_cntn <= 5'h0;
end
else if (exits_r == 1'b1) begin
rsnt_cntn <= 5'd10;
end
else if (rsnt_cntn != 5'd20) begin
rsnt_cntn <= rsnt_cntn + 5'h1;
end
end
//sync and config reset
always @(posedge pld_clk or negedge npor_sync) begin
if (npor_sync == 1'b0) begin
hiprst_r <= 1'b1;
end
else begin
if (exits_r == 1'b1) begin
hiprst_r <= 1'b1;
end
else if (rsnt_cntn == 5'd20) begin
hiprst_r <= 1'b0;
end
end
end
always @(posedge pld_clk or negedge npor_sync) begin
if (npor_sync == 1'b0) begin
dlup_exit_r <= 1'b1;
hotrst_exit_r <= 1'b1;
l2_exit_r <= 1'b1;
exits_r <= 1'b0;
hiprst <= 1'b1;
ltssm_r <= LTSSM_DETQ;
ltssm_rr <= LTSSM_DETQ;
end
else begin
ltssm_r <= ltssm;
ltssm_rr <= ltssm_r;
hiprst <= hiprst_r;
dlup_exit_r <= dlup_exit;
hotrst_exit_r <= hotrst_exit;
l2_exit_r <= l2_exit;
exits_r <= ((l2_exit_r == 1'b0)||(hotrst_exit_r == 1'b0)||(dlup_exit_r == 1'b0)||(ltssm_r == LTSSM_DIS))?1'b1:1'b0;
end
end
endmodule
platform/altera/wb_pcie/arria10gx_ftm4_pcie_hip/arria10gx_ftm4_pcie_hip/altera_pcie_a10_hip_181/synth/altpcie_sc_bitsync.v deleted 100644 → 0
View file @ 735d0f96
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
module altpcie_sc_bitsync
#(
parameter DWIDTH = 1, // Sync Data input
parameter NODENAME = "altpcie_sc_bitsync", // Expecting Instance name
parameter SYNCSTAGE = 2, // Sync stages
parameter SDC_TYPE = 0, // 0: Multi Cycle=3, 1:Multi Cycle=2, 2: Set False Path
parameter RESET_VAL = 0 // Reset value
)
(
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in
output wire [DWIDTH-1:0] data_out // data out
);
localparam SYNCSTAGE_INT=SYNCSTAGE-1;
// set of handy SDC constraints
localparam MULTI_2 = {"-name SDC_STATEMENT \"set_multicycle_path -to [get_keepers *" , NODENAME , "*altpcie_sc_bitsync_meta_dff\[*\]] 2\" "};
localparam MULTI_3 = {"-name SDC_STATEMENT \"set_multicycle_path -to [get_keepers *" , NODENAME , "*altpcie_sc_bitsync_meta_dff\[*\]] 3\" "};
localparam FPATH = {"-name SDC_STATEMENT \"set_false_path -to [get_keepers *" , NODENAME , "*altpcie_sc_bitsync_meta_dff\[*\]]\" "};
localparam FHOLD = {"-name SDC_STATEMENT \"set_false_path -hold -to [get_keepers *", NODENAME , "*altpcie_sc_bitsync_meta_dff\[*\]]\" "};
localparam SDC = (SDC_TYPE==0)?{MULTI_3,";",FHOLD}:(SDC_TYPE==1)?{MULTI_2,";",FHOLD}:{FPATH ,";",FHOLD};
// synthesis translate_off
initial begin
$display("INFO: altpcie_sc_bitsync::---------------------------------------------------------------------------------------------");
$display("INFO: altpcie_sc_bitsync:: NODENAME is %s", NODENAME);
$display("INFO: altpcie_sc_bitsync:: SDC is %s", SDC);
end
// synthesis translate_on
// Define wires/regs
(* altera_attribute = SDC *)
reg [DWIDTH-1:0] altpcie_sc_bitsync_meta_dff;
wire reset_value;
assign reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0; // To eliminate truncating warning
generate begin : g_bitsync
if (SYNCSTAGE==2) begin : g_bitsync2
// Sync Always block
// Sync Always block
reg [DWIDTH-1:0] sync_regs;
reg [DWIDTH-1:0] sync_regsb;
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
sync_regs[DWIDTH-1:0] <= {(DWIDTH){reset_value}};
sync_regsb[DWIDTH-1:0] <= {(DWIDTH){reset_value}};
end
else begin
sync_regs[DWIDTH-1:0] <= altpcie_sc_bitsync_meta_dff;
sync_regsb[DWIDTH-1:0] <= sync_regs[DWIDTH-1:0] ;
end
end
assign data_out[DWIDTH-1:0] = sync_regsb[DWIDTH-1:0];
end
else if (SYNCSTAGE==3) begin : g_bitsync3
// Sync Always block
// Sync Always block
reg [DWIDTH-1:0] sync_regs;
reg [DWIDTH-1:0] sync_regsb;
reg [DWIDTH-1:0] sync_regsc;
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
sync_regs[DWIDTH-1:0] <= {(DWIDTH){reset_value}};
sync_regsb[DWIDTH-1:0] <= {(DWIDTH){reset_value}};
sync_regsc[DWIDTH-1:0] <= {(DWIDTH){reset_value}};
end
else begin
sync_regs[DWIDTH-1:0] <= altpcie_sc_bitsync_meta_dff;
sync_regsb[DWIDTH-1:0] <= sync_regs[DWIDTH-1:0] ;
sync_regsc[DWIDTH-1:0] <= sync_regsb[DWIDTH-1:0] ;
end
end
assign data_out[DWIDTH-1:0] = sync_regsc[DWIDTH-1:0];
end
else begin : g_bitsync4
// Sync Always block
reg [DWIDTH-1:0] sync_regs;
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
sync_regs[DWIDTH-1:0] <= {(DWIDTH){reset_value}};
end
else begin
sync_regs[DWIDTH-1:0] <= altpcie_sc_bitsync_meta_dff;
end
end
assign data_out[DWIDTH-1:0] = sync_regs[DWIDTH-1:0];
end
end
endgenerate
// Separated out the first stage of FFs without reset
always @(posedge clk) begin
altpcie_sc_bitsync_meta_dff[DWIDTH-1:0] <= data_in;
end
endmodule // altpcie_sc_bitsync
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
module altpcie_sc_bitsync_node
#(
parameter DWIDTH = 1, // Sync Data input
parameter NODENAME = "altpcie_sc_bitsync_node", // Instance name
parameter SYNCSTAGE = 2, // Sync stages
parameter SDC_TYPE = 0, // 0: Multi Cycle=3, 1:Multi Cycle=2, 2: Set False Path
parameter RESET_VAL = 0 // Reset value
)
(
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in
output wire [DWIDTH-1:0] data_out // data out
);
altpcie_sc_bitsync #(
.DWIDTH ( DWIDTH ),// Sync Data input
.NODENAME ( NODENAME ),// Sync stages
.SYNCSTAGE ( SYNCSTAGE ),// 0: Multi Cycle=3, 1:Multi Cycle=2, 2: Set False Path
.SDC_TYPE ( SDC_TYPE ),// Instance name
.RESET_VAL ( RESET_VAL ) // Reset value
) altpcie_sc_bitsync (
.clk (clk ),// clock
.rst_n (rst_n ),// async reset
.data_in (data_in ),// data in
.data_out (data_out ) // data out
);
endmodule //altpcie_sc_bitsync_node
platform/altera/wb_pcie/arria10gx_ftm4_pcie_hip/arria10gx_ftm4_pcie_hip/altera_pcie_a10_hip_181/synth/fpll_g1g2xn_cfg.v deleted 100644 → 0
View file @ 735d0f96
config fpll_g1g2xn_cfg;
design fpll_g1g2xn;
instance fpll_g1g2xn.fpll_g1g2xn use arria10gx_ftm4_pcie_hip_altera_xcvr_fpll_a10_181.altera_xcvr_fpll_a10;
endconfig
platform/altera/wb_pcie/arria10gx_ftm4_pcie_hip/arria10gx_ftm4_pcie_hip/altera_pcie_a10_hip_181/synth/phy_g1x4_cfg.v deleted 100644 → 0
View file @ 735d0f96
config phy_g1x4_cfg;
design phy_g1x4;
instance phy_g1x4.phy_g1x4 use arria10gx_ftm4_pcie_hip_altera_xcvr_native_a10_181.arria10gx_ftm4_pcie_hip_altera_xcvr_native_a10_181_7zb32zq;
endconfig
platform/altera/wb_pcie/arria10gx_ftm4_pcie_hip/arria10gx_ftm4_pcie_hip/altera_pcie_a10_hip_181/synth/skp_det_g3.v deleted 100644 → 0
View file @ 735d0f96
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
module skp_det_g3 (
input [31:0] rxdata,
input rxstartblock,
input [1:0] rxsynchdr,
input rxvalid,
input rxdatavalid,
input rate_g3,
input core_clk,
input core_rst_n,
output reg skp_pat_det_g3_ps //pulse stretched SKP pattern detect indicator
);
wire skp_pat_det_g3_sb;
wire skp_pat_det_g3_d;
wire skp_end_det_g3;
wire false_skp_det;
reg [1:0] skp_pat_det_g3;
//reg skp_pat_det_g3_ps;
reg skp_pat_det_g3_sb_dly;
reg skp_pat_det_g3_d_dly;
reg [1:0] rxsynchdr_ext;
//detect Arria 10 Gen3 block aligner SKP error pattern. SKP pattern detected during data block
assign skp_pat_det_g3_sb = ((rxdata[31:0] == 32'haaaa_aaaa) & rxstartblock & (rxsynchdr[1:0] == 2'b10) & rxvalid); //Detect start of SKP in scrambled data when syn header is datablk
assign skp_pat_det_g3_d = ((rxdata[31:0] == 32'haaaa_aaaa) & (rxsynchdr_ext[1:0] == 2'b10) & rxvalid & rxdatavalid); //Detect next cycle of scrambled data looking like a SKP
assign skp_end_det_g3 = (rxdata[7:0] == 8'he1) & (rxsynchdr_ext[1:0] == 2'b10) & rxvalid & rxdatavalid;
//assign false_skp_det = ~(k_g3_skp_det_dis) & (skp_pat_det_g3_sb_dly & skp_pat_det_g3_d) | (skp_pat_det_g3_d_dly & skp_end_det_g3); //first two cycles of a 32-bit SKP OS detected in a datablock
//assign false_skp_det = (skp_pat_det_g3_sb_dly & skp_pat_det_g3_d) | (skp_pat_det_g3_d_dly & skp_end_det_g3); //first two cycles of a 32-bit SKP OS detected in a datablock
assign false_skp_det = (skp_pat_det_g3_sb_dly & skp_pat_det_g3_d) | (skp_pat_det_g3_sb_dly & skp_end_det_g3); //first two cycles of a 32-bit SKP OS detected in a datablock
always @ (posedge core_clk or negedge core_rst_n) begin
if(!core_rst_n) begin
skp_pat_det_g3[1:0] <= 2'b00;
skp_pat_det_g3_ps <= 1'b0;
skp_pat_det_g3_sb_dly <= 1'b0;
skp_pat_det_g3_d_dly <= 1'b0;
rxsynchdr_ext <= 2'b00;
end
else begin
skp_pat_det_g3_sb_dly <= rxvalid ? skp_pat_det_g3_sb : skp_pat_det_g3_sb_dly;
skp_pat_det_g3_d_dly <= skp_pat_det_g3_d;
skp_pat_det_g3[1:0] <= {skp_pat_det_g3[0], false_skp_det};
skp_pat_det_g3_ps <= (skp_pat_det_g3[1] | skp_pat_det_g3[0] | false_skp_det ); //pulse stretch output for 3 cycles (6ns worst case @ 500MHz)
rxsynchdr_ext[1:0] <= (rxstartblock==1'b1) ? rxsynchdr[1:0] : rxsynchdr_ext[1:0];
end
end
endmodule
\ No newline at end of file
platform/altera/wb_pcie/arria10gx_ftm4_pcie_hip/arria10gx_ftm4_pcie_hip/altera_xcvr_fpll_a10_181/synth/alt_xcvr_pll_embedded_debug.sv deleted 100644 → 0
View file @ 735d0f96
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_xcvr_pll_embedded_debug #(
parameter dbg_capability_reg_enable = 0,
parameter dbg_user_identifier = 0,
parameter dbg_stat_soft_logic_enable = 0,
parameter dbg_ctrl_soft_logic_enable = 0,
parameter en_master_cgb = 0
) (
// avmm signals
input avmm_clk,
input avmm_reset,
input [8:0] avmm_address,
input [7:0] avmm_writedata,
input avmm_write,
input avmm_read,
output [7:0] avmm_readdata,
output avmm_waitrequest,
// input signals from the core
input in_pll_powerdown,
input in_pll_locked,
input in_pll_cal_busy,
input in_avmm_busy,
// output signals to the ip
output out_pll_powerdown
);
wire prbs_done_sync;
wire csr_prbs_snapshot;
wire csr_prbs_count_en;
wire csr_prbs_reset;
wire [47:0] prbs_err_count;
wire [47:0] prbs_bit_count;
alt_xcvr_pll_avmm_csr #(
.dbg_capability_reg_enable ( dbg_capability_reg_enable ),
.dbg_user_identifier ( dbg_user_identifier ),
.dbg_stat_soft_logic_enable ( dbg_stat_soft_logic_enable ),
.dbg_ctrl_soft_logic_enable ( dbg_ctrl_soft_logic_enable ),
.en_master_cgb ( en_master_cgb)
) embedded_debug_soft_csr (
// avmm signals
.avmm_clk (avmm_clk),
.avmm_reset (avmm_reset),
.avmm_address (avmm_address),
.avmm_writedata (avmm_writedata),
.avmm_write (avmm_write),
.avmm_read (avmm_read),
.avmm_readdata (avmm_readdata),
.avmm_waitrequest (avmm_waitrequest),
// input status signals from the channel
.pll_powerdown (in_pll_powerdown),
.pll_locked (in_pll_locked),
.pll_cal_busy (in_pll_cal_busy),
.avmm_busy (in_avmm_busy),
// output control signals
.csr_pll_powerdown (out_pll_powerdown)
);
endmodule
platform/altera/wb_pcie/arria10gx_ftm4_pcie_hip/arria10gx_ftm4_pcie_hip/altera_xcvr_fpll_a10_181/synth/plain_files.txt deleted 100644 → 0
View file @ 735d0f96
./twentynm_xcvr_avmm.sv
./alt_xcvr_resync.sv
./altera_xcvr_fpll_a10.sv
./a10_avmm_h.sv
./alt_xcvr_native_avmm_nf.sv
./alt_xcvr_pll_embedded_debug.sv
./alt_xcvr_pll_avmm_csr.sv
platform/altera/wb_pcie/arria10gx_ftm4_pcie_hip/arria10gx_ftm4_pcie_hip/altera_xcvr_native_a10_181/synth/plain_files.txt deleted 100644 → 0
View file @ 735d0f96
./alt_xcvr_resync.sv
./alt_xcvr_arbiter.sv
./twentynm_pcs.sv
./twentynm_pma.sv
./twentynm_xcvr_avmm.sv
./twentynm_xcvr_native.sv
./altera_xcvr_native_a10_functions_h.sv
./a10_avmm_h.sv
./alt_xcvr_native_pipe_retry.sv
./alt_xcvr_native_avmm_csr.sv
./alt_xcvr_native_prbs_accum.sv
./alt_xcvr_native_odi_accel.sv
./alt_xcvr_native_rcfg_arb.sv
./altera_xcvr_native_pcie_dfe_params_h.sv
./pcie_mgmt_commands_h.sv
./pcie_mgmt_functions_h.sv
./pcie_mgmt_program.sv
./pcie_mgmt_cpu.sv
./pcie_mgmt_master.sv
./altera_xcvr_native_pcie_dfe_ip.sv
platform/altera/wb_pcie/arria10gx_ftm4_pcie_hip/arria10gx_ftm4_pcie_hip/synth/arria10gx_ftm4_pcie_hip_cfg.v deleted 100644 → 0
View file @ 735d0f96
config arria10gx_ftm4_pcie_hip_cfg;
design arria10gx_ftm4_pcie_hip;
instance arria10gx_ftm4_pcie_hip.pcie_a10_hip_0 use arria10gx_ftm4_pcie_hip_altera_pcie_a10_hip_181.arria10gx_ftm4_pcie_hip_altera_pcie_a10_hip_181_hyz2b2a;
endconfig
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