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Platform-independent core collection
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Platform-independent core collection
Commits
65f4fe8e
Commit
65f4fe8e
authored
Aug 18, 2020
by
Mathias Kreider
Committed by
A. Hahn
Sep 15, 2020
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Fixed UARTs too short delay between RX read and ACK
parent
f9ad7336
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simple_uart_wb.vhd
modules/wishbone/wb_uart/simple_uart_wb.vhd
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modules/wishbone/wb_uart/simple_uart_wb.vhd
View file @
65f4fe8e
...
...
@@ -223,7 +223,7 @@ begin
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_sreg
(
1
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"100"
=>
if
(
wb_we_i
=
'1'
)
then
...
...
@@ -277,7 +277,7 @@ begin
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_sreg
(
1
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
...
...
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