Commit 64f7e518 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

sim: create accessor object to WB master interface as singleton

parent fcca65bf
...@@ -298,10 +298,14 @@ class CIWBMasterAccessor extends CWishboneAccessor; ...@@ -298,10 +298,14 @@ class CIWBMasterAccessor extends CWishboneAccessor;
endclass // CIWBMasterAccessor endclass // CIWBMasterAccessor
CIWBMasterAccessor theAccessor;
initial
theAccessor = new;
function automatic CIWBMasterAccessor get_accessor(); function automatic CIWBMasterAccessor get_accessor();
automatic CIWBMasterAccessor tmp; return theAccessor;
tmp = new;
return tmp;
endfunction // get_accessor endfunction // get_accessor
always@(posedge clk_i) always@(posedge clk_i)
......
...@@ -9,12 +9,16 @@ virtual class CWishboneAccessor extends CBusAccessor; ...@@ -9,12 +9,16 @@ virtual class CWishboneAccessor extends CBusAccessor;
protected wb_cycle_type_t m_cycle_type; protected wb_cycle_type_t m_cycle_type;
function new(); function new();
$display("NEW");
m_cycle_type = CLASSIC; m_cycle_type = CLASSIC;
m_default_xfer_size = 4; m_default_xfer_size = 4;
endfunction // new endfunction // new
virtual task set_mode(wb_cycle_type_t mode); virtual task automatic set_mode(wb_cycle_type_t mode);
m_cycle_type = mode; m_cycle_type = mode;
$display("SET MODE %d", mode );
endtask // set_mode endtask // set_mode
...@@ -29,18 +33,18 @@ virtual class CWishboneAccessor extends CBusAccessor; ...@@ -29,18 +33,18 @@ virtual class CWishboneAccessor extends CBusAccessor;
// RANDOM - event occurs randomly with probability (prob) // RANDOM - event occurs randomly with probability (prob)
// These two can be combined (random events occuring after a certain initial delay) // These two can be combined (random events occuring after a certain initial delay)
// DELAYED events can be repeated (rep_rate parameter) // DELAYED events can be repeated (rep_rate parameter)
virtual task add_event(wba_sim_event_t evt, wba_sim_behavior_t behv, int dly_start, real prob, int rep_rate); virtual task automatic add_event(wba_sim_event_t evt, wba_sim_behavior_t behv, int dly_start, real prob, int rep_rate);
endtask // add_event endtask // add_event
// [slave only] gets a cycle from the queue // [slave only] gets a cycle from the queue
virtual task get(ref wb_cycle_t xfer); virtual task automatic get(ref wb_cycle_t xfer);
endtask // get endtask // get
// [master only] executes a cycle and returns its result // [master only] executes a cycle and returns its result
virtual task put(ref wb_cycle_t xfer); virtual task automatic put(ref wb_cycle_t xfer);
endtask // put endtask // put
...@@ -49,7 +53,7 @@ virtual class CWishboneAccessor extends CBusAccessor; ...@@ -49,7 +53,7 @@ virtual class CWishboneAccessor extends CBusAccessor;
endfunction // idle endfunction // idle
// [master only] generic write(s), blocking // [master only] generic write(s), blocking
virtual task writem(uint64_t addr[], uint64_t data[], int size = 4, ref int result = _null); virtual task automatic writem(uint64_t addr[], uint64_t data[], int size = 4, ref int result = _null);
wb_cycle_t cycle; wb_cycle_t cycle;
int i; int i;
...@@ -74,11 +78,13 @@ virtual class CWishboneAccessor extends CBusAccessor; ...@@ -74,11 +78,13 @@ virtual class CWishboneAccessor extends CBusAccessor;
endtask // write endtask // write
// [master only] generic read(s), blocking // [master only] generic read(s), blocking
virtual task readm(uint64_t addr[], ref uint64_t data[],input int size = 4, ref int result = _null); virtual task automatic readm(uint64_t addr[], ref uint64_t data[],input int size = 4, ref int result = _null);
wb_cycle_t cycle; wb_cycle_t cycle;
int i; int i;
cycle.ctype = m_cycle_type; cycle.ctype = m_cycle_type;
$display("CYCLE CTYPE %d %d", cycle.ctype, m_cycle_type );
cycle.rw = 1'b0; cycle.rw = 1'b0;
for(i=0;i < addr.size(); i++) for(i=0;i < addr.size(); i++)
...@@ -99,7 +105,7 @@ virtual class CWishboneAccessor extends CBusAccessor; ...@@ -99,7 +105,7 @@ virtual class CWishboneAccessor extends CBusAccessor;
endtask // readm endtask // readm
virtual task read(uint64_t addr, ref uint64_t data, input int size = 4, ref int result = _null); virtual task automatic read(uint64_t addr, ref uint64_t data, input int size = 4, ref int result = _null);
uint64_t aa[], da[]; uint64_t aa[], da[];
aa = new[1]; aa = new[1];
da = new[1]; da = new[1];
...@@ -108,7 +114,7 @@ virtual class CWishboneAccessor extends CBusAccessor; ...@@ -108,7 +114,7 @@ virtual class CWishboneAccessor extends CBusAccessor;
data = da[0]; data = da[0];
endtask endtask
virtual task write(uint64_t addr, uint64_t data, int size = 4, ref int result = _null); virtual task automatic write(uint64_t addr, uint64_t data, int size = 4, ref int result = _null);
uint64_t aa[], da[]; uint64_t aa[], da[];
aa = new[1]; aa = new[1];
da = new[1]; da = new[1];
......
...@@ -24,10 +24,10 @@ virtual class CBusAccessor; ...@@ -24,10 +24,10 @@ virtual class CBusAccessor;
pure virtual task writem(uint64_t addr[], uint64_t data[], input int size, ref int result); pure virtual task automatic writem(uint64_t addr[], uint64_t data[], input int size, ref int result);
pure virtual task readm(uint64_t addr[], ref uint64_t data[], input int size, ref int result); pure virtual task automatic readm(uint64_t addr[], ref uint64_t data[], input int size, ref int result);
virtual task read(uint64_t addr, ref uint64_t data, input int size = m_default_xfer_size, ref int result = _null); virtual task automatic read(uint64_t addr, ref uint64_t data, input int size = m_default_xfer_size, ref int result = _null);
int res; int res;
uint64_t aa[1], da[]; uint64_t aa[1], da[];
...@@ -39,7 +39,7 @@ virtual class CBusAccessor; ...@@ -39,7 +39,7 @@ virtual class CBusAccessor;
endtask endtask
virtual task write(uint64_t addr, uint64_t data, input int size = m_default_xfer_size, ref int result = _null); virtual task automatic write(uint64_t addr, uint64_t data, input int size = m_default_xfer_size, ref int result = _null);
uint64_t aa[1], da[1]; uint64_t aa[1], da[1];
aa[0] = addr; aa[0] = addr;
da[0] = data; da[0] = data;
......
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