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Platform-independent core collection
Commit 61ca3f49 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: Eradicate INT from wishbone records and peripheral ports. 

For the few peripherals where it was being used (eg. uart, spi, etc) the output port
has been renamed to "int_o".

The only peripheral that was not touched is "wb_eic.vhd", because this one is being used
by wbgen, and it would require users to update their wbgen tool as well. So, until a new
tool is introduced, wbgen-generated interrupt controllers will have an output port called
wb_int_o".
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Showing with 68 additions and 165 deletions
modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
View file @ 61ca3f49
......@@ -114,7 +114,6 @@ begin
wb_in.err <= wb_err;
wb_in.rty <= wb_rty;
wb_in.ack <= wb_ack;
wb_in.int <= '0';
wb_in.stall <= wb_stall;
wb_in.dat <= wb_dat_s2m;
......
modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
View file @ 61ca3f49
......@@ -219,5 +219,4 @@ begin
end if;
end process;
slave_o.int <= '0'; -- TODO: not implemented
end rtl;
modules/wishbone/wb_crossbar/sdb_rom.vhd
View file @ 61ca3f49
......@@ -140,7 +140,6 @@ begin
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.stall <= '0';
slave_o.int <= '0'; -- Tom sucks! This should not be here.
s_adr <= unsigned(slave_i.adr(c_rom_depth+c_rom_lowbits-1 downto c_rom_lowbits));
s_sel <= unsigned(f_msi_flag_index(master_i));
......
modules/wishbone/wb_crossbar/xwb_crossbar.vhd
View file @ 61ca3f49
......@@ -6,7 +6,7 @@
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2011-06-08
-- Last update: 2018-03-14
-- Last update: 2018-03-19
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -374,8 +374,7 @@ architecture rtl of xwb_crossbar is
ERR => vector_OR(ERR_row),
RTY => vector_OR(RTY_row),
STALL => not vector_OR(STALL_row),
DAT => master_matrix_OR(DAT_matrix),
INT => '0');
DAT => master_matrix_OR(DAT_matrix));
end master_logic;
begin
-- The virtual error slave is pretty straight-forward:
......@@ -387,8 +386,7 @@ begin
ERR => virtual_ERR,
RTY => '0',
STALL => '0',
DAT => (others => '0'),
INT => '0');
DAT => (others => '0'));
virtual_error_slave : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
......
modules/wishbone/wb_dpram/xwb_dpram.vhd
View file @ 61ca3f49
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : CERN
-- Created : 2011-02-15
-- Last update: 2017-02-03
-- Last update: 2018-03-08
-- Platform : FPGA-generics
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -178,8 +178,6 @@ begin
slave2_out.err <= '0';
slave1_out.rty <= '0';
slave2_out.rty <= '0';
slave1_out.int <= '0';
slave2_out.int <= '0';
end struct;
modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
View file @ 61ca3f49
......@@ -5,7 +5,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2018-03-14
-- Last update: 2018-03-19
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -331,7 +331,6 @@ begin
wb_out.ack <= ack_int;
wb_out.stall <= '0';
wb_out.err <= '0';
wb_out.int <= '0';
wb_out.rty <='0';
end behavioral;
......
modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
View file @ 61ca3f49
......@@ -5,7 +5,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2017-10-11
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -113,7 +113,6 @@ begin -- rtl
gpio_oen_o => gpio_oen_o);
slave_o.err <= '0';
slave_o.int <= '0';
slave_o.rty <= '0';
end rtl;
modules/wishbone/wb_i2c_master/i2c_master_top.vhd
View file @ 61ca3f49
......@@ -100,7 +100,8 @@ entity i2c_master_top is
wb_stb_i : in std_logic; -- Strobe signals / core select signal
wb_cyc_i : in std_logic; -- Valid bus cycle input
wb_ack_o : out std_logic; -- Bus cycle acknowledge output
wb_inta_o : out std_logic := '0'; -- interrupt request output signal
inta_o : out std_logic := '0'; -- interrupt request output signal
-- i2c lines
scl_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0); -- i2c clock line input
......@@ -373,13 +374,13 @@ begin
gen_irq: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
wb_inta_o <= '0';
inta_o <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
wb_inta_o <= '0';
inta_o <= '0';
else
-- interrupt signal is only generated when IEN (interrupt enable bit) is set
wb_inta_o <= irq_flag and ien;
inta_o <= irq_flag and ien;
end if;
end if;
end process gen_irq;
......
modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
View file @ 61ca3f49
......@@ -5,7 +5,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2013-09-09
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -50,9 +50,10 @@ entity wb_i2c_master is
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
int_o : out std_logic;
scl_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0); -- i2c clock line input
scl_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0); -- i2c clock line output
scl_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0); -- i2c clock line output enable, active low
......@@ -78,7 +79,7 @@ architecture rtl of wb_i2c_master is
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_inta_o : out std_logic;
inta_o : out std_logic;
scl_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
scl_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
scl_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0);
......@@ -120,8 +121,7 @@ begin
sl_we_i => wb_we_i,
sl_dat_o => wb_dat_o,
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o,
sl_int_o => wb_int_o);
sl_stall_o => wb_stall_o);
rst <= not rst_n_i;
......@@ -140,7 +140,7 @@ begin
wb_stb_i => wb_in.stb,
wb_cyc_i => wb_in.cyc,
wb_ack_o => wb_out.ack,
wb_inta_o => wb_out.int,
inta_o => int_o,
scl_pad_i => scl_pad_i,
scl_pad_o => scl_pad_o,
scl_padoen_o => scl_padoen_o,
......
modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
View file @ 61ca3f49
......@@ -22,6 +22,8 @@ entity xwb_i2c_master is
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
int_o : out std_logic;
scl_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0); -- i2c clock line input
scl_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0); -- i2c clock line output
scl_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0); -- i2c clock line output enable, active low
......@@ -33,32 +35,6 @@ end xwb_i2c_master;
architecture rtl of xwb_i2c_master is
component wb_i2c_master
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_num_interfaces : integer := 1);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
scl_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
scl_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
scl_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0);
sda_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
sda_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
sda_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0));
end component;
begin -- rtl
......@@ -78,8 +54,8 @@ begin -- rtl
wb_cyc_i => slave_i.cyc,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_int_o => slave_o.int,
wb_stall_o => slave_o.stall,
int_o => int_o,
scl_pad_i => scl_pad_i,
scl_pad_o => scl_pad_o,
scl_padoen_o => scl_padoen_o,
......
modules/wishbone/wb_irq/wb_irq_master.vhd
View file @ 61ca3f49
......@@ -6,7 +6,7 @@
-- Author : Mathias Kreider
-- Company : GSI
-- Created : 2013-08-10
-- Last update: 2014-06-05
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -121,7 +121,6 @@ s_irq <= irq_i or r_swirq;
s_c_dati <= ctrl_slave_i.dat;
s_c_sel <= ctrl_slave_i.sel;
ctrl_slave_o.int <= '0';
ctrl_slave_o.rty <= '0';
ctrl_slave_o.stall <= '0';
ctrl_slave_o.ack <= r_c_ack;
......
modules/wishbone/wb_irq/wb_irq_slave.vhd
View file @ 61ca3f49
......@@ -6,7 +6,7 @@
-- Author : Mathias Kreider
-- Company : GSI
-- Created : 2013-08-10
-- Last update: 2013-08-10
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -124,7 +124,6 @@ begin
irq_pop(I) <= r_pop(I) and r_status(I);
r_status(I) <= not irq_empty(I);
irq_slave_o(I).int <= '0'; --will be obsolete soon
irq_slave_o(I).rty <= '0';
irq_slave_o(I).err <= '0';
irq_slave_o(I).dat <= (others => '0');
......@@ -168,7 +167,6 @@ begin
queue_offs <= to_integer(adr(adr'left downto 4)-1);
word_offs <= to_integer(adr(3 downto 0));
ctrl_slave_o.int <= '0';
ctrl_slave_o.rty <= '0';
ctrl_slave_o.stall <= '0';
......
modules/wishbone/wb_irq/wb_irq_timer.vhd
View file @ 61ca3f49
......@@ -6,7 +6,7 @@
-- Author : Mathias Kreider
-- Company : GSI
-- Created : 2013-08-10
-- Last update: 2013-08-10
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -167,7 +167,6 @@ begin
s_c_dati <= ctrl_slave_i.dat;
s_c_sel <= ctrl_slave_i.sel;
ctrl_slave_o.int <= '0';
ctrl_slave_o.rty <= '0';
ctrl_slave_o.stall <= '0';
ctrl_slave_o.ack <= r_c_ack;
......
modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
View file @ 61ca3f49
......@@ -5,7 +5,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2012-02-23
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -57,9 +57,10 @@ entity wb_onewire_master is
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
int_o : out std_logic;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0)
......@@ -115,7 +116,6 @@ begin -- rtl
slave_in.dat <= wb_dat_i;
slave_in.we <= wb_we_i;
wb_int_o <= slave_out.int;
wb_dat_o <= slave_out.dat;
wb_stall_o <= slave_out.stall;
wb_ack_o <= slave_out.ack;
......@@ -171,7 +171,7 @@ begin -- rtl
bus_adr => adp_out.adr(0 downto 0),
bus_wdt => adp_out.dat,
bus_rdt => rdat_int,
bus_irq => adp_in.int,
bus_irq => int_o,
owr_p => owr_pwren_o,
owr_e => owr_en_o,
owr_i => owr_i);
......
modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
View file @ 61ca3f49
......@@ -30,6 +30,8 @@ entity xwb_onewire_master is
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
int_o : out std_logic;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0)
......@@ -40,35 +42,6 @@ end xwb_onewire_master;
architecture rtl of xwb_onewire_master is
component wb_onewire_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer;
g_ow_btp_normal : string;
g_ow_btp_overdrive : string;
g_CDR_N : integer;
g_CDR_O : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0));
end component;
begin -- rtl
U_Wrapped_1W : wb_onewire_master
......@@ -91,8 +64,8 @@ begin -- rtl
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_ack_o => slave_o.ack,
wb_int_o => slave_o.int,
wb_stall_o => slave_o.stall,
int_o => int_o,
owr_pwren_o => owr_pwren_o,
owr_en_o => owr_en_o,
owr_i => owr_i);
......
modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
View file @ 61ca3f49
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2012-12-18
-- Last update: 2013-09-10
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -115,6 +115,5 @@ begin -- rtl
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.int <= '0';
end wrapper;
modules/wishbone/wb_simple_timer/xwb_tics.vhd
View file @ 61ca3f49
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : CERN
-- Created : 2011-04-03
-- Last update: 2013-09-13
-- Last update: 2018-03-08
-- Platform : FPGA-generics
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -97,7 +97,6 @@ begin
wb_stall_o => slave_o.stall);
slave_o.err <= '0';
slave_o.int <= '0';
slave_o.rty <= '0';
end rtl;
modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
View file @ 61ca3f49
......@@ -68,7 +68,6 @@ entity wb_slave_adapter is
sl_rty_o : out std_logic;
sl_ack_o : out std_logic;
sl_stall_o : out std_logic;
sl_int_o : out std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
......@@ -86,7 +85,6 @@ entity wb_slave_adapter is
ma_rty_i : in std_logic;
ma_ack_i : in std_logic;
ma_stall_i : in std_logic;
ma_int_i : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out
......@@ -146,7 +144,6 @@ begin -- rtl
sl_err_o <= slave_out.err;
sl_stall_o <= slave_out.stall;
sl_dat_o <= slave_out.dat;
sl_int_o <= slave_out.int;
gen_master_use_struct : if (g_master_use_struct) generate
......@@ -159,8 +156,7 @@ begin -- rtl
rty => ma_rty_i,
err => ma_err_i,
dat => ma_dat_i,
stall => ma_stall_i,
int => ma_int_i);
stall => ma_stall_i);
end generate gen_master_use_slv;
master_o <= master_out;
......@@ -228,5 +224,4 @@ begin -- rtl
slave_out.err <= master_in.err;
slave_out.rty <= master_in.rty;
slave_out.dat <= master_in.dat;
slave_out.int <= master_in.int;
end rtl;
modules/wishbone/wb_spi/spi_top.v
View file @ 61ca3f49
......@@ -54,7 +54,10 @@ module spi_top
(
// Wishbone signals
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o,
// Interrupt output
int_o,
// SPI signals
ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
......@@ -78,7 +81,7 @@ module spi_top
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_err_o; // termination w/ error
output wb_int_o; // interrupt request signal output
output int_o; // interrupt request signal output
// SPI signals
output [SPI_SS_NB-1:0] ss_pad_o; // slave select
......@@ -88,7 +91,7 @@ module spi_top
reg [32-1:0] wb_dat_o = 32'b0;
reg wb_ack_o = 1'b0;
reg wb_int_o = 1'b0;
reg int_o = 1'b0;
// Internal signals
reg [SPI_DIVIDER_LEN-1:0] divider; // Divider register
......@@ -198,11 +201,11 @@ module spi_top
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
wb_int_o <= #Tp 1'b0;
int_o <= #Tp 1'b0;
else if (ie && tip && last_bit && pos_edge)
wb_int_o <= #Tp 1'b1;
int_o <= #Tp 1'b1;
else if (wb_ack_o)
wb_int_o <= #Tp 1'b0;
int_o <= #Tp 1'b0;
end
// Divider register
......
modules/wishbone/wb_spi/wb_spi.vhd
View file @ 61ca3f49
......@@ -58,9 +58,10 @@ entity wb_spi is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
int_o : out std_logic;
pad_cs_o : out std_logic_vector(g_num_slaves-1 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
......@@ -90,7 +91,8 @@ architecture rtl of wb_spi is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_int_o : out std_logic;
int_o : out std_logic;
ss_pad_o : out std_logic_vector(SPI_SS_NB-1 downto 0);
sclk_pad_o : out std_logic;
......@@ -132,7 +134,6 @@ begin
sl_dat_o => wb_dat_o,
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o,
sl_int_o => wb_int_o,
sl_err_o => wb_err_o);
rst <= not rst_n_i;
......@@ -155,7 +156,7 @@ begin
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_err_o => wb_out.err,
wb_int_o => wb_out.int,
int_o => int_o,
ss_pad_o => pad_cs_o,
sclk_pad_o => pad_sclk_o,
mosi_pad_o => pad_mosi_o,
......
modules/wishbone/wb_spi/xwb_spi.vhd
View file @ 61ca3f49
......@@ -55,6 +55,8 @@ entity xwb_spi is
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
int_o : out std_logic;
pad_cs_o : out std_logic_vector(g_num_slaves-1 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
......@@ -65,33 +67,6 @@ end xwb_spi;
architecture rtl of xwb_spi is
component wb_spi
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_divider_len : integer := 16;
g_max_char_len : integer := 128;
g_num_slaves : integer := 8);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
pad_cs_o : out std_logic_vector(g_num_slaves-1 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
pad_miso_i : in std_logic);
end component;
begin
U_Wrapped_SPI: wb_spi
......@@ -113,7 +88,7 @@ begin
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_err_o => slave_o.err,
wb_int_o => slave_o.int,
int_o => int_o,
wb_stall_o => slave_o.stall,
pad_cs_o => pad_cs_o,
pad_sclk_o => pad_sclk_o,
......
modules/wishbone/wb_spi_flash/wb_spi_flash.vhd
View file @ 61ca3f49
......@@ -6,7 +6,7 @@
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-04-15
-- Last update: 2013-04-15
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -230,7 +230,6 @@ begin
master_i.ack <= r_ack(r_ack'left);
master_i.err <= r_err;
master_i.rty <= '0';
master_i.int <= '0';
master_i.dat <= r_shift_i;
master_i.stall <= r_stall;
......
modules/wishbone/wb_uart/wb_simple_uart.vhd
View file @ 61ca3f49
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2011-02-21
-- Last update: 2017-02-03
-- Last update: 2018-03-08
-- Platform : FPGA-generics
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -211,7 +211,6 @@ begin -- syn
wb_out.err <= '0';
wb_out.rty <= '0';
wb_out.int <= '0';
gen_phys_uart : if(g_with_physical_uart) generate
......
modules/wishbone/wb_uart/xwb_simple_uart.vhd
View file @ 61ca3f49
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2017-02-03
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -122,7 +122,6 @@ begin -- rtl
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.int <='0';
desc_o <= (others => '0');
......
modules/wishbone/wb_vic/wb_vic.vhd
View file @ 61ca3f49
......@@ -5,7 +5,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2015-11-19
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -272,7 +272,6 @@ begin -- syn
wb_out.rty <= '0';
wb_out.err <= '0';
wb_out.int <= '0';
U_wb_controller : wb_slave_vic
......
modules/wishbone/wb_vic/xwb_vic.vhd
View file @ 61ca3f49
......@@ -5,7 +5,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2015-11-19
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -105,6 +105,5 @@ begin -- wrapper
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.int <= '0';
end wrapper;
modules/wishbone/wishbone_pkg.vhd
View file @ 61ca3f49
......@@ -7,7 +7,7 @@
-- Platform : FPGA-generics
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Copyright (c) 2011-2017 CERN
-- Copyright (c) 2011-2018 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
......@@ -69,7 +69,6 @@ package wishbone_pkg is
err : std_logic;
rty : std_logic;
stall : std_logic;
int : std_logic;
dat : t_wishbone_data;
end record t_wishbone_slave_out;
subtype t_wishbone_master_in is t_wishbone_slave_out;
......@@ -98,7 +97,7 @@ package wishbone_pkg is
-- Dangerous! Will stall a bus.
constant cc_dummy_slave_out : t_wishbone_slave_out :=
('X', 'X', 'X', 'X', 'X', cc_dummy_data);
('X', 'X', 'X', 'X', cc_dummy_data);
constant cc_dummy_master_in : t_wishbone_master_in := cc_dummy_slave_out;
constant cc_dummy_address_array : t_wishbone_address_array(0 downto 0) := (0 => cc_dummy_address);
......@@ -267,7 +266,6 @@ package wishbone_pkg is
sl_rty_o : out std_logic;
sl_ack_o : out std_logic;
sl_stall_o : out std_logic;
sl_int_o : out std_logic;
slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
slave_o : out t_wishbone_slave_out;
ma_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
......@@ -281,7 +279,6 @@ package wishbone_pkg is
ma_rty_i : in std_logic := '0';
ma_ack_i : in std_logic := '0';
ma_stall_i : in std_logic := '0';
ma_int_i : in std_logic := '0';
master_i : in t_wishbone_master_in := cc_dummy_slave_out;
master_o : out t_wishbone_master_out);
end component;
......@@ -674,8 +671,8 @@ package wishbone_pkg is
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
int_o : out std_logic;
scl_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
scl_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
scl_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0);
......@@ -695,6 +692,7 @@ package wishbone_pkg is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
int_o : out std_logic;
scl_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
scl_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
scl_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0);
......@@ -739,8 +737,10 @@ package wishbone_pkg is
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer;
g_ow_btp_normal : string := "1.0";
g_ow_btp_overdrive : string := "5.0");
g_ow_btp_normal : string;
g_ow_btp_overdrive : string;
g_CDR_N : integer;
g_CDR_O : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -752,8 +752,8 @@ package wishbone_pkg is
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
int_o : out std_logic;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0));
......@@ -772,6 +772,7 @@ package wishbone_pkg is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
int_o : out std_logic;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0));
......@@ -812,8 +813,8 @@ package wishbone_pkg is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
int_o : out std_logic;
pad_cs_o : out std_logic_vector(g_num_slaves-1 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
......@@ -833,6 +834,7 @@ package wishbone_pkg is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
int_o : out std_logic;
pad_cs_o : out std_logic_vector(g_num_slaves-1 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
......
platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
View file @ 61ca3f49
......@@ -213,7 +213,6 @@ begin -- behavioral
wb_out.err <= '0';
wb_out.rty <= '0';
wb_out.stall <= '0';
wb_out.int <= '0';
xlx_m_o <= "11"; -- permamently select Passive serial
-- boot mode
......
platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
View file @ 61ca3f49
......@@ -151,7 +151,6 @@ begin -- rtl
boot_en_i => boot_en_i,
gpio_o => gpio_o);
slave_o.int <= '0';
slave_o.err <= '0';
slave_o.rty <= '0';
end rtl;
top/gsi_pexaria2a/wishbone_demo/wishbone_demo_top.vhd
View file @ 61ca3f49
......@@ -223,8 +223,7 @@ begin
end if;
end if;
end process;
gpio_slave_o.int <= '0'; -- In my opinion, this should not be in the structure,
-- but it is in there. Bother Thomasz to remove it.
gpio_slave_o.err <= '0';
gpio_slave_o.rty <= '0';
gpio_slave_o.stall <= '0'; -- This simple example is always ready
......
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