Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
P
Platform-independent core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
19
Issues
19
List
Board
Labels
Milestones
Merge Requests
5
Merge Requests
5
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Platform-independent core collection
Commits
4c098f9b
Commit
4c098f9b
authored
Apr 24, 2019
by
Tristan Gingold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
WIP: more descriptions in README.md
parent
30a4c8c0
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
36 additions
and
1 deletion
+36
-1
README.md
README.md
+36
-1
No files found.
README.md
View file @
4c098f9b
...
...
@@ -5,6 +5,11 @@ require a dedicated repository.
In
[
modules/common
](
modules/common
)
there are general purpose cores:
*
The package
[
gencores_pkg
](
modules/common/gencores_pkg.vhd
)
provides the
declarations of the components (this is not required, you can always
directly instantiate the entities) but also some useful subprograms
like functions for gray encode/decode, boolean conversions...
*
For clock-domain crossing or asynchronous signal register, use
[
gc_sync_ffs
](
modules/common/gc_sync_ffs.vhd
)
. It also has an edge
detector.
...
...
@@ -12,4 +17,34 @@ In [modules/common](modules/common) there are general purpose cores:
is deprecated. It can synchronize multiple signals at the same time but
doesn't ensure coherency between these signals.
*
...
To pass words from one clock domain to another, you can use the module
[
gc_sync_word_wr
](
modules/common/gc_sync_word_wr.vhd
)
To pass one pulse from one domain to another, use module
[
gc_pulse_synchronizer
](
modules/common/gc_pulse_synchronizer.vhd
)
or the version with resets
[
gc_pulse_synchronizer2
](
modules/common/gc_pulse_synchronizer2.vhd
)
*
For reset generation, you can use
[
gc_reset
](
modules/common/gc_reset.vhd
)
which generate synchronous resets once all the PLL lock signals are set.
The module
[
gc_reset_multi_aasd
](
modules/common/gc_reset_multi_aasd.vhd
)
generate asynchronously asserted synchronously deasserted resets for
multiple clock domains.
The module
[
gc_single_reset_gen
](
modules/common/gc_single_reset_gen.vhd
)
is convenient to generate a single reset from multiple sources (like
powerup signal and a reset button).
*
Words can be packed or unpacked using the module
[
gc_word_packer
](
modules/common/gc_word_packer.vhd
)
*
Module
[
gc_i2c_slave
](
modules/common/gc_i2c_slave.vhd
)
provides a simple
i2c slave. This module is used in
[
gc_sfp_i2c_adapter
](
modules/common/gc_sfp_i2c_adapter.vhd
)
to emulate an
SFP DDM.
*
The module
[
gc_serial_dac
](
modules/common/gc_serial_dac.vhd
)
provides an
interface to a serial DAC.
*
The module
[
gc_rr_arbiter
](
modules/common/gc_rr_arbiter.vhd
)
provides a
round-robin arbiter amount an arbitrary number of requests.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment