Fix BVALID signalling in AXI4Lite-to-WB bridge wrapper

The BVALID signal must be asserted once the write operation is completed. The master is not required to assert BREADY before this happens. The old code happened to work if the master tied BREADY high, which is allowed but not required.

Fix BVALID signalling in AXI4Lite-to-WB bridge wrapper
The BVALID signal must be asserted once the write operation is completed. The master is not required to assert BREADY before this happens. The old code happened to work if the master tied BREADY high, which is allowed but not required.
496eced5 · Marcus Comstedt · Olof Kindgren · 392ed83d · 496eced5
Commit 496eced5 authored Apr 23, 2020 by Marcus Comstedt Committed by Olof Kindgren Apr 30, 2020
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xwb_axi4lite_bridge.vhd modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd +1 -1

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--- a/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
@@ -171,8 +171,8 @@ begin

            
          when RESPONSE_WRITE =>
+            axi4_slave_o.BVALID <= '1';
            if (axi4_slave_i.BREADY = '1') then
-              axi4_slave_o.BVALID <= '1';
              state               <= IDLE;
            end if;