Commit 37f93117 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana Committed by Tomasz Wlostowski

Added gc_fsm_watchdog component

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Wlostowski's avatarTomasz Włostowski <tomasz.wlostowski@cern.ch>
parent e470d30d
FILE=gc_fsm_watchdog
all:
$(MAKE) -C fig
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
# bibtex $(FILE).aux
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
evince $(FILE).pdf &
clean:
$(MAKE) -C fig clean
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
Type 'make' to create your .pdf documentation file.
You need Inkscape to make the documentation files:
sudo apt-get install inkscape
\ No newline at end of file
\begin{titlepage}
\vspace*{3cm}
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent{\LARGE \textbf{Finite State Machine Watchdog Timer}}
\noindent \rule{\textwidth}{.1cm}
\hfill November 23, 2013
\vspace*{3cm}
\begin{figure}[h]
\includegraphics[height=3cm]{fig/cern-logo}
\hfill
\includegraphics[height=3cm]{fig/ohwr-logo}
\end{figure}
\vfill
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent \rule{\textwidth}{.05cm}
\end{titlepage}
SRC = $(wildcard *.svg)
OBJS = $(SRC:.svg=.pdf)
all: $(OBJS)
%.pdf : %.svg
inkscape -f $< -A $@
clean :
rm -f *.pdf
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@misc{coding-guidelines,
author = "Patrick Loschmidt and Nata{\v s}a Simani\'c and C\'esar Prados and Pablo Alvarez and Javier Serrano",
title = {{Guidelines for VHDL Coding}},
month = 04,
year = 2011,
note = {\url{http://www.ohwr.org/documents/24}}
}
%==============================================================================
% Document header
%==============================================================================
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{multirow}
\usepackage{color}
\usepackage[toc,page]{appendix}
% Header and footer customization
\usepackage{fancyhdr}
\setlength{\headheight}{15.2pt}
\pagestyle{fancy}
\fancyhead[L]{\nouppercase{\leftmark}}
\fancyhead[R]{}
\renewcommand{\footrulewidth}{0.4pt}
%==============================================================================
% Start of document
%==============================================================================
\begin{document}
%------------------------------------------------------------------------------
% Title
%------------------------------------------------------------------------------
\include{cern-title}
%------------------------------------------------------------------------------
% Revision history
%------------------------------------------------------------------------------
\thispagestyle{empty}
\section*{Revision history}
\centerline
{
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
23-11-2013 & 0.1 & First draft \\
\hline
\end{tabular}
}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
\tableofcontents
%------------------------------------------------------------------------------
% List of figs, tables, abbrevs
%------------------------------------------------------------------------------
\pagebreak
\listoffigures
\listoftables
\section*{List of Abbreviations}
\begin{tabular}{l l}
FSM & Finite State Machine \\
\end{tabular}
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
%==============================================================================
% SEC: Intro
%==============================================================================
\section{Introduction}
\label{sec:intro}
The Finite State Machine (FSM) Watchdog Timer component (\textit{gc\_fsm\_watchdog})
is a simple component that can be used to reset an FSM in case it spends too much
time outside the state machine's IDLE state. The component asserts its output signal
when the watchdog reaches a user-selected value. This output can then be used
in the HDL code to reset the FSM.
%==============================================================================
% SEC: Instantiation
%==============================================================================
\section{Instantiation}
\label{sec:instantiation}
The ports of the \textit{gc\_fsm\_watchdog} module are shown in Table~\ref{tbl:ports}.
\begin{table}[h]
\caption{Ports of \textit{vbcp\_wb} module}
\label{tbl:ports}
\centerline
{
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Port}} & \textbf{Size} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
clk\_i & 1 & Clock input \\
rst\_n\_i & 1 & Active-low reset input \\
wdt\_rst\_i & 1 & Active-high reset input from the FSM to the watchdog timer \newline
Synchronous to \textit{clk\_i}\\
fsm\_rst\_o & 1 & Active-high reset output from the watchdog timer to the FSM \newline
Synchronous to \textit{clk\_i}\\ \\
\hline
\end{tabular}
}
\end{table}
Figure~\ref{fig:conn} shows how the \textit{gc\_fsm\_watchdog} module can be connected
to an FSM in a design. The clock (\textit{clk\_i}) and active-low reset (\textit{rst\_n\_i})
input ports should be connected to the master reset lines in the design. The signal connected
to the active-high input reset port (\textit{wdt\_rst\_i}) should be asserted by the FSM when
it is in its IDLE state. The reset output to the FSM (\textit{fsm\_rst\_o}) should be
ORed together with the active-low master reset input and connected to the reset input
of the FSM.
\begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/conn}}
\caption{Connecting the \textit{gc\_fsm\_watchdog} module to an FSM}
\label{fig:conn}
\end{figure}
Examples of how to connect to the \textit{gc\_fsm\_watchdog} module are given in
Appendix~\ref{app:instantiation}.
%==============================================================================
% SEC: Instantiation
%==============================================================================
\section{Implementation}
\label{sec:implem}
The watchdog timer is implemented as a simple up-counter which asserts the
\textit{fsm\_rst\_o} output when the maximum value of \textit{g\_wdt\_max} is
reached. The counter is reset by either the active-low (system) reset and the
active-high (FSM) reset. A diagram of the block is shown in Figure~\ref{fig:implem}.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/implem}}
\caption{Diagram of the FSM watchdog module}
\label{fig:implem}
\end{figure}
%==============================================================================
% APPENDICES
%==============================================================================
\pagebreak
\begin{appendices}
\section{Example instantiation}
\label{app:instantiation}
\subsection{VHDL}
\begin{verbatim}
p_proc : process (sys_clk)
begin
if rising_edge(sys_clk) then
if (sys_rst_n = '0') or (rst_fr_wdt = '1') then
state <= IDLE;
else
case state is
when IDLE =>
wdt_rst <= '1';
if (trigger = '1') then
wdt_rst <= '0';
state <= NEXT_STATE;
end if;
when NEXT_STATE =>
-- ...
end case;
end if;
end if;
end process p_proc;
cmp_fsm_watchdog : gc_fsm_watchdog
generic map
(
-- FSM should return to IDLE within 256 clk_i cycles
g_wdt_max => 256
)
port map
(
clk_i => sys_clk;
rst_n_i => sys_rst_n;
wdt_rst_i => wdt_rst;
fsm_rst_o => fsm_rst;
);
\end{verbatim}
\pagebreak
\subsection{Verilog}
\begin{verbatim}
always @(posedge sys_clk)
begin
if (!rst_n_i) or (rst_fr_wdt) then
state <= IDLE;
else
begin
case (state)
IDLE:
begin
wdt_rst <= 1'b1;
if (trigger = '1') then
begin
wdt_rst <= 1'b0;
state <= NEXT_STATE;
end
end
NEXT_STATE:
begin
// ...
end
endcase
end
end
gc_fsm_watchdog cmp_gc_fsm_watchdog (
.clk_i (sys_clk),
.rst_n_i (sys_rst_n),
.wdt_rst_i (wdt_rst),
.fsm_rst_o (rst_fr_wdt)
)
\end{verbatim}
\end{appendices}
%==============================================================================
% Bibliography
%==============================================================================
%\pagebreak
%\bibliographystyle{ieeetr}
%\bibliography{gc_fsm_watchdog}
\end{document}
\ No newline at end of file
......@@ -16,6 +16,6 @@ files = [ "gencores_pkg.vhd",
"gc_word_packer.vhd",
"gc_i2c_slave.vhd",
"gc_glitch_filt.vhd",
"gc_big_adder.vhd"
"gc_big_adder.vhd",
"gc_fsm_watchdog.vhd"
];
--==============================================================================
-- CERN (BE-CO-HT)
-- Finite State Machine Watchdog Timer
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-11-22
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-11-22 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity gc_fsm_watchdog is
generic
(
-- Maximum value of watchdog timer in clk_i cycles
g_wdt_max : positive := 65535
);
port
(
-- Clock and active-low reset line
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Active-high watchdog timer reset line, synchronous to clk_i
wdt_rst_i : in std_logic;
-- Active-high reset output, synchronous to clk_i
fsm_rst_o : out std_logic
);
end entity gc_fsm_watchdog;
architecture behav of gc_fsm_watchdog is
--============================================================================
-- Signal declarations
--============================================================================
signal wdt : unsigned(f_log2_size(g_wdt_max)-1 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Watchdog timer process
--============================================================================
p_wdt : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (wdt_rst_i = '1') then
wdt <= (others => '0');
fsm_rst_o <= '0';
else
wdt <= wdt + 1;
if (wdt = g_wdt_max) then
fsm_rst_o <= '1';
end if;
end if;
end if;
end process p_wdt;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
vlib work
vcom -explicit -93 "../../modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../../modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "../../modules/common/gc_fsm_watchdog.vhd"
vcom -explicit -93 "tb_gc_fsm_watchdog.vhd"
vsim -t 1ps -voptargs="+acc" -lib work work.tb_gc_fsm_watchdog
radix -hexadecimal
#add wave *
do wave.do
run 4 ms
wave zoomfull
--==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for FSM Watchdog Timer
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-11-22
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-11-22 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity tb_gc_fsm_watchdog is
end entity tb_gc_fsm_watchdog;
architecture behav of tb_gc_fsm_watchdog is
--============================================================================
-- Type declarations
--============================================================================
type t_state is
(
IDLE,
RUN
);
--============================================================================
-- Constant declarations
--============================================================================
constant c_clk_per : time := 50 ns;
constant c_reset_width : time := 112 ns;
constant c_fsm_time : positive := 32767;
--============================================================================
-- Signal declarations
--============================================================================
signal clk, rst_n : std_logic := '0';
signal wdt_rst : std_logic;
signal rst_from_wdt : std_logic;
signal state : t_state;
signal cnt : unsigned(15 downto 0);
signal cnt_tick_p : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Generate clock and reset signals
--============================================================================
-- Clock generation
p_clk: process
begin
clk <= not clk;
wait for c_clk_per/2;
end process p_clk;
-- Reset generation
p_rst_n: process
begin
rst_n <= '0';
wait for c_reset_width;
rst_n <= '1';
wait;
end process p_rst_n;
--============================================================================
-- DUT instantiation
--============================================================================
DUT : gc_fsm_watchdog
generic map
(
g_wdt_max => 65536
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
wdt_rst_i => wdt_rst,
fsm_rst_o => rst_from_wdt
);
--============================================================================
-- FSM to test the Watchdog
--============================================================================
p_fsm : process (clk) is
begin
if rising_edge(clk) then
if (rst_n = '0') or (rst_from_wdt = '1') then
wdt_rst <= '1';
state <= IDLE;
else
case state is
when IDLE =>
wdt_rst <= '1';
if (cnt_tick_p = '1') then
state <= RUN;
wdt_rst <= '0';
end if;
when RUN =>
if (cnt_tick_p = '1') then
state <= IDLE;
end if;
end case;
end if;
end if;
end process p_fsm;
p_cnt : process (clk) is
begin
if rising_edge(clk) then
if (rst_n = '0') then
cnt <= (others => '0');
cnt_tick_p <= '0';
else
cnt <= cnt+1;
cnt_tick_p <= '0';
if (cnt = c_fsm_time) then
cnt <= (others => '0');
cnt_tick_p <= '1';
end if;
end if;
end if;
end process p_cnt;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /tb_gc_fsm_watchdog/clk
add wave -noupdate /tb_gc_fsm_watchdog/rst_n
add wave -noupdate /tb_gc_fsm_watchdog/wdt_rst
add wave -noupdate /tb_gc_fsm_watchdog/rst_from_wdt
add wave -noupdate /tb_gc_fsm_watchdog/state
add wave -noupdate /tb_gc_fsm_watchdog/cnt
add wave -noupdate /tb_gc_fsm_watchdog/cnt_tick_p
add wave -noupdate -divider watchdog
add wave -noupdate /tb_gc_fsm_watchdog/DUT/wdt_rst_i
add wave -noupdate /tb_gc_fsm_watchdog/DUT/fsm_rst_o
add wave -noupdate /tb_gc_fsm_watchdog/DUT/wdt
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {834632588 ps} 0}
configure wave -namecolwidth 280
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {3851118211 ps}
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