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Platform-independent core collection
Commit 1f7fae25 authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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Cleanup reset logic. 

Each clock domain needs a separate reset line.
However, one cannot reset only a single domain---that could cause inconsistency
at clock crossing boundaries.
This change splits reset lines per clock domain and centralizes generation.
parent c33d3885
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Inline Side-by-side
Showing with 239 additions and 132 deletions
modules/common/Manifest.py
View file @ 1f7fae25
......@@ -4,6 +4,7 @@ files = [ "gencores_pkg.vhd",
"gc_extend_pulse.vhd",
"gc_delay_gen.vhd",
"gc_dual_pi_controller.vhd",
"gc_reset.vhd",
"gc_serial_dac.vhd",
"gc_sync_ffs.vhd",
"gc_arbitrated_mux.vhd",
......
modules/common/gc_reset.vhd 0 → 100644
View file @ 1f7fae25
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity gc_reset is
generic(
g_clocks : natural := 1;
g_logdelay : natural := 10;
g_syncdepth : natural := 3);
port(
free_clk_i : in std_logic;
locked_i : in std_logic := '1'; -- All the PLL locked signals ANDed together
clks_i : in std_logic_vector(g_clocks-1 downto 0);
rstn_o : out std_logic_vector(g_clocks-1 downto 0));
end gc_reset;
architecture rtl of gc_reset is
subtype t_shifter is std_logic_vector(g_syncdepth-1 downto 0);
type t_shifters is array(natural range <>) of t_shifter;
signal shifters : t_shifters(g_clocks-1 downto 0) := (others => (others => '0')); -- start reset
signal locked_count : unsigned(g_syncdepth-1 downto 0) := (others => '0');
signal master_rstn : std_logic;
begin
lock : process(free_clk_i)
constant locked_done : unsigned(g_syncdepth-1 downto 0) := (others => '1');
begin
if rising_edge(free_clk_i) then
if locked_i = '0' then
master_rstn <= '0';
locked_count <= (others => '0');
else
if locked_count = locked_done then
master_rstn <= '1';
else
master_rstn <= '0';
locked_count <= locked_count + 1;
end if;
end if;
end if;
end process;
-- Generate the sync chains for each clock domain
syncs : for i in g_clocks-1 downto 0 generate
sync : process(clks_i(i))
begin
if rising_edge(clks_i(i)) then
shifters(i) <= master_rstn & shifters(i)(g_syncdepth-1 downto 1);
end if;
end process;
end generate;
-- Output the synchronized reset
rstn : for i in g_clocks-1 downto 0 generate
rstn_o(i) <= shifters(i)(0);
end generate;
end rtl;
modules/common/gc_wfifo.vhd
View file @ 1f7fae25
......@@ -10,19 +10,21 @@ entity gc_wfifo is
addr_width : natural := 4;
data_width : natural := 32);
port(
rst_n_i : in std_logic;
-- write port, only set w_en when w_rdy
w_clk_i : in std_logic;
w_rst_n_i: in std_logic;
w_rdy_o : out std_logic;
w_en_i : in std_logic;
w_data_i : in std_logic_vector(data_width-1 downto 0);
-- (pre)alloc port, can be unused
a_clk_i : in std_logic;
a_rst_n_i: in std_logic;
a_rdy_o : out std_logic;
a_en_i : in std_logic;
-- read port, only set r_en when r_rdy
-- data is valid the cycle after r_en raised
r_clk_i : in std_logic;
r_rst_n_i: in std_logic;
r_rdy_o : out std_logic;
r_en_i : in std_logic;
r_data_o : out std_logic_vector(data_width-1 downto 0));
......@@ -101,7 +103,7 @@ begin
variable idx : counter;
begin
if rising_edge(r_clk_i) then
if rst_n_i = '0' then
if r_rst_n_i = '0' then
idx := (others => '0');
elsif r_en_i = '1' then
idx := r_idx_bnry + 1;
......@@ -120,7 +122,7 @@ begin
variable idx : counter;
begin
if rising_edge(w_clk_i) then
if rst_n_i = '0' then
if w_rst_n_i = '0' then
idx := (others => '0');
elsif w_en_i = '1' then
idx := w_idx_bnry + 1;
......@@ -139,7 +141,7 @@ begin
variable idx : counter;
begin
if rising_edge(a_clk_i) then
if rst_n_i = '0' then
if a_rst_n_i = '0' then
idx := (others => '0');
elsif a_en_i = '1' then
idx := a_idx_bnry + 1;
......
modules/common/gencores_pkg.vhd
View file @ 1f7fae25
......@@ -218,24 +218,39 @@ package gencores_pkg is
addr_width : natural := 4;
data_width : natural := 32);
port(
rst_n_i : in std_logic;
-- write port, only set w_en when w_rdy
w_clk_i : in std_logic;
w_rst_n_i: in std_logic;
w_rdy_o : out std_logic;
w_en_i : in std_logic;
w_data_i : in std_logic_vector(data_width-1 downto 0);
-- (pre)alloc port, can be unused
a_clk_i : in std_logic;
a_rst_n_i: in std_logic;
a_rdy_o : out std_logic;
a_en_i : in std_logic;
-- read port, only set r_en when r_rdy
-- data is valid the cycle after r_en raised
r_clk_i : in std_logic;
r_rst_n_i: in std_logic;
r_rdy_o : out std_logic;
r_en_i : in std_logic;
r_data_o : out std_logic_vector(data_width-1 downto 0));
end component;
-- Power-On reset generation
component gc_reset is
generic(
g_clocks : natural := 1;
g_logdelay : natural := 10;
g_syncdepth : natural := 3);
port(
free_clk_i : in std_logic;
locked_i : in std_logic := '1'; -- All the PLL locked signals ANDed together
clks_i : in std_logic_vector(g_clocks-1 downto 0);
rstn_o : out std_logic_vector(g_clocks-1 downto 0));
end component;
procedure f_rr_arbitrate (
signal req : in std_logic_vector;
signal pre_grant : in std_logic_vector;
......@@ -284,4 +299,3 @@ package body gencores_pkg is
end f_rr_arbitrate;
end gencores_pkg;
modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
View file @ 1f7fae25
......@@ -4,21 +4,23 @@ use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
-- If you reset one clock domain, you must reset BOTH!
-- Release of the reset lines may be arbitrarily out-of-phase
entity xwb_clock_crossing is
generic(
sync_depth : natural := 3;
log2fifo : natural := 4);
port(
-- Common wishbone signals
rst_n_i : in std_logic;
-- Slave control port
slave_clk_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
slave_clk_i : in std_logic;
slave_rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- Master reader port
master_clk_i : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out);
master_clk_i : in std_logic;
master_rst_n_i : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out);
end xwb_clock_crossing;
architecture rtl of xwb_clock_crossing is
......@@ -58,9 +60,9 @@ architecture rtl of xwb_clock_crossing is
begin
mfifo : gc_wfifo
generic map(addr_width => log2fifo, data_width => mlen, sync_depth => sync_depth, gray_code => true)
port map(w_clk_i => slave_clk_i, w_rdy_o => mw_rdy, w_en_i => mw_en, w_data_i => msend_vect,
r_clk_i => master_clk_i, r_rdy_o => mr_rdy, r_en_i => mr_en, r_data_o => mrecv_vect,
a_clk_i => '0', a_rdy_o => open, a_en_i => '0', rst_n_i => rst_n_i);
port map(w_clk_i => slave_clk_i, w_rst_n_i => slave_rst_n_i, w_rdy_o => mw_rdy, w_en_i => mw_en, w_data_i => msend_vect,
r_clk_i => master_clk_i, r_rst_n_i => master_rst_n_i, r_rdy_o => mr_rdy, r_en_i => mr_en, r_data_o => mrecv_vect,
a_clk_i => '0', a_rst_n_i => '0', a_rdy_o => open, a_en_i => '0');
msend_vect(mCYC_start) <= msend.CYC;
msend_vect(mWE_start) <= msend.WE;
......@@ -76,9 +78,9 @@ begin
sfifo : gc_wfifo
generic map(addr_width => log2fifo, data_width => slen, sync_depth => sync_depth, gray_code => true)
port map(w_clk_i => master_clk_i, w_rdy_o => open, w_en_i => sw_en, w_data_i => ssend_vect,
r_clk_i => slave_clk_i, r_rdy_o => sr_rdy, r_en_i => sr_en, r_data_o => srecv_vect,
a_clk_i => slave_clk_i, a_rdy_o => sa_rdy, a_en_i => sa_en, rst_n_i => rst_n_i);
port map(w_clk_i => master_clk_i, w_rst_n_i => master_rst_n_i, w_rdy_o => open, w_en_i => sw_en, w_data_i => ssend_vect,
r_clk_i => slave_clk_i, r_rst_n_i => slave_rst_n_i, r_rdy_o => sr_rdy, r_en_i => sr_en, r_data_o => srecv_vect,
a_clk_i => slave_clk_i, a_rst_n_i => slave_rst_n_i, a_rdy_o => sa_rdy, a_en_i => sa_en);
ssend_vect(sACK_start) <= ssend.ACK;
ssend_vect(sRTY_start) <= ssend.RTY;
......@@ -113,7 +115,7 @@ begin
drive_master_port : process(master_clk_i)
begin
if rising_edge(master_clk_i) then
if rst_n_i = '0' then
if master_rst_n_i = '0' then
master_o_STB <= '0';
else
master_o_STB <= mr_en or (mrecv.CYC and master_o_STB and master_i.STALL);
......@@ -138,7 +140,7 @@ begin
drive_slave_port : process(slave_clk_i)
begin
if rising_edge(slave_clk_i) then
if rst_n_i = '0' then
if slave_rst_n_i = '0' then
slave_o_PUSH <= '0';
slave_CYC <= '0';
else
......
modules/wishbone/wb_pcie/pcie_altera.vhd
View file @ 1f7fae25
......@@ -6,8 +6,7 @@ entity pcie_altera is
port(
clk125_i : in std_logic; -- 125 MHz, free running
cal_clk50_i : in std_logic; -- 50 MHz, shared between all PHYs
rstn_i : in std_logic; -- Power on reset
rstn_o : out std_logic; -- If PCIe resets
async_rstn : in std_logic;
pcie_refclk_i : in std_logic; -- 100 MHz, must not derive clk125_i or cal_clk50_i
pcie_rstn_i : in std_logic; -- PCIe reset pin
......@@ -17,7 +16,8 @@ entity pcie_altera is
cfg_busdev_o : out std_logic_vector(12 downto 0); -- Configured Bus#:Dev#
-- Simplified wishbone output stream
wb_clk_o : out std_logic;
wb_clk_o : out std_logic; -- core_clk_out (of PCIe Hard-IP)
wb_rstn_i : in std_logic; -- wb_rstn_i in PCIe clock domain
rx_wb_stb_o : out std_logic;
rx_wb_dat_o : out std_logic_vector(63 downto 0);
......@@ -445,9 +445,8 @@ begin
end if;
end process;
npor <= rstn_i and pcie_rstn_i;
rstn <= rstn_i or rst_reg;
rstn_o <= rstn;
npor <= async_rstn and pcie_rstn_i; -- async
rstn <= wb_rstn_i and not crst; -- core_clk_out
-- Recover bus:device IDs from config space
cfg : process(core_clk_out)
......
modules/wishbone/wb_pcie/pcie_wb.vhd
View file @ 1f7fae25
......@@ -12,22 +12,21 @@ entity pcie_wb is
port(
clk125_i : in std_logic; -- 125 MHz, free running
cal_clk50_i : in std_logic; -- 50 MHz, shared between all PHYs
rstn_i : in std_logic;
pcie_refclk_i : in std_logic; -- 100 MHz, must not derive clk125_i or cal_clk50_i
pcie_rstn_i : in std_logic;
pcie_rstn_i : in std_logic; -- Reset PCIe sticky registers
pcie_rx_i : in std_logic_vector(3 downto 0);
pcie_tx_o : out std_logic_vector(3 downto 0);
wb_clk : in std_logic; -- Whatever clock you want these signals on:
wb_rstn_i : in std_logic; -- (whatever clock domain you like)
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in);
end pcie_wb;
architecture rtl of pcie_wb is
signal internal_wb_clk : std_logic; -- Should be input in final version
signal rstn, stall : std_logic;
signal internal_wb_clk, internal_wb_rstn, stall : std_logic;
signal internal_wb_rstn_sync : std_logic_vector(3 downto 0) := (others => '0');
signal rx_wb64_stb, rx_wb64_stall : std_logic;
signal rx_wb32_stb, rx_wb32_stall : std_logic;
......@@ -65,8 +64,8 @@ begin
pcie_phy : pcie_altera port map(
clk125_i => clk125_i,
cal_clk50_i => cal_clk50_i,
rstn_i => rstn_i,
rstn_o => rstn,
async_rstn => wb_rstn_i,
pcie_refclk_i => pcie_refclk_i,
pcie_rstn_i => pcie_rstn_i,
pcie_rx_i => pcie_rx_i,
......@@ -75,6 +74,7 @@ begin
cfg_busdev_o => cfg_busdev,
wb_clk_o => internal_wb_clk,
wb_rstn_i => internal_wb_rstn,
rx_wb_stb_o => rx_wb64_stb,
rx_wb_dat_o => rx_wb64_dat,
......@@ -90,7 +90,7 @@ begin
pcie_rx : pcie_64to32 port map(
clk_i => internal_wb_clk,
rstn_i => rstn,
rstn_i => internal_wb_rstn,
master64_stb_i => rx_wb64_stb,
master64_dat_i => rx_wb64_dat,
master64_stall_o => rx_wb64_stall,
......@@ -100,7 +100,7 @@ begin
pcie_tx : pcie_32to64 port map(
clk_i => internal_wb_clk,
rstn_i => rstn,
rstn_i => internal_wb_rstn,
master32_stb_i => tx_wb32_stb,
master32_dat_i => tx_wb32_dat,
master32_stall_o => open,
......@@ -110,7 +110,7 @@ begin
pcie_logic : pcie_tlp port map(
clk_i => internal_wb_clk,
rstn_i => rstn,
rstn_i => internal_wb_rstn,
rx_wb_stb_i => rx_wb32_stb,
rx_wb_dat_i => rx_wb32_dat,
......@@ -137,11 +137,14 @@ begin
wb_rty_i => slave_o.rty,
wb_dat_i => wb_dat);
internal_wb_rstn <= internal_wb_rstn_sync(0);
tx64_alloc <= tx32_alloc and tx_alloc_mask;
alloc : process(internal_wb_clk)
begin
if rising_edge(internal_wb_clk) then
if rstn = '0' then
internal_wb_rstn_sync <= wb_rstn_i & internal_wb_rstn_sync(internal_wb_rstn_sync'length-1 downto 1);
if internal_wb_rstn = '0' then
tx_alloc_mask <= '1';
else
tx_alloc_mask <= tx_alloc_mask xor tx32_alloc;
......@@ -150,13 +153,14 @@ begin
end process;
clock_crossing : xwb_clock_crossing port map(
rst_n_i => rstn,
slave_clk_i => internal_wb_clk,
slave_i => slave_i,
slave_o => slave_o,
master_clk_i => wb_clk,
master_i => master_i,
master_o => master_o);
slave_clk_i => internal_wb_clk,
slave_rst_n_i => internal_wb_rstn,
slave_i => slave_i,
slave_o => slave_o,
master_clk_i => wb_clk,
master_rst_n_i => wb_rstn_i,
master_i => master_i,
master_o => master_o);
slave_i.stb <= wb_stb when wb_bar = "001" else '0';
wb_stall <= slave_o.stall when wb_bar = "001" else '0';
......
modules/wishbone/wb_pcie/pcie_wb_pkg.vhd
View file @ 1f7fae25
......@@ -10,14 +10,14 @@ package pcie_wb_pkg is
port(
clk125_i : in std_logic; -- 125 MHz, free running
cal_clk50_i : in std_logic; -- 50 MHz, shared between all PHYs
rstn_i : in std_logic;
pcie_refclk_i : in std_logic; -- 100 MHz, must not derive clk125_i or cal_clk50_i
pcie_rstn_i : in std_logic;
pcie_rstn_i : in std_logic; -- Asynchronous "clear sticky" PCIe pin
pcie_rx_i : in std_logic_vector(3 downto 0);
pcie_tx_o : out std_logic_vector(3 downto 0);
wb_clk : in std_logic; -- Whatever clock you want these signals on:
wb_rstn_i : in std_logic; -- Reset wishbone bus
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in);
end component;
......@@ -26,8 +26,7 @@ package pcie_wb_pkg is
port(
clk125_i : in std_logic; -- 125 MHz, free running
cal_clk50_i : in std_logic; -- 50 MHz, shared between all PHYs
rstn_i : in std_logic; -- Logical reset
rstn_o : out std_logic; -- If PCIe resets
async_rstn : in std_logic;
pcie_refclk_i : in std_logic; -- 100 MHz, must not derive clk125_i or cal_clk50_i
pcie_rstn_i : in std_logic; -- PCIe reset pin
......@@ -38,6 +37,7 @@ package pcie_wb_pkg is
-- Simplified wishbone output stream
wb_clk_o : out std_logic;
wb_rstn_i : in std_logic;
rx_wb_stb_o : out std_logic;
rx_wb_dat_o : out std_logic_vector(63 downto 0);
......
modules/wishbone/wishbone_pkg.vhd
View file @ 1f7fae25
......@@ -330,21 +330,23 @@ package wishbone_pkg is
);
end component;
-- If you reset one clock domain, you must reset BOTH!
-- Release of the reset lines may be arbitrarily out-of-phase
component xwb_clock_crossing is
generic(
sync_depth : natural := 3;
log2fifo : natural := 4);
port(
-- Common wishbone signals
rst_n_i : in std_logic;
-- Slave control port
slave_clk_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
slave_clk_i : in std_logic;
slave_rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- Master reader port
master_clk_i : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out);
master_clk_i : in std_logic;
master_rst_n_i : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out);
end component;
subtype t_xwb_dpram_init is t_generic_ram_init;
......
syn/gsi_pexaria2a/wishbone_demo/wishbone_demo.qsf
View file @ 1f7fae25
......@@ -51,6 +51,63 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_U23 -to pcie_refclk_i
set_location_assignment PIN_W1 -to pcie_rstn_i
set_location_assignment PIN_N23 -to pcie_rx_i[3]
set_location_assignment PIN_R23 -to pcie_rx_i[2]
set_location_assignment PIN_W23 -to pcie_rx_i[1]
set_location_assignment PIN_AA23 -to pcie_rx_i[0]
set_location_assignment PIN_M21 -to pcie_tx_o[3]
set_location_assignment PIN_P21 -to pcie_tx_o[2]
set_location_assignment PIN_V21 -to pcie_tx_o[1]
set_location_assignment PIN_Y21 -to pcie_tx_o[0]
set_location_assignment PIN_U9 -to leds_o[0]
set_location_assignment PIN_V9 -to leds_o[1]
set_location_assignment PIN_AA7 -to leds_o[2]
set_location_assignment PIN_AB7 -to leds_o[3]
set_location_assignment PIN_W9 -to leds_o[4]
set_location_assignment PIN_W10 -to leds_o[5]
set_location_assignment PIN_AA10 -to leds_o[6]
set_location_assignment PIN_AB10 -to leds_o[7]
set_location_assignment PIN_D11 -to clk125_i
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[3]
set_location_assignment PIN_N24 -to "pcie_rx_i[3](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[2]
set_location_assignment PIN_R24 -to "pcie_rx_i[2](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[1]
set_location_assignment PIN_W24 -to "pcie_rx_i[1](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[0]
set_location_assignment PIN_AA24 -to "pcie_rx_i[0](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[3]
set_location_assignment PIN_M22 -to "pcie_tx_o[3](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[2]
set_location_assignment PIN_P22 -to "pcie_tx_o[2](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[1]
set_location_assignment PIN_V22 -to "pcie_tx_o[1](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[0]
set_location_assignment PIN_Y22 -to "pcie_tx_o[0](n)"
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to pcie_rstn_i
set_instance_assignment -name IO_STANDARD HCSL -to pcie_refclk_i
set_location_assignment PIN_U24 -to "pcie_refclk_i(n)"
set_instance_assignment -name IO_STANDARD LVDS -to clk125_i
set_location_assignment PIN_C11 -to "clk125_i(n)"
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[0]
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "ACTIVE SERIAL"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_JAM_FILE ON
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHZ
set_global_assignment -name SDC_FILE ../../../top/gsi_pexaria2a/wishbone_demo/wishbone_demo.sdc
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
set_global_assignment -name VHDL_FILE ../../../modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
......@@ -96,6 +153,7 @@ set_global_assignment -name VHDL_FILE ../../../modules/common/gc_frequency_meter
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_pulse_synchronizer.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_arbitrated_mux.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_sync_ffs.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_reset.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_serial_dac.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_dual_pi_controller.vhd
set_global_assignment -name VHDL_FILE ../../../modules/common/gc_delay_gen.vhd
......@@ -106,53 +164,7 @@ set_global_assignment -name VHDL_FILE ../../../modules/common/gencores_pkg.vhd
set_global_assignment -name VHDL_FILE ../../../top/gsi_pexaria2a/wishbone_demo/sys_pll.vhd
set_global_assignment -name VHDL_FILE ../../../top/gsi_pexaria2a/wishbone_demo/wishbone_demo_top.vhd
set_global_assignment -name QIP_FILE ../../../top/gsi_pexaria2a/wishbone_demo/sys_pll.qip
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_U23 -to pcie_refclk_i
set_location_assignment PIN_W1 -to pcie_rstn_i
set_location_assignment PIN_N23 -to pcie_rx_i[3]
set_location_assignment PIN_R23 -to pcie_rx_i[2]
set_location_assignment PIN_W23 -to pcie_rx_i[1]
set_location_assignment PIN_AA23 -to pcie_rx_i[0]
set_location_assignment PIN_M21 -to pcie_tx_o[3]
set_location_assignment PIN_P21 -to pcie_tx_o[2]
set_location_assignment PIN_V21 -to pcie_tx_o[1]
set_location_assignment PIN_Y21 -to pcie_tx_o[0]
set_location_assignment PIN_U9 -to leds_o[0]
set_location_assignment PIN_V9 -to leds_o[1]
set_location_assignment PIN_AA7 -to leds_o[2]
set_location_assignment PIN_AB7 -to leds_o[3]
set_location_assignment PIN_W9 -to leds_o[4]
set_location_assignment PIN_W10 -to leds_o[5]
set_location_assignment PIN_AA10 -to leds_o[6]
set_location_assignment PIN_AB10 -to leds_o[7]
set_location_assignment PIN_D11 -to clk125_i
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[3]
set_location_assignment PIN_N24 -to "pcie_rx_i[3](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[2]
set_location_assignment PIN_R24 -to "pcie_rx_i[2](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[1]
set_location_assignment PIN_W24 -to "pcie_rx_i[1](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[0]
set_location_assignment PIN_AA24 -to "pcie_rx_i[0](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[3]
set_location_assignment PIN_M22 -to "pcie_tx_o[3](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[2]
set_location_assignment PIN_P22 -to "pcie_tx_o[2](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[1]
set_location_assignment PIN_V22 -to "pcie_tx_o[1](n)"
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[0]
set_location_assignment PIN_Y22 -to "pcie_tx_o[0](n)"
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to pcie_rstn_i
set_instance_assignment -name IO_STANDARD HCSL -to pcie_refclk_i
set_location_assignment PIN_U24 -to "pcie_refclk_i(n)"
set_instance_assignment -name IO_STANDARD LVDS -to clk125_i
set_location_assignment PIN_C11 -to "clk125_i(n)"
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to leds_o[0]
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
top/gsi_pexaria2a/wishbone_demo/sys_pll.vhd
View file @ 1f7fae25
......@@ -150,9 +150,9 @@ BEGIN
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_divide_by => 25,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_multiply_by => 26,
clk0_phase_shift => "0",
clk1_divide_by => 5,
clk1_duty_cycle => 50,
......@@ -241,11 +241,11 @@ END SYN;
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "5"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "25"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "130.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
......@@ -269,12 +269,12 @@ END SYN;
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "26"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "135.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
......@@ -317,9 +317,9 @@ END SYN;
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "26"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
......
top/gsi_pexaria2a/wishbone_demo/wishbone_demo.sdc
View file @ 1f7fae25
create_clock -period 100Mhz -name pcie_refclk_i [get_ports {pcie_refclk_i}]
create_clock -period 125Mhz -name clk125_i [get_ports {clk125_i}]
derive_pll_clocks
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty
set_false_path -from {*|gc_wfifo:*|r_idx_gray*} -to {*|gc_wfifo:*|r_idx_shift_w*}
set_false_path -from {*|gc_wfifo:*|r_idx_gray*} -to {*|gc_wfifo:*|r_idx_shift_a*}
set_false_path -from {*|gc_wfifo:*|w_idx_gray*} -to {*|gc_wfifo:*|w_idx_shift_r*}
set_clock_groups -asynchronous \
-group { PCIe|* } \
-group { clk125_i sys_pll_inst|*|clk[1] } \
-group { sys_pll_inst|*|clk[0] }
top/gsi_pexaria2a/wishbone_demo/wishbone_demo_top.vhd
View file @ 1f7fae25
......@@ -5,6 +5,7 @@ use IEEE.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.pcie_wb_pkg.all;
use work.gencores_pkg.all;
entity wishbone_demo_top is
port(
......@@ -69,8 +70,14 @@ architecture rtl of wishbone_demo_top is
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
signal clk_sys, clk_cal, rstn, locked : std_logic;
signal clk_sys, clk_cal : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal reset_clks : std_logic_vector(0 downto 0);
signal reset_rstn : std_logic_vector(0 downto 0);
signal gpio_slave_o : t_wishbone_slave_out;
signal gpio_slave_i : t_wishbone_slave_in;
......@@ -83,12 +90,18 @@ begin
port map (
inclk0 => clk125_i, -- 125Mhz oscillator from board
areset => '0',
c0 => clk_sys, -- 126MHz system clk (cannot use external pin as clock for RAM blocks)
c0 => clk_sys, -- 130MHz system clk (to test clock crossing from clk125_i)
c1 => clk_cal, -- 50Mhz calibration clock for Altera reconfig cores
locked => locked); -- '1' when the PLL has locked
-- Hold the entire WB bus reset until the PLL has locked
rstn <= locked;
reset : gc_reset
port map(
free_clk_i => clk125_i,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn);
reset_clks(0) <= clk_sys;
clk_sys_rstn <= reset_rstn(0);
-- The top-most Wishbone B.4 crossbar
interconnect : xwb_sdb_crossbar
......@@ -101,7 +114,7 @@ begin
g_sdb_addr => c_sdb_address)
port map(
clk_sys_i => clk_sys,
rst_n_i => rstn,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
......@@ -114,24 +127,25 @@ begin
generic map(
sdb_addr => c_sdb_address)
port map(
clk125_i => clk_sys, -- Free running clock
clk125_i => clk125_i, -- Free running clock
cal_clk50_i => clk_cal, -- Transceiver global calibration clock
rstn_i => rstn, -- Reset for the PCIe decoder logic
pcie_refclk_i => pcie_refclk_i, -- External PCIe 100MHz bus clock
pcie_rstn_i => pcie_rstn_i, -- External PCIe system reset pin
pcie_rx_i => pcie_rx_i,
pcie_tx_o => pcie_tx_o,
wb_clk => clk_sys, -- Desired clock for the WB bus
wb_rstn_i => clk_sys_rstn,
master_o => cbar_slave_i(0),
master_i => cbar_slave_o(0));
-- The LM32 is master 1+2
lm32_rstn <= clk_sys_rstn and not r_reset;
LM32 : xwb_lm32
generic map(
g_profile => "medium_icache_debug") -- Including JTAG and I-cache (no divide)
port map(
clk_sys_i => clk_sys,
rst_n_i => rstn and not r_reset,
rst_n_i => lm32_rstn,
irq_i => lm32_interrupt,
dwb_o => cbar_slave_i(1), -- Data bus
dwb_i => cbar_slave_o(1),
......@@ -145,7 +159,7 @@ begin
dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => rstn,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(2),
slave_o => cbar_master_i(2),
r_master_i => cbar_slave_o(3),
......@@ -164,7 +178,7 @@ begin
g_slave2_granularity => WORD)
port map(
clk_sys_i => clk_sys,
rst_n_i => rstn,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
......
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