Commit 1b74c39c authored by Dimitris Lampridis's avatar Dimitris Lampridis

[hdl][vic] do not mask RISR register. Closes #4

parent 63af6eeb
......@@ -173,7 +173,7 @@ begin -- syn
end if;
end process;
vic_risr <= (31 downto g_NUM_INTERRUPTS => '0') & irqs_i_reg;
vic_risr <= (31 downto g_NUM_INTERRUPTS => '0') & (irqs_i or swi_mask(g_NUM_INTERRUPTS-1 downto 0));
U_Slave_adapter : entity work.wb_slave_adapter
generic map (
......
......@@ -76,7 +76,7 @@ memory-map:
access: ro
description: Raw Interrupt Status Register
comment: |
Each bit reflects the current state of corresponding IRQ input line.
Each bit reflects the current state of corresponding IRQ input line, irrespective of the state of the IMR register.
- read 1: interrupt line is currently active
- read 0: interrupt line is inactive
- reg:
......
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