diff --git a/platform/altera/wb_pcie/Manifest.py b/platform/altera/wb_pcie/Manifest.py
index 47ab8af31eb582f42e4283fbece25c663768d4c3..be14d29442ea1a6e8686eefe3bc58b82a09c399e 100644
--- a/platform/altera/wb_pcie/Manifest.py
+++ b/platform/altera/wb_pcie/Manifest.py
@@ -9,5 +9,4 @@ files = [
"pcie_tlp.vhd",
"pcie_wb.vhd",
"pcie_wb_pkg.vhd",
- "altera_pcie.sdc",
"ip_compiler_for_pci_express-library/altpcie_rs_serdes.v"]
diff --git a/platform/altera/wb_pcie/altera_pcie.qip b/platform/altera/wb_pcie/altera_pcie.qip
index fc19ec9ebb874f9ecf88860fbceddde3d006ddbd..b90d5b15365d501e9e844c8c6b7e66f76ace8df1 100644
--- a/platform/altera/wb_pcie/altera_pcie.qip
+++ b/platform/altera/wb_pcie/altera_pcie.qip
@@ -1,65 +1,65 @@
set_global_assignment -name IP_TOOL_NAME "IP Compiler for PCI Express"
-set_global_assignment -name IP_TOOL_VERSION "11.1"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altera_pcie.vhd"]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altera_pcie_core.vhd"]
set_global_assignment -name SEARCH_PATH [file join $::quartus(qip_path) "." ]
set_global_assignment -name SEARCH_PATH [file join $::quartus(qip_path) ip_compiler_for_pci_express-library ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcierd_reconfig_clk_pll.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_dlink.ocp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_16p.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen2_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_hip_256_pipen1b.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pclk_align.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x8d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x4d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_250_100.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy0.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy1_62p5.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_16p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_reconfig_4sgx.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_rs_serdes.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_15625.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_dlink.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pclk_align.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_16p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_16p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x4d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pclk_pll.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp_dcram.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x8d_10000.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_dlink.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_100_250.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_15625.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy5_62p5.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen2_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_16p.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_hip_256_pipen1b.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_trans.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_dlink.ocp ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy0.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_100_125.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_15625.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy2.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_15625_125.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcierd_reconfig_clk_pll.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x4d_10000.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_250_100.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy3_62p5.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen2_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_100_250.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_100_125.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x1d_10000.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy3_62p5.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy5_62p5.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_16p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_15625_125.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_rs_serdes.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_phasefifo.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_trans.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x2d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_16p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen2_08p.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pclk_pll.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp_dcram.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x1d_10000.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_125_250.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy2.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x8d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_phasefifo.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_core.cmp ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_core.vhd ]
diff --git a/platform/altera/wb_pcie/altera_pcie.sdc b/platform/altera/wb_pcie/altera_pcie.sdc
index 5a1ac5fd7157531ca42028d64cee069b4ef97af9..e355f21ac837a72472d54b15262a4dd97023a5a3 100644
--- a/platform/altera/wb_pcie/altera_pcie.sdc
+++ b/platform/altera/wb_pcie/altera_pcie.sdc
@@ -1,35 +1,25 @@
# The refclk assignment may need to be renamed to match design top level port name.
# May be desireable to move refclk assignment to a top level SDC file.
-#create_clock -period "100 MHz" -name {refclk} {refclk}
-#create_clock -period "100 MHz" -name {fixedclk_serdes} {fixedclk_serdes}
+create_clock -period "100 MHz" -name {refclk} {refclk}
+create_clock -period "100 MHz" -name {fixedclk_serdes} {fixedclk_serdes}
# testin bits are either static or treated asynchronously, cut the paths.
-#set_false_path -to [get_pins -hierarchical {*hssi_pcie_hip|testin[*]} ]
+set_false_path -to [get_pins -hierarchical {*hssi_pcie_hip|testin[*]} ]
# SERDES Digital Reset inputs are asynchronous
-#set_false_path -to {*|altera_pcie_serdes:serdes|*|tx_digitalreset_reg0c[0]}
-#set_false_path -to {*|altera_pcie_serdes:serdes|*|rx_digitalreset_reg0c[0]}
+set_false_path -to {*|altera_pcie_serdes:serdes|*|tx_digitalreset_reg0c[0]}
+set_false_path -to {*|altera_pcie_serdes:serdes|*|rx_digitalreset_reg0c[0]}
#
# The following multicycle path constraints are only valid if the logic use to sample the tl_cfg_ctl and tl_cfg_sts signals
# are as designed in the Altera provided files altpcierd_tl_cfg_sample.v and altpcierd_tl_cfg_sample.vhd
#
# These constraints are only valid when the altpcierd_tl_cfg_sample module or entity is used with the PCI Express
# Hard IP block in Stratix IV, Arria II, Cyclone IV and HardCopy IV devices.
-# These constraints are not neccesary for PCI Express Hard IP in Stratix V devices.
#
-#global tl_cfg_ctl_wr_setup
-#global tl_cfg_sts_wr_setup
+set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl_wr_hip}] 2
+set_multicycle_path -end -hold -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl_wr_hip}] 1
+set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl_hip[*]}] 3
+set_multicycle_path -end -hold -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl_hip[*]}] 2
#
-# If there are consistent hold time violations for the tl_cfg_ctl_wr signal in your chosen device and design,
-# the multicycle setup constraint for tl_cfg_ctl_wr can be changed from 1 to 0 in the following variable:
-#set tl_cfg_ctl_wr_setup 1
-#
-# If there are consistent hold time violations for the tl_cfg_sts_wr signal in your chosen device and design,
-# the multicycle setup constraint for tl_cfg_sts_wr can be changed from 1 to 0 in the following variable:
-#set tl_cfg_sts_wr_setup 1
-#
-#set_multicycle_path -start -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl_wr}] $tl_cfg_ctl_wr_setup
-#set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl[*]}] [expr $tl_cfg_ctl_wr_setup + 2]
-#set_multicycle_path -end -hold -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl[*]}] 3
-#
-#set_multicycle_path -start -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts_wr}] $tl_cfg_sts_wr_setup
-#set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts[*]}] [expr $tl_cfg_sts_wr_setup + 2]
-#set_multicycle_path -end -hold -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts[*]}] 3
+set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts_wr_hip}] 2
+set_multicycle_path -end -hold -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts_wr_hip}] 1
+set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts_hip[*]}] 3
+set_multicycle_path -end -hold -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts_hip[*]}] 2
diff --git a/platform/altera/wb_pcie/altera_pcie.vhd b/platform/altera/wb_pcie/altera_pcie.vhd
index 8032d140549205b9b7f112b8242eabfa5e065462..5d817eb6f048be4cd25b63bde6e9a650c15da7c9 100644
--- a/platform/altera/wb_pcie/altera_pcie.vhd
+++ b/platform/altera/wb_pcie/altera_pcie.vhd
@@ -1,10 +1,10 @@
--- megafunction wizard: %IP Compiler for PCI Express v11.1%
+-- megafunction wizard: %IP Compiler for PCI Express v12.1%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- ============================================================
---Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
+--Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
@@ -147,7 +147,6 @@ entity altera_pcie is
signal rxpolarity2_ext : OUT STD_LOGIC;
signal rxpolarity3_ext : OUT STD_LOGIC;
signal suc_spd_neg : OUT STD_LOGIC;
- signal test_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
signal tl_cfg_add : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tl_cfg_ctl : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
signal tl_cfg_ctl_wr : OUT STD_LOGIC;
@@ -626,7 +625,6 @@ PORT (
begin
- test_out <= internal_lane_act & internal_ltssm;
txdetectrx_ext <= txdetectrx0_ext;
powerdown_ext <= powerdown0_ext;
rxdata(7 DOWNTO 0) <= A_WE_StdLogicVector((std_logic'(pipe_mode_int) = '1'), rxdata0_ext, rxdata_pcs(7 DOWNTO 0));
@@ -1118,8 +1116,6 @@ begin
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- pipe_mode_int <= std_logic'('0');
--- internal_clk250_out <= '0';
--- internal_clk500_out <= '0';
--synthesis read_comments_as_HDL off
end europa;
@@ -1133,7 +1129,7 @@ end europa;
-- Warning: If you modify this section, IP Compiler for PCI Express Wizard may not be able to reproduce your chosen configuration.
--
-- Retrieval info: <?xml version="1.0"?>
--- Retrieval info: <MEGACORE title="IP Compiler for PCI Express" version="11.1" build="173" iptb_version="1.3.0 Build 173" format_version="120" >
+-- Retrieval info: <MEGACORE title="IP Compiler for PCI Express" version="12.1" build="243" iptb_version="1.3.0 Build 243" format_version="120" >
-- Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.MVCModel" active_core="altpcie_hip_pipen1b" >
-- Retrieval info: <STATIC_SECTION>
-- Retrieval info: <PRIVATES>
@@ -1141,7 +1137,7 @@ end europa;
-- Retrieval info: <PRIVATE name = "p_pcie_phy" value="Arria II GX" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_port_type" value="Native Endpoint" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_tag_supported" value="32" type="INTEGER" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pcie_msi_message_requested" value="4" type="INTEGER" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pcie_msi_message_requested" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_low_priority_virtual_channels" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_retry_fifo_depth" value="64" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_nfts_common_clock" value="255" type="INTEGER" enable="1" />
@@ -1174,7 +1170,7 @@ end europa;
-- Retrieval info: <PRIVATE name = "actualBAR4Size" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "actualBAR5AvalonAddress" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "actualBAR5Size" value="0" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "allowedDeviceFamilies" value="[Stratix III, Stratix II, HardCopy II, Stratix II GX, Stratix, Stratix GX, Cyclone III LS, Cyclone V, Cyclone IV E, Cyclone IV GX, Cyclone III, Cyclone II, Cyclone, MAX II, MAX V, Arria GX, Stratix IV, Stratix V, Arria II GX, HardCopy III, HardCopy IV, Arria II GZ, Arria V, Unknown, None]" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "allowedDeviceFamilies" value="[Stratix II, Arria II GZ, Arria V, Arria V GZ, Stratix GX, Cyclone III, Cyclone II, Cyclone IV E, Cyclone V, HardCopy II, HardCopy III, HardCopy IV, MAX V, Arria II GX, Cyclone IV GX, Stratix II GX, Arria GX, Stratix V, Cyclone III LS, Stratix IV, Stratix III, Cyclone, MAX II, Stratix]" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "altgx_generated" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "clockSource" value="N/A" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "contextState" value="NativeContext" type="STRING" enable="1" />
@@ -1305,7 +1301,7 @@ end europa;
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_5" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_channel_number" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_chk_io" value="0" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pcie_class_code" value="0xFF0000" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pcie_class_code" value="0x068000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_data_credit_vc0" value="112" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_data_credit_vc1" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_completion_data_credit_vc2" value="0" type="INTEGER" enable="1" />
@@ -1325,7 +1321,7 @@ end europa;
-- Retrieval info: <PRIVATE name = "p_pcie_completion_timeout" value="NONE" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_custom_phy_x8" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_custom_rx_buffer_xml" value="0" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pcie_device_id" value="0x0004" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pcie_device_id" value="0x019A" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_disable_L0s" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_dll_active_report_support" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_eie_b4_nfts_count" value="4" type="INTEGER" enable="1" />
@@ -1407,11 +1403,11 @@ end europa;
-- Retrieval info: <PRIVATE name = "p_pcie_slot_capabilities" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_special_phy_gl" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_special_phy_px" value="1" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pcie_subsystem_device_id" value="0x0004" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pcie_subsystem_vendor_id" value="0x1172" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pcie_subsystem_device_id" value="0x019A" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pcie_subsystem_vendor_id" value="0x10DC" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_surprise_down_error_support" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_target_performance_preset" value="High" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pcie_test_out_width" value="9 bits" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pcie_test_out_width" value="None" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_threshold_for_L0s_entry" value="8192 ns" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_total_header_credit_vc0" value="64" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_total_header_credit_vc1" value="0" type="INTEGER" enable="1" />
@@ -1422,7 +1418,7 @@ end europa;
-- Retrieval info: <PRIVATE name = "p_pcie_use_crc_forwarding" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_use_parity" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_variation_name" value="altera_pcie_core" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pcie_vendor_id" value="0x1172" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pcie_vendor_id" value="0x10DC" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_version" value="1.1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_virutal_channels" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "pref_nonp_independent" value="false" type="STRING" enable="1" />
@@ -1493,6 +1489,7 @@ end europa;
-- Retrieval info: <PRIVATE name = "uiPaneSize" value="20" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ui_pcie_msix_pba_bir" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "ui_pcie_msix_table_bir" value="0" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_tx_cdc_full_value" value="12" type="INTEGER" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen_enable">
-- Retrieval info: <PRIVATE name = "language" value="VHDL" type="STRING" enable="1" />
diff --git a/platform/altera/wb_pcie/altera_pcie_core.vhd b/platform/altera/wb_pcie/altera_pcie_core.vhd
index 6b82f8e728f65ddb90e91d4cc6fd7053b054a470..0f0d5fdb42a051e9326b67ddebb51e1188a10739 100644
--- a/platform/altera/wb_pcie/altera_pcie_core.vhd
+++ b/platform/altera/wb_pcie/altera_pcie_core.vhd
@@ -1,8 +1,8 @@
--- Generated by IP Compiler for PCI Express 11.1 [Altera, IP Toolbench 1.3.0 Build 173]
+-- Generated by IP Compiler for PCI Express 12.1 [Altera, IP Toolbench 1.3.0 Build 243]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
--- Copyright (C) 1991-2012 Altera Corporation
+-- Copyright (C) 1991-2013 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
@@ -290,6 +290,7 @@ ARCHITECTURE SYN OF altera_pcie_core IS
COMPONENT altpcie_hip_pipen1b
GENERIC (
+ tx_cdc_full_value : NATURAL;
p_pcie_hip_type : STRING;
retry_buffer_last_active_address : STRING;
advanced_errors : STRING;
@@ -756,6 +757,7 @@ BEGIN
altpcie_hip_pipen1b_inst : altpcie_hip_pipen1b
GENERIC MAP (
+ tx_cdc_full_value => 12,
p_pcie_hip_type => "1",
retry_buffer_last_active_address => "255",
advanced_errors => "false",
@@ -786,15 +788,15 @@ BEGIN
enable_coreclk_out_half_rate => "false",
enable_gen2_core => "false",
gen2_lane_rate_mode => "false",
- vendor_id => 4466,
- device_id => 4,
+ vendor_id => 4316,
+ device_id => 410,
revision_id => 1,
- class_code => 16711680,
- subsystem_vendor_id => 4466,
- subsystem_device_id => 4,
+ class_code => 425984,
+ subsystem_vendor_id => 4316,
+ subsystem_device_id => 410,
port_link_number => 1,
max_payload_size => 1,
- msi_function_count => 2,
+ msi_function_count => 0,
endpoint_l0_latency => 0,
endpoint_l1_latency => 0,
diffclock_nfts_count => 255,
diff --git a/platform/altera/wb_pcie/altera_pcie_serdes.vhd b/platform/altera/wb_pcie/altera_pcie_serdes.vhd
index 8576fdcc641b4688efc2ef5071e51f95aca03671..5c929eab582ceed9c518ff8461e5164b0e0dc86d 100644
--- a/platform/altera/wb_pcie/altera_pcie_serdes.vhd
+++ b/platform/altera/wb_pcie/altera_pcie_serdes.vhd
@@ -14,11 +14,11 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
--- 11.1 Build 173 11/01/2011 SJ Full Version
+-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
---Copyright (C) 1991-2011 Altera Corporation
+--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
@@ -34,7 +34,7 @@
--alt4gxb CBX_AUTO_BLACKBOX="ALL" coreclkout_control_width=1 device_family="Arria II GX" effective_data_rate="2500 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=1 equalizer_dcgain_setting=1 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 hip_enable="true" input_clock_frequency="100.0 MHz" intended_device_speed_grade="4" intended_device_variant="ANY" loopback_mode="none" number_of_channels=4 number_of_quads=1 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="pcie" rateswitch_control_width=1 receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x4" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_inclock0_period=10000 rx_cru_m_divider=0 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=2 rx_data_rate=2500 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_bonding="x4" tx_channel_width=8 tx_clkout_width=4 tx_common_mode="0.65v" tx_data_rate=2500 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=10000 tx_pll_m_divider=0 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=2 tx_slew_rate="off" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk coreclkout fixedclk gxb_powerdown hip_tx_clkout pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked pll_powerdown powerdn rateswitch rateswitchbaseclock reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_elecidleinfersel rx_freqlocked rx_patterndetect rx_pll_locked rx_signaldetect rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle tx_pipedeemph tx_pipemargin
---VERSION_BEGIN 11.1 cbx_alt4gxb 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_tgx 2011:10:31:21:09:45:SJ VERSION_END
+--VERSION_BEGIN 12.1SP1 cbx_alt4gxb 2013:01:31:18:04:54:SJ cbx_mgl 2013:01:31:19:27:12:SJ cbx_tgx 2013:01:31:18:04:54:SJ VERSION_END
LIBRARY arriaii_hssi;
USE arriaii_hssi.all;
@@ -259,7 +259,7 @@
SIGNAL wire_receive_pcs0_phfiforesetout : STD_LOGIC;
SIGNAL wire_receive_pcs0_phfifowrdisableout : STD_LOGIC;
SIGNAL wire_receive_pcs0_pipestatetransdoneout : STD_LOGIC;
--- SIGNAL wire_receive_pcs0_rateswitchout : STD_LOGIC;
+ SIGNAL wire_receive_pcs0_rateswitchout : STD_LOGIC;
SIGNAL wire_receive_pcs0_revparallelfdbkdata : STD_LOGIC_VECTOR (19 DOWNTO 0);
SIGNAL wire_receive_pcs0_signaldetect : STD_LOGIC;
SIGNAL wire_receive_pcs0_xgmdatain : STD_LOGIC_VECTOR (7 DOWNTO 0);
@@ -280,7 +280,7 @@
SIGNAL wire_receive_pcs1_phfiforesetout : STD_LOGIC;
SIGNAL wire_receive_pcs1_phfifowrdisableout : STD_LOGIC;
SIGNAL wire_receive_pcs1_pipestatetransdoneout : STD_LOGIC;
--- SIGNAL wire_receive_pcs1_rateswitchout : STD_LOGIC;
+ SIGNAL wire_receive_pcs1_rateswitchout : STD_LOGIC;
SIGNAL wire_receive_pcs1_revparallelfdbkdata : STD_LOGIC_VECTOR (19 DOWNTO 0);
SIGNAL wire_receive_pcs1_signaldetect : STD_LOGIC;
SIGNAL wire_receive_pcs1_xgmdatain : STD_LOGIC_VECTOR (7 DOWNTO 0);
@@ -301,7 +301,7 @@
SIGNAL wire_receive_pcs2_phfiforesetout : STD_LOGIC;
SIGNAL wire_receive_pcs2_phfifowrdisableout : STD_LOGIC;
SIGNAL wire_receive_pcs2_pipestatetransdoneout : STD_LOGIC;
--- SIGNAL wire_receive_pcs2_rateswitchout : STD_LOGIC;
+ SIGNAL wire_receive_pcs2_rateswitchout : STD_LOGIC;
SIGNAL wire_receive_pcs2_revparallelfdbkdata : STD_LOGIC_VECTOR (19 DOWNTO 0);
SIGNAL wire_receive_pcs2_signaldetect : STD_LOGIC;
SIGNAL wire_receive_pcs2_xgmdatain : STD_LOGIC_VECTOR (7 DOWNTO 0);
@@ -322,7 +322,7 @@
SIGNAL wire_receive_pcs3_phfiforesetout : STD_LOGIC;
SIGNAL wire_receive_pcs3_phfifowrdisableout : STD_LOGIC;
SIGNAL wire_receive_pcs3_pipestatetransdoneout : STD_LOGIC;
--- SIGNAL wire_receive_pcs3_rateswitchout : STD_LOGIC;
+ SIGNAL wire_receive_pcs3_rateswitchout : STD_LOGIC;
SIGNAL wire_receive_pcs3_revparallelfdbkdata : STD_LOGIC_VECTOR (19 DOWNTO 0);
SIGNAL wire_receive_pcs3_signaldetect : STD_LOGIC;
SIGNAL wire_receive_pcs3_xgmdatain : STD_LOGIC_VECTOR (7 DOWNTO 0);
@@ -366,7 +366,7 @@
SIGNAL wire_transmit_pcs0_dprioout : STD_LOGIC_VECTOR (149 DOWNTO 0);
SIGNAL wire_transmit_pcs0_forcedisp : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_transmit_pcs0_forceelecidleout : STD_LOGIC;
- --SIGNAL wire_transmit_pcs0_grayelecidleinferselout : STD_LOGIC_VECTOR (2 DOWNTO 0);
+ SIGNAL wire_transmit_pcs0_grayelecidleinferselout : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_transmit_pcs0_hipdatain : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_transmit_pcs0_phfiforddisableout : STD_LOGIC;
SIGNAL wire_transmit_pcs0_phfiforesetout : STD_LOGIC;
@@ -383,7 +383,7 @@
SIGNAL wire_transmit_pcs1_dprioout : STD_LOGIC_VECTOR (149 DOWNTO 0);
SIGNAL wire_transmit_pcs1_forcedisp : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_transmit_pcs1_forceelecidleout : STD_LOGIC;
- --SIGNAL wire_transmit_pcs1_grayelecidleinferselout : STD_LOGIC_VECTOR (2 DOWNTO 0);
+ SIGNAL wire_transmit_pcs1_grayelecidleinferselout : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_transmit_pcs1_hipdatain : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_transmit_pcs1_phfiforddisableout : STD_LOGIC;
SIGNAL wire_transmit_pcs1_phfiforesetout : STD_LOGIC;
@@ -400,7 +400,7 @@
SIGNAL wire_transmit_pcs2_dprioout : STD_LOGIC_VECTOR (149 DOWNTO 0);
SIGNAL wire_transmit_pcs2_forcedisp : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_transmit_pcs2_forceelecidleout : STD_LOGIC;
- --SIGNAL wire_transmit_pcs2_grayelecidleinferselout : STD_LOGIC_VECTOR (2 DOWNTO 0);
+ SIGNAL wire_transmit_pcs2_grayelecidleinferselout : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_transmit_pcs2_hipdatain : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_transmit_pcs2_phfiforddisableout : STD_LOGIC;
SIGNAL wire_transmit_pcs2_phfiforesetout : STD_LOGIC;
@@ -417,7 +417,7 @@
SIGNAL wire_transmit_pcs3_dprioout : STD_LOGIC_VECTOR (149 DOWNTO 0);
SIGNAL wire_transmit_pcs3_forcedisp : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_transmit_pcs3_forceelecidleout : STD_LOGIC;
- --SIGNAL wire_transmit_pcs3_grayelecidleinferselout : STD_LOGIC_VECTOR (2 DOWNTO 0);
+ SIGNAL wire_transmit_pcs3_grayelecidleinferselout : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_transmit_pcs3_hipdatain : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_transmit_pcs3_phfiforddisableout : STD_LOGIC;
SIGNAL wire_transmit_pcs3_phfiforesetout : STD_LOGIC;
@@ -669,7 +669,7 @@
SIGNAL tx_txdprioout : STD_LOGIC_VECTOR (599 DOWNTO 0);
SIGNAL txdetectrxout : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL w_cent_unit_dpriodisableout1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
- --SIGNAL wire_w_coreclkout_wire_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL wire_w_coreclkout_wire_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_fixedclk_div_in_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_fixedclk_div_in_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_fixedclk_div_in_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -1773,8 +1773,6 @@
END COMPONENT;
BEGIN
- rx_patterndetect <= (others => '0');
- rx_syncstatus <= (others => '0');
wire_gnd <= '0';
wire_vcc <= '1';
wire_w_lg_w_lg_w_lg_fixedclk_sel23w24w25w(0) <= wire_w_lg_w_lg_fixedclk_sel23w24w(0) AND wire_w_fixedclk_div_in_range15w(0);
@@ -1986,7 +1984,7 @@
tx_txdprioout <= ( wire_transmit_pcs3_dprioout & wire_transmit_pcs2_dprioout & wire_transmit_pcs1_dprioout & wire_transmit_pcs0_dprioout);
txdetectrxout <= ( wire_transmit_pcs3_txdetectrx & wire_transmit_pcs2_txdetectrx & wire_transmit_pcs1_txdetectrx & wire_transmit_pcs0_txdetectrx);
w_cent_unit_dpriodisableout1w(0) <= ( wire_cent_unit0_dpriodisableout);
- --wire_w_coreclkout_wire_range206w(0) <= coreclkout_wire(0);
+ wire_w_coreclkout_wire_range206w(0) <= coreclkout_wire(0);
wire_w_fixedclk_div_in_range15w(0) <= fixedclk_div_in(0);
wire_w_fixedclk_div_in_range30w(0) <= fixedclk_div_in(1);
wire_w_fixedclk_div_in_range39w(0) <= fixedclk_div_in(2);
@@ -2570,7 +2568,7 @@
pipestatetransdoneout => wire_receive_pcs0_pipestatetransdoneout,
prbscidenable => rx_prbscidenable(0),
quadreset => cent_unit_quadresetout(0),
- rateswitchout => open, -- wire_receive_pcs0_rateswitchout,
+ rateswitchout => wire_receive_pcs0_rateswitchout,
rateswitchxndone => int_hiprateswtichdone(0),
recoveredclk => rx_pma_clockout(0),
refclk => refclk_pma(0),
@@ -2735,7 +2733,7 @@
pipestatetransdoneout => wire_receive_pcs1_pipestatetransdoneout,
prbscidenable => rx_prbscidenable(1),
quadreset => cent_unit_quadresetout(0),
- rateswitchout => open, -- wire_receive_pcs1_rateswitchout,
+ rateswitchout => wire_receive_pcs1_rateswitchout,
rateswitchxndone => int_hiprateswtichdone(0),
recoveredclk => rx_pma_clockout(1),
refclk => refclk_pma(0),
@@ -2900,7 +2898,7 @@
pipestatetransdoneout => wire_receive_pcs2_pipestatetransdoneout,
prbscidenable => rx_prbscidenable(2),
quadreset => cent_unit_quadresetout(0),
- rateswitchout => open, -- wire_receive_pcs2_rateswitchout,
+ rateswitchout => wire_receive_pcs2_rateswitchout,
rateswitchxndone => int_hiprateswtichdone(0),
recoveredclk => rx_pma_clockout(2),
refclk => refclk_pma(0),
@@ -3065,7 +3063,7 @@
pipestatetransdoneout => wire_receive_pcs3_pipestatetransdoneout,
prbscidenable => rx_prbscidenable(3),
quadreset => cent_unit_quadresetout(0),
- rateswitchout => open, -- wire_receive_pcs3_rateswitchout,
+ rateswitchout => wire_receive_pcs3_rateswitchout,
rateswitchxndone => int_hiprateswtichdone(0),
recoveredclk => rx_pma_clockout(3),
refclk => refclk_pma(0),
@@ -3382,7 +3380,7 @@
forcedisp => wire_transmit_pcs0_forcedisp,
forcedispcompliance => wire_gnd,
forceelecidleout => wire_transmit_pcs0_forceelecidleout,
- grayelecidleinferselout => open, -- wire_transmit_pcs0_grayelecidleinferselout,
+ grayelecidleinferselout => wire_transmit_pcs0_grayelecidleinferselout,
hipdatain => wire_transmit_pcs0_hipdatain,
hipdetectrxloop => tx_detectrxloop(0),
hipelecidleinfersel => rx_elecidleinfersel(2 DOWNTO 0),
@@ -3476,7 +3474,7 @@
forcedisp => wire_transmit_pcs1_forcedisp,
forcedispcompliance => wire_gnd,
forceelecidleout => wire_transmit_pcs1_forceelecidleout,
- grayelecidleinferselout => open, -- wire_transmit_pcs1_grayelecidleinferselout,
+ grayelecidleinferselout => wire_transmit_pcs1_grayelecidleinferselout,
hipdatain => wire_transmit_pcs1_hipdatain,
hipdetectrxloop => tx_detectrxloop(1),
hipelecidleinfersel => rx_elecidleinfersel(5 DOWNTO 3),
@@ -3570,7 +3568,7 @@
forcedisp => wire_transmit_pcs2_forcedisp,
forcedispcompliance => wire_gnd,
forceelecidleout => wire_transmit_pcs2_forceelecidleout,
- grayelecidleinferselout => open, -- wire_transmit_pcs2_grayelecidleinferselout,
+ grayelecidleinferselout => wire_transmit_pcs2_grayelecidleinferselout,
hipdatain => wire_transmit_pcs2_hipdatain,
hipdetectrxloop => tx_detectrxloop(2),
hipelecidleinfersel => rx_elecidleinfersel(8 DOWNTO 6),
@@ -3664,7 +3662,7 @@
forcedisp => wire_transmit_pcs3_forcedisp,
forcedispcompliance => wire_gnd,
forceelecidleout => wire_transmit_pcs3_forceelecidleout,
- grayelecidleinferselout => open, -- wire_transmit_pcs3_grayelecidleinferselout,
+ grayelecidleinferselout => wire_transmit_pcs3_grayelecidleinferselout,
hipdatain => wire_transmit_pcs3_hipdatain,
hipdetectrxloop => tx_detectrxloop(3),
hipelecidleinfersel => rx_elecidleinfersel(11 DOWNTO 9),
diff --git a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v
index 0a75b83604e9962903d95fc86dfab6b465150169..f78dc5d823ef50fcf2188cc01a1a71ce69748068 100644
Binary files a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v and b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v differ
diff --git a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v
index 7fc92fc50aea7adc150aa5910871faffc50101be..e1d47adf3eeeaf2ce9ccc0906b37931c40279c77 100644
Binary files a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v and b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v differ
diff --git a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v
index 22ec7fe4d6ba6749f580ef9c3aa3cdcde61100b2..a961fd9a0e8eef480d4e852dad4ccabfb1345f02 100644
Binary files a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v and b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v differ
diff --git a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v
index 2563ef7b2977bc3ce07f4013b5edd7d18ac268fd..0cf0ff79e83efbf3dfd58b9d20adad1d18204eec 100644
Binary files a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v and b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v differ
diff --git a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v
index 2e0f7e468bdd92dc1538aaccdbe1adb29758c98b..50893b077e2c07411b3f7f72f91aee1972e35d0a 100644
--- a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v
+++ b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v
@@ -84,6 +84,7 @@ module altpcie_rs_serdes (
reg [2:0] pll_locked_r;
reg [6:0] pll_locked_cnt;
reg pll_locked_stable;
+ reg [4:0] ltssm_r;
wire rx_pll_freq_locked_sync;
reg [2:0] rx_pll_freq_locked_r;
@@ -133,10 +134,12 @@ module altpcie_rs_serdes (
if (arst == 1'b1) begin
pll_locked_r[2:0] <= 3'b000;
rx_pll_freq_locked_r[2:0] <= 3'b000;
+ ltssm_r <= 5'h0;
end
else begin
pll_locked_r[2:0] <= {pll_locked_r[1],pll_locked_r[0],pll_locked};
rx_pll_freq_locked_r[2:0] <= {rx_pll_freq_locked_r[1],rx_pll_freq_locked_r[0],rx_pll_freq_locked};
+ ltssm_r <= ltssm;
end
end
assign pll_locked_sync = pll_locked_r[2];
@@ -191,7 +194,7 @@ module altpcie_rs_serdes (
ltssm_detect <= 1'b1;
end
else begin
- if ((ltssm==5'h0)||(ltssm==5'h1)) begin
+ if ((ltssm_r==5'h0)||(ltssm_r==5'h1)) begin
ltssm_detect <= 1'b1;
end
else begin
@@ -356,7 +359,7 @@ module altpcie_rs_serdes (
IDLE_ST_SD: begin
//reset RXPCS on polling.active
- if (ltssm == LTSSM_POL) begin
+ if (ltssm_r == LTSSM_POL) begin
rx_sd_idl_cnt <= (rx_sd_idl_cnt > 20'd10) ? rx_sd_idl_cnt - 20'd10 : 20'h0;
sd_state <= RSET_ST_SD;
end
@@ -374,7 +377,7 @@ module altpcie_rs_serdes (
//Incoming data unstable, back to IDLE_ST_SD iff in detect
if (stable_sd == 1'b0) begin
rx_sd_idl_cnt <= 20'h0;
- sd_state <= (ltssm == LTSSM_DET) ? IDLE_ST_SD : RSET_ST_SD;
+ sd_state <= (ltssm_r == LTSSM_DET) ? IDLE_ST_SD : RSET_ST_SD;
end
else begin
if ((test_sim == 1'b1) & (rx_sd_idl_cnt >= 20'd32)) begin
@@ -397,7 +400,7 @@ module altpcie_rs_serdes (
//Incoming data unstable, back to IDLE_ST_SD iff in detect
if (stable_sd == 1'b0) begin
rx_sd_idl_cnt <= 20'h0;
- sd_state <= (ltssm == LTSSM_DET) ? IDLE_ST_SD : DONE_ST_SD;
+ sd_state <= (ltssm_r == LTSSM_DET) ? IDLE_ST_SD : DONE_ST_SD;
end
end
diff --git a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp
index 7c6199b88b9757e7bd2afcc0e4ed002c6246edae..9d3e09e135ba4c2b4b7e2c8ee013851683cbed62 100644
Binary files a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp and b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp differ
diff --git a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp
index 50800a37083a10c93df1468e2e2d00c406356b54..2f98af0cd09a12fe9078f116430f435e03dd6c94 100644
Binary files a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp and b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp differ
diff --git a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp64_dlink.ocp b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp64_dlink.ocp
index b7612cb9dc9c3022efde20dff8e6688a6645f4be..1a915f753bfefe26e61c2fed3e19cd5891f72834 100644
Binary files a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp64_dlink.ocp and b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp64_dlink.ocp differ
diff --git a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp64_dlink.v b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp64_dlink.v
index 2cf35064c0bff0943d36ede96ae16a960ea12275..93d70988905223b27dddcc2618c036c15973560f 100644
Binary files a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp64_dlink.v and b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp64_dlink.v differ
diff --git a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp64_trans.v b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp64_trans.v
index 98c5a074ec65dcd6c3ea5e25b4f7a37498534185..2109d9415f63a2827f829a415ba2d6910f50ea61 100644
Binary files a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp64_trans.v and b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp64_trans.v differ
diff --git a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp_dcram.v b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp_dcram.v
index 1dd3693552f6239ec60e7417cfc3b12cb1321f8f..fbcffbb0aa6414a8efc52f345c348c12d7256fb4 100644
Binary files a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp_dcram.v and b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexp_dcram.v differ
diff --git a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v
index c6bef3e50033745a83f07fbbf706a04e46f0649d..0ff1226019266d7865ba7a777f212abe02c96a1b 100644
Binary files a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v and b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v differ
diff --git a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp
index 61c556643d9807c4fa36eb8b9d3da1b2a8812296..75f7287e5a626d8a6369381eed2ffcea0f994951 100644
Binary files a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp and b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp differ
diff --git a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp
index 073be79a26e0b1b396ce582193e9b1ad17df3c8a..f115acfcb1f051f328d099e4994dc5d637614eee 100644
Binary files a/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp and b/platform/altera/wb_pcie/ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp differ
diff --git a/platform/altera/wb_pcie/pcie_altera.vhd b/platform/altera/wb_pcie/pcie_altera.vhd
index 9760f5a330099f200fff7ec61b40cff48c9c6987..51528a455582f864ff91745cefcbd85dcb952502 100644
--- a/platform/altera/wb_pcie/pcie_altera.vhd
+++ b/platform/altera/wb_pcie/pcie_altera.vhd
@@ -156,7 +156,6 @@ architecture rtl of pcie_altera is
signal rxpolarity2_ext : out std_logic;
signal rxpolarity3_ext : out std_logic;
signal suc_spd_neg : out std_logic;
- signal test_out : out std_logic_vector (8 downto 0);
signal tl_cfg_add : out std_logic_vector (3 downto 0);
signal tl_cfg_ctl : out std_logic_vector (31 downto 0);
signal tl_cfg_ctl_wr : out std_logic;
@@ -426,7 +425,6 @@ begin
-- Debugging signals
lane_act => open, -- 3 downto 0
test_in => (others => '0'), -- 39 downto 0
- test_out => open, -- 8 downto 0
-- WTF? Not documented
rc_rx_digitalreset => open);