diff --git a/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v b/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
index c84f865e4f75de5fab51e1b4243b5bf58e86c997..4c225acbcc6a2db1a50545336ec28088fff714e7 100644
--- a/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
+++ b/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
@@ -26,58 +26,31 @@
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@@ -398,156 +277,100 @@
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@@ -566,19 +389,16 @@ module lm32_top_full (
interrupt,
-
+
-
-
-
+
I_DAT_I,
I_ACK_I,
I_ERR_I,
I_RTY_I,
-
D_DAT_I,
@@ -586,15 +406,13 @@ module lm32_top_full (
D_ERR_I,
D_RTY_I,
-
+
-
-
-
+
I_DAT_O,
I_ADR_O,
@@ -605,7 +423,6 @@ module lm32_top_full (
I_CTI_O,
I_LOCK_O,
I_BTE_O,
-
D_DAT_O,
@@ -627,25 +444,22 @@ input clk_i;
input rst_i;
-input [ (32-1):0] interrupt;
+input [(32-1):0] interrupt;
-
+
-
-
-
-input [ (32-1):0] I_DAT_I;
+
+input [(32-1):0] I_DAT_I;
input I_ACK_I;
input I_ERR_I;
input I_RTY_I;
-
-input [ (32-1):0] D_DAT_I;
+input [(32-1):0] D_DAT_I;
input D_ACK_I;
input D_ERR_I;
input D_RTY_I;
@@ -654,7 +468,7 @@ input D_RTY_I;
-
+
@@ -665,54 +479,51 @@ input D_RTY_I;
-
-
-
-output [ (32-1):0] I_DAT_O;
-wire [ (32-1):0] I_DAT_O;
-output [ (32-1):0] I_ADR_O;
-wire [ (32-1):0] I_ADR_O;
+
+output [(32-1):0] I_DAT_O;
+wire [(32-1):0] I_DAT_O;
+output [(32-1):0] I_ADR_O;
+wire [(32-1):0] I_ADR_O;
output I_CYC_O;
wire I_CYC_O;
-output [ (4-1):0] I_SEL_O;
-wire [ (4-1):0] I_SEL_O;
+output [(4-1):0] I_SEL_O;
+wire [(4-1):0] I_SEL_O;
output I_STB_O;
wire I_STB_O;
output I_WE_O;
wire I_WE_O;
-output [ (3-1):0] I_CTI_O;
-wire [ (3-1):0] I_CTI_O;
+output [(3-1):0] I_CTI_O;
+wire [(3-1):0] I_CTI_O;
output I_LOCK_O;
wire I_LOCK_O;
-output [ (2-1):0] I_BTE_O;
-wire [ (2-1):0] I_BTE_O;
-
+output [(2-1):0] I_BTE_O;
+wire [(2-1):0] I_BTE_O;
-output [ (32-1):0] D_DAT_O;
-wire [ (32-1):0] D_DAT_O;
-output [ (32-1):0] D_ADR_O;
-wire [ (32-1):0] D_ADR_O;
+output [(32-1):0] D_DAT_O;
+wire [(32-1):0] D_DAT_O;
+output [(32-1):0] D_ADR_O;
+wire [(32-1):0] D_ADR_O;
output D_CYC_O;
wire D_CYC_O;
-output [ (4-1):0] D_SEL_O;
-wire [ (4-1):0] D_SEL_O;
+output [(4-1):0] D_SEL_O;
+wire [(4-1):0] D_SEL_O;
output D_STB_O;
wire D_STB_O;
output D_WE_O;
wire D_WE_O;
-output [ (3-1):0] D_CTI_O;
-wire [ (3-1):0] D_CTI_O;
+output [(3-1):0] D_CTI_O;
+wire [(3-1):0] D_CTI_O;
output D_LOCK_O;
wire D_LOCK_O;
-output [ (2-1):0] D_BTE_O;
-wire [ (2-1):0] D_BTE_O;
+output [(2-1):0] D_BTE_O;
+wire [(2-1):0] D_BTE_O;
-
+
@@ -724,8 +535,7 @@ wire [ (2-1):0] D_BTE_O;
-
-
+
@@ -741,10 +551,7 @@ wire [ (2-1):0] D_BTE_O;
-
-
-
-
+
@@ -797,45 +604,37 @@ endfunction
-
lm32_cpu_full cpu (
.clk_i (clk_i),
-
+
-
.rst_i (rst_i),
-
-
- .interrupt (interrupt),
+ .interrupt (interrupt),
-
+
-
-
+
-
-
-
+
.I_DAT_I (I_DAT_I),
.I_ACK_I (I_ACK_I),
.I_ERR_I (I_ERR_I),
.I_RTY_I (I_RTY_I),
-
.D_DAT_I (D_DAT_I),
@@ -843,7 +642,7 @@ lm32_cpu_full cpu (
.D_ERR_I (D_ERR_I),
.D_RTY_I (D_RTY_I),
-
+
@@ -853,21 +652,17 @@ lm32_cpu_full cpu (
-
-
+
-
-
+
-
-
-
+
.I_DAT_O (I_DAT_O),
.I_ADR_O (I_ADR_O),
@@ -878,8 +673,7 @@ lm32_cpu_full cpu (
.I_CTI_O (I_CTI_O),
.I_LOCK_O (I_LOCK_O),
.I_BTE_O (I_BTE_O),
-
-
+
.D_DAT_O (D_DAT_O),
.D_ADR_O (D_ADR_O),
@@ -892,7 +686,7 @@ lm32_cpu_full cpu (
.D_BTE_O (D_BTE_O)
);
-
+
@@ -905,7 +699,6 @@ lm32_cpu_full cpu (
-
endmodule
@@ -937,10 +730,7 @@ endmodule
-
-
-
-
+
@@ -970,9 +760,9 @@ endmodule
-
+
@@ -1254,24 +1044,15 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
@@ -1283,30 +1064,24 @@ module lm32_mc_arithmetic_full (
rst_i,
stall_d,
kill_x,
-
-
+
divide_d,
modulus_d,
-
-
+
-
-
+
-
operand_0_d,
operand_1_d,
result_x,
-
-
- divide_by_zero_x,
+ divide_by_zero_x,
stall_request_x
);
@@ -1319,36 +1094,30 @@ input clk_i;
input rst_i;
input stall_d;
input kill_x;
-
-
+
input divide_d;
input modulus_d;
-
-
+
-
-
+
+input [(32-1):0] operand_0_d;
+input [(32-1):0] operand_1_d;
-input [ (32-1):0] operand_0_d;
-input [ (32-1):0] operand_1_d;
-
-output [ (32-1):0] result_x;
-reg [ (32-1):0] result_x;
-
-
+output [(32-1):0] result_x;
+reg [(32-1):0] result_x;
+
output divide_by_zero_x;
reg divide_by_zero_x;
-
output stall_request_x;
wire stall_request_x;
@@ -1357,19 +1126,17 @@ wire stall_request_x;
-reg [ (32-1):0] p;
-reg [ (32-1):0] a;
-reg [ (32-1):0] b;
-
-
-wire [32:0] t;
+reg [(32-1):0] p;
+reg [(32-1):0] a;
+reg [(32-1):0] b;
+wire [32:0] t;
-reg [ 2:0] state;
+reg [2:0] state;
reg [5:0] cycles;
-
+
@@ -1379,18 +1146,15 @@ reg [5:0] cycles;
+assign stall_request_x = state != 3'b000;
-assign stall_request_x = state != 3'b000;
+
-
+assign t = {p[32-2:0], a[32-1]} - b;
-assign t = {p[ 32-2:0], a[ 32-1]} - b;
-
-
-
@@ -1399,57 +1163,48 @@ assign t = {p[ 32-2:0], a[ 32-1]} - b;
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
cycles <= {6{1'b0}};
- p <= { 32{1'b0}};
- a <= { 32{1'b0}};
- b <= { 32{1'b0}};
-
+ p <= {32{1'b0}};
+ a <= {32{1'b0}};
+ b <= {32{1'b0}};
+
-
-
-
- divide_by_zero_x <= 1'b0;
+ divide_by_zero_x <= 1'b0;
- result_x <= { 32{1'b0}};
- state <= 3'b000;
+ result_x <= {32{1'b0}};
+ state <= 3'b000;
end
else
begin
-
-
- divide_by_zero_x <= 1'b0;
+ divide_by_zero_x <= 1'b0;
case (state)
- 3'b000:
+ 3'b000:
begin
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
begin
- cycles <= 32;
+ cycles <= 32;
p <= 32'b0;
a <= operand_0_d;
b <= operand_1_d;
-
-
- if (divide_d == 1'b1)
- state <= 3'b011 ;
- if (modulus_d == 1'b1)
- state <= 3'b010 ;
+ if (divide_d == 1'b1)
+ state <= 3'b011 ;
+ if (modulus_d == 1'b1)
+ state <= 3'b010 ;
-
+
-
-
+
@@ -1466,57 +1221,54 @@ begin
-
end
end
-
-
- 3'b011 :
+
+ 3'b011 :
begin
if (t[32] == 1'b0)
begin
p <= t[31:0];
- a <= {a[ 32-2:0], 1'b1};
+ a <= {a[32-2:0], 1'b1};
end
else
begin
- p <= {p[ 32-2:0], a[ 32-1]};
- a <= {a[ 32-2:0], 1'b0};
+ p <= {p[32-2:0], a[32-1]};
+ a <= {a[32-2:0], 1'b0};
end
result_x <= a;
- if ((cycles == 32'd0) || (kill_x == 1'b1))
+ if ((cycles == 32'd0) || (kill_x == 1'b1))
begin
- divide_by_zero_x <= b == { 32{1'b0}};
- state <= 3'b000;
+ divide_by_zero_x <= b == {32{1'b0}};
+ state <= 3'b000;
end
cycles <= cycles - 1'b1;
end
- 3'b010 :
+ 3'b010 :
begin
if (t[32] == 1'b0)
begin
p <= t[31:0];
- a <= {a[ 32-2:0], 1'b1};
+ a <= {a[32-2:0], 1'b1};
end
else
begin
- p <= {p[ 32-2:0], a[ 32-1]};
- a <= {a[ 32-2:0], 1'b0};
+ p <= {p[32-2:0], a[32-1]};
+ a <= {a[32-2:0], 1'b0};
end
result_x <= p;
- if ((cycles == 32'd0) || (kill_x == 1'b1))
+ if ((cycles == 32'd0) || (kill_x == 1'b1))
begin
- divide_by_zero_x <= b == { 32{1'b0}};
- state <= 3'b000;
+ divide_by_zero_x <= b == {32{1'b0}};
+ state <= 3'b000;
end
cycles <= cycles - 1'b1;
end
-
-
+
@@ -1528,9 +1280,8 @@ begin
-
-
+
@@ -1547,7 +1298,6 @@ begin
-
endcase
end
@@ -1618,10 +1368,7 @@ endmodule
-
-
-
-
+
@@ -1651,9 +1398,9 @@ endmodule
-
+
@@ -1938,47 +1685,38 @@ endmodule
-
-
module lm32_cpu_full (
clk_i,
-
+
-
rst_i,
-
-
- interrupt,
+ interrupt,
-
+
-
-
+
-
-
-
+
I_DAT_I,
I_ACK_I,
I_ERR_I,
I_RTY_I,
-
D_DAT_I,
@@ -1986,7 +1724,7 @@ module lm32_cpu_full (
D_ERR_I,
D_RTY_I,
-
+
@@ -1996,21 +1734,17 @@ module lm32_cpu_full (
-
-
+
-
-
+
-
-
-
+
I_DAT_O,
I_ADR_O,
@@ -2021,7 +1755,6 @@ module lm32_cpu_full (
I_CTI_O,
I_LOCK_O,
I_BTE_O,
-
D_DAT_O,
@@ -2039,20 +1772,18 @@ module lm32_cpu_full (
-parameter eba_reset = 32'h00000000;
-
+parameter eba_reset = 32'h00000000;
+
-
-
-
-parameter icache_associativity = 1;
-parameter icache_sets = 256;
-parameter icache_bytes_per_line = 16;
-parameter icache_base_address = 32'h0;
-parameter icache_limit = 32'h7fffffff;
+parameter icache_associativity = 1;
+parameter icache_sets = 256;
+parameter icache_bytes_per_line = 16;
+parameter icache_base_address = 32'h0;
+parameter icache_limit = 32'h7fffffff;
+
@@ -2060,15 +1791,13 @@ parameter icache_limit = 32'h7fffffff;
-
-
-
-parameter dcache_associativity = 1;
-parameter dcache_sets = 256;
-parameter dcache_bytes_per_line = 16;
-parameter dcache_base_address = 32'h0;
-parameter dcache_limit = 32'h7fffffff;
+parameter dcache_associativity = 1;
+parameter dcache_sets = 256;
+parameter dcache_bytes_per_line = 16;
+parameter dcache_base_address = 32'h0;
+parameter dcache_limit = 32'h7fffffff;
+
@@ -2076,28 +1805,21 @@ parameter dcache_limit = 32'h7fffffff;
-
-
+
-
parameter watchpoints = 0;
-
-
+
-
parameter breakpoints = 0;
-
-
-
-parameter interrupts = 32;
-
+parameter interrupts = 32;
+
@@ -2105,42 +1827,35 @@ parameter interrupts = 32;
input clk_i;
-
+
-
input rst_i;
-
-
-input [ (32-1):0] interrupt;
+input [(32-1):0] interrupt;
-
+
-
-
+
-
-
-
-input [ (32-1):0] I_DAT_I;
+
+input [(32-1):0] I_DAT_I;
input I_ACK_I;
input I_ERR_I;
input I_RTY_I;
-
-input [ (32-1):0] D_DAT_I;
+input [(32-1):0] D_DAT_I;
input D_ACK_I;
input D_ERR_I;
input D_RTY_I;
@@ -2149,7 +1864,7 @@ input D_RTY_I;
-
+
@@ -2166,16 +1881,14 @@ input D_RTY_I;
-
-
+
-
-
+
@@ -2186,59 +1899,54 @@ input D_RTY_I;
-
-
-
-output [ (32-1):0] I_DAT_O;
-wire [ (32-1):0] I_DAT_O;
-output [ (32-1):0] I_ADR_O;
-wire [ (32-1):0] I_ADR_O;
+
+output [(32-1):0] I_DAT_O;
+wire [(32-1):0] I_DAT_O;
+output [(32-1):0] I_ADR_O;
+wire [(32-1):0] I_ADR_O;
output I_CYC_O;
wire I_CYC_O;
-output [ (4-1):0] I_SEL_O;
-wire [ (4-1):0] I_SEL_O;
+output [(4-1):0] I_SEL_O;
+wire [(4-1):0] I_SEL_O;
output I_STB_O;
wire I_STB_O;
output I_WE_O;
wire I_WE_O;
-output [ (3-1):0] I_CTI_O;
-wire [ (3-1):0] I_CTI_O;
+output [(3-1):0] I_CTI_O;
+wire [(3-1):0] I_CTI_O;
output I_LOCK_O;
wire I_LOCK_O;
-output [ (2-1):0] I_BTE_O;
-wire [ (2-1):0] I_BTE_O;
-
+output [(2-1):0] I_BTE_O;
+wire [(2-1):0] I_BTE_O;
-output [ (32-1):0] D_DAT_O;
-wire [ (32-1):0] D_DAT_O;
-output [ (32-1):0] D_ADR_O;
-wire [ (32-1):0] D_ADR_O;
+output [(32-1):0] D_DAT_O;
+wire [(32-1):0] D_DAT_O;
+output [(32-1):0] D_ADR_O;
+wire [(32-1):0] D_ADR_O;
output D_CYC_O;
wire D_CYC_O;
-output [ (4-1):0] D_SEL_O;
-wire [ (4-1):0] D_SEL_O;
+output [(4-1):0] D_SEL_O;
+wire [(4-1):0] D_SEL_O;
output D_STB_O;
wire D_STB_O;
output D_WE_O;
wire D_WE_O;
-output [ (3-1):0] D_CTI_O;
-wire [ (3-1):0] D_CTI_O;
+output [(3-1):0] D_CTI_O;
+wire [(3-1):0] D_CTI_O;
output D_LOCK_O;
wire D_LOCK_O;
-output [ (2-1):0] D_BTE_O;
-wire [ (2-1):0] D_BTE_O;
-
+output [(2-1):0] D_BTE_O;
+wire [(2-1):0] D_BTE_O;
-
-reg valid_a;
+reg valid_a;
reg valid_f;
reg valid_d;
@@ -2247,7 +1955,7 @@ reg valid_m;
reg valid_w;
wire q_x;
-wire [ (32-1):0] immediate_d;
+wire [(32-1):0] immediate_d;
wire load_d;
reg load_x;
reg load_m;
@@ -2256,13 +1964,13 @@ wire store_q_x;
wire store_d;
reg store_x;
reg store_m;
-wire [ 1:0] size_d;
-reg [ 1:0] size_x;
+wire [1:0] size_d;
+reg [1:0] size_x;
wire branch_d;
wire branch_predict_d;
wire branch_predict_taken_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
wire bi_unconditional;
wire bi_conditional;
reg branch_x;
@@ -2274,61 +1982,51 @@ reg branch_predict_taken_m;
wire branch_mispredict_taken_m;
wire branch_flushX_m;
wire branch_reg_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
-wire [ 0:0] d_result_sel_0_d;
-wire [ 1:0] d_result_sel_1_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [0:0] d_result_sel_0_d;
+wire [1:0] d_result_sel_1_d;
wire x_result_sel_csr_d;
reg x_result_sel_csr_x;
-
-
+
wire x_result_sel_mc_arith_d;
reg x_result_sel_mc_arith_x;
-
-
+
-
-
-
+
wire x_result_sel_sext_d;
reg x_result_sel_sext_x;
-
wire x_result_sel_logic_d;
reg x_result_sel_logic_x;
-
+
-
wire x_result_sel_add_d;
reg x_result_sel_add_x;
wire m_result_sel_compare_d;
reg m_result_sel_compare_x;
reg m_result_sel_compare_m;
-
-
+
wire m_result_sel_shift_d;
reg m_result_sel_shift_x;
reg m_result_sel_shift_m;
-
wire w_result_sel_load_d;
reg w_result_sel_load_x;
reg w_result_sel_load_m;
reg w_result_sel_load_w;
-
-
+
wire w_result_sel_mul_d;
reg w_result_sel_mul_x;
reg w_result_sel_mul_m;
reg w_result_sel_mul_w;
-
wire x_bypass_enable_d;
reg x_bypass_enable_x;
@@ -2345,33 +2043,31 @@ wire write_enable_q_m;
reg write_enable_w;
wire write_enable_q_w;
wire read_enable_0_d;
-wire [ (5-1):0] read_idx_0_d;
+wire [(5-1):0] read_idx_0_d;
wire read_enable_1_d;
-wire [ (5-1):0] read_idx_1_d;
-wire [ (5-1):0] write_idx_d;
-reg [ (5-1):0] write_idx_x;
-reg [ (5-1):0] write_idx_m;
-reg [ (5-1):0] write_idx_w;
-wire [ (3-1):0] csr_d;
-reg [ (3-1):0] csr_x;
-wire [ (3-1):0] condition_d;
-reg [ (3-1):0] condition_x;
-
+wire [(5-1):0] read_idx_1_d;
+wire [(5-1):0] write_idx_d;
+reg [(5-1):0] write_idx_x;
+reg [(5-1):0] write_idx_m;
+reg [(5-1):0] write_idx_w;
+wire [(3-1):0] csr_d;
+reg [(3-1):0] csr_x;
+wire [(3-1):0] condition_d;
+reg [(3-1):0] condition_x;
+
-
wire scall_d;
reg scall_x;
wire eret_d;
reg eret_x;
wire eret_q_x;
reg eret_m;
-
+
-
-
+
@@ -2380,56 +2076,48 @@ reg eret_m;
-
wire csr_write_enable_d;
reg csr_write_enable_x;
wire csr_write_enable_q_x;
-
+
-
-
-
+
wire bus_error_d;
reg bus_error_x;
reg data_bus_error_exception_m;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] memop_pc_w;
-
-
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] memop_pc_w;
-reg [ (32-1):0] d_result_0;
-reg [ (32-1):0] d_result_1;
-reg [ (32-1):0] x_result;
-reg [ (32-1):0] m_result;
-reg [ (32-1):0] w_result;
-reg [ (32-1):0] operand_0_x;
-reg [ (32-1):0] operand_1_x;
-reg [ (32-1):0] store_operand_x;
-reg [ (32-1):0] operand_m;
-reg [ (32-1):0] operand_w;
+reg [(32-1):0] d_result_0;
+reg [(32-1):0] d_result_1;
+reg [(32-1):0] x_result;
+reg [(32-1):0] m_result;
+reg [(32-1):0] w_result;
+reg [(32-1):0] operand_0_x;
+reg [(32-1):0] operand_1_x;
+reg [(32-1):0] store_operand_x;
+reg [(32-1):0] operand_m;
+reg [(32-1):0] operand_w;
-
-reg [ (32-1):0] reg_data_live_0;
-reg [ (32-1):0] reg_data_live_1;
-reg use_buf;
-reg [ (32-1):0] reg_data_buf_0;
-reg [ (32-1):0] reg_data_buf_1;
-
-
+reg [(32-1):0] reg_data_live_0;
+reg [(32-1):0] reg_data_live_1;
+reg use_buf;
+reg [(32-1):0] reg_data_buf_0;
+reg [(32-1):0] reg_data_buf_1;
-
+
-wire [ (32-1):0] reg_data_0;
-wire [ (32-1):0] reg_data_1;
-reg [ (32-1):0] bypass_data_0;
-reg [ (32-1):0] bypass_data_1;
+wire [(32-1):0] reg_data_0;
+wire [(32-1):0] reg_data_1;
+reg [(32-1):0] bypass_data_0;
+reg [(32-1):0] bypass_data_1;
wire reg_write_enable_q_w;
reg interlock;
@@ -2444,123 +2132,101 @@ wire stall_m;
wire adder_op_d;
reg adder_op_x;
reg adder_op_x_n;
-wire [ (32-1):0] adder_result_x;
+wire [(32-1):0] adder_result_x;
wire adder_overflow_x;
wire adder_carry_n_x;
-wire [ 3:0] logic_op_d;
-reg [ 3:0] logic_op_x;
-wire [ (32-1):0] logic_result_x;
-
-
-
+wire [3:0] logic_op_d;
+reg [3:0] logic_op_x;
+wire [(32-1):0] logic_result_x;
-wire [ (32-1):0] sextb_result_x;
-wire [ (32-1):0] sexth_result_x;
-wire [ (32-1):0] sext_result_x;
+wire [(32-1):0] sextb_result_x;
+wire [(32-1):0] sexth_result_x;
+wire [(32-1):0] sext_result_x;
-
-
+
+
-
wire direction_d;
reg direction_x;
reg direction_m;
-wire [ (32-1):0] shifter_result_m;
-
+wire [(32-1):0] shifter_result_m;
-
+
-
-
+
-
-
-
-wire [ (32-1):0] multiplier_result_w;
+wire [(32-1):0] multiplier_result_w;
-
+
-
-
-
+
wire divide_d;
wire divide_q_d;
wire modulus_d;
wire modulus_q_d;
wire divide_by_zero_x;
-
-
-
-wire mc_stall_request_x;
-wire [ (32-1):0] mc_result_x;
+wire mc_stall_request_x;
+wire [(32-1):0] mc_result_x;
-
-
-wire [ (32-1):0] interrupt_csr_read_data_x;
+wire [(32-1):0] interrupt_csr_read_data_x;
-wire [ (32-1):0] cfg;
-wire [ (32-1):0] cfg2;
-
+wire [(32-1):0] cfg;
+wire [(32-1):0] cfg2;
+
-
-reg [ (32-1):0] csr_read_data_x;
+reg [(32-1):0] csr_read_data_x;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
-
-
-
-wire [ (32-1):0] instruction_f;
+wire [(32-1):0] instruction_f;
-wire [ (32-1):0] instruction_d;
-
-
+wire [(32-1):0] instruction_d;
+
wire iflush;
wire icache_stall_request;
wire icache_restart_request;
wire icache_refill_request;
wire icache_refilling;
-
-
+
@@ -2569,22 +2235,19 @@ wire icache_refilling;
-
-
-
+
wire dflush_x;
reg dflush_m;
wire dcache_stall_request;
wire dcache_restart_request;
wire dcache_refill_request;
wire dcache_refilling;
-
-wire [ (32-1):0] load_data_w;
+wire [(32-1):0] load_data_w;
wire stall_wb_load;
-
+
@@ -2604,7 +2267,6 @@ wire stall_wb_load;
-
wire raw_x_0;
@@ -2621,10 +2283,8 @@ wire cmp_overflow;
wire cmp_carry_n;
reg condition_met_x;
reg condition_met_m;
-
-
+
wire branch_taken_x;
-
wire branch_taken_m;
@@ -2634,19 +2294,17 @@ wire kill_x;
wire kill_m;
wire kill_w;
-reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
-
+reg [(clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
+
-
-reg [ (3-1):0] eid_x;
-
+reg [(3-1):0] eid_x;
+
-
-
+
@@ -2661,57 +2319,43 @@ reg [ (3-1):0] eid_x;
-
wire exception_x;
reg exception_m;
reg exception_w;
wire exception_q_w;
-
-
+
-
-
-
-wire interrupt_exception;
+wire interrupt_exception;
-
+
-
-
-
+
wire instruction_bus_error_exception;
wire data_bus_error_exception;
-
-
-
-wire divide_by_zero_exception;
+wire divide_by_zero_exception;
wire system_call_exception;
-
-
-reg data_bus_error_seen;
+reg data_bus_error_seen;
-
-
-
+
@@ -2767,7 +2411,6 @@ endfunction
-
lm32_instruction_unit_full #(
.associativity (icache_associativity),
.sets (icache_sets),
@@ -2789,50 +2432,40 @@ lm32_instruction_unit_full #(
.kill_f (kill_f),
.branch_predict_taken_d (branch_predict_taken_d),
.branch_predict_address_d (branch_predict_address_d),
-
-
+
.branch_taken_x (branch_taken_x),
.branch_target_x (branch_target_x),
-
.exception_m (exception_m),
.branch_taken_m (branch_taken_m),
.branch_mispredict_taken_m (branch_mispredict_taken_m),
.branch_target_m (branch_target_m),
-
-
- .iflush (iflush),
+ .iflush (iflush),
-
+
-
-
-
+
.dcache_restart_request (dcache_restart_request),
.dcache_refill_request (dcache_refill_request),
.dcache_refilling (dcache_refilling),
-
-
-
+
.i_dat_i (I_DAT_I),
.i_ack_i (I_ACK_I),
.i_err_i (I_ERR_I),
.i_rty_i (I_RTY_I),
-
-
+
-
.pc_f (pc_f),
@@ -2840,20 +2473,16 @@ lm32_instruction_unit_full #(
.pc_x (pc_x),
.pc_m (pc_m),
.pc_w (pc_w),
-
-
+
.icache_stall_request (icache_stall_request),
.icache_restart_request (icache_restart_request),
.icache_refill_request (icache_refill_request),
.icache_refilling (icache_refilling),
-
-
+
-
-
-
+
.i_dat_o (I_DAT_O),
.i_adr_o (I_ADR_O),
@@ -2864,22 +2493,16 @@ lm32_instruction_unit_full #(
.i_cti_o (I_CTI_O),
.i_lock_o (I_LOCK_O),
.i_bte_o (I_BTE_O),
-
-
+
-
-
-
- .bus_error_d (bus_error_d),
+ .bus_error_d (bus_error_d),
-
-
- .instruction_f (instruction_f),
+ .instruction_f (instruction_f),
.instruction_d (instruction_d)
);
@@ -2892,37 +2515,27 @@ lm32_decoder_full decoder (
.d_result_sel_0 (d_result_sel_0_d),
.d_result_sel_1 (d_result_sel_1_d),
.x_result_sel_csr (x_result_sel_csr_d),
-
-
- .x_result_sel_mc_arith (x_result_sel_mc_arith_d),
+ .x_result_sel_mc_arith (x_result_sel_mc_arith_d),
-
+
-
-
-
- .x_result_sel_sext (x_result_sel_sext_d),
+ .x_result_sel_sext (x_result_sel_sext_d),
.x_result_sel_logic (x_result_sel_logic_d),
-
+
-
.x_result_sel_add (x_result_sel_add_d),
.m_result_sel_compare (m_result_sel_compare_d),
-
-
- .m_result_sel_shift (m_result_sel_shift_d),
+ .m_result_sel_shift (m_result_sel_shift_d),
.w_result_sel_load (w_result_sel_load_d),
-
-
- .w_result_sel_mul (w_result_sel_mul_d),
+ .w_result_sel_mul (w_result_sel_mul_d),
.x_bypass_enable (x_bypass_enable_d),
.m_bypass_enable (m_bypass_enable_d),
@@ -2940,45 +2553,36 @@ lm32_decoder_full decoder (
.sign_extend (sign_extend_d),
.adder_op (adder_op_d),
.logic_op (logic_op_d),
-
-
- .direction (direction_d),
+ .direction (direction_d),
-
+
-
-
+
-
-
-
+
.divide (divide_d),
.modulus (modulus_d),
-
.branch (branch_d),
.bi_unconditional (bi_unconditional),
.bi_conditional (bi_conditional),
.branch_reg (branch_reg_d),
.condition (condition_d),
-
+
-
.scall (scall_d),
.eret (eret_d),
-
+
-
-
+
-
.csr_write_enable (csr_write_enable_d)
);
@@ -3012,15 +2616,12 @@ lm32_load_store_unit_full #(
.store_q_m (store_q_m),
.sign_extend_x (sign_extend_x),
.size_x (size_x),
-
-
- .dflush (dflush_m),
+ .dflush (dflush_m),
-
+
-
.d_dat_i (D_DAT_I),
.d_ack_i (D_ACK_I),
@@ -3028,21 +2629,18 @@ lm32_load_store_unit_full #(
.d_rty_i (D_RTY_I),
-
-
+
.dcache_refill_request (dcache_refill_request),
.dcache_restart_request (dcache_restart_request),
.dcache_stall_request (dcache_stall_request),
.dcache_refilling (dcache_refilling),
-
-
+
-
.load_data_w (load_data_w),
.stall_wb_load (stall_wb_load),
@@ -3081,8 +2679,7 @@ lm32_logic_op logic_op (
.logic_result_x (logic_result_x)
);
-
-
+
lm32_shifter shifter (
@@ -3096,11 +2693,9 @@ lm32_shifter shifter (
.shifter_result_m (shifter_result_m)
);
-
-
-
+
lm32_multiplier multiplier (
@@ -3113,11 +2708,9 @@ lm32_multiplier multiplier (
.result (multiplier_result_w)
);
-
-
-
+
lm32_mc_arithmetic_full mc_arithmetic (
@@ -3125,38 +2718,30 @@ lm32_mc_arithmetic_full mc_arithmetic (
.rst_i (rst_i),
.stall_d (stall_d),
.kill_x (kill_x),
-
-
+
.divide_d (divide_q_d),
.modulus_d (modulus_q_d),
-
-
+
-
-
+
-
.operand_0_d (d_result_0),
.operand_1_d (d_result_1),
.result_x (mc_result_x),
-
-
+
.divide_by_zero_x (divide_by_zero_x),
-
.stall_request_x (mc_stall_request_x)
);
-
-
-
+
lm32_interrupt_full interrupt_unit (
@@ -3166,19 +2751,16 @@ lm32_interrupt_full interrupt_unit (
.interrupt (interrupt),
.stall_x (stall_x),
-
+
-
.exception (exception_q_w),
-
.eret_q_x (eret_q_x),
-
+
-
.csr (csr_x),
.csr_write_data (operand_1_x),
.csr_write_enable (csr_write_enable_q_x),
@@ -3187,10 +2769,9 @@ lm32_interrupt_full interrupt_unit (
.csr_read_data (interrupt_csr_read_data_x)
);
-
-
+
@@ -3240,8 +2821,7 @@ lm32_interrupt_full interrupt_unit (
-
-
+
@@ -3284,9 +2864,7 @@ lm32_interrupt_full interrupt_unit (
-
-
-
+
@@ -3347,8 +2925,8 @@ lm32_interrupt_full interrupt_unit (
- always @(posedge clk_i )
- if (rst_i == 1'b1)
+ always @(posedge clk_i )
+ if (rst_i == 1'b1)
begin
regfile_raw_0 <= 1'b0;
regfile_raw_1 <= 1'b0;
@@ -3403,10 +2981,9 @@ lm32_interrupt_full interrupt_unit (
.rdata_o (regfile_data_1)
);
-
-
+
@@ -3479,58 +3056,53 @@ lm32_interrupt_full interrupt_unit (
-
-
-
+
assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
-
-
-
+
-
-assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == 1'b1);
-assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == 1'b1);
-assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == 1'b1);
-assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == 1'b1);
-assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == 1'b1);
-assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == 1'b1);
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == 1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == 1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == 1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == 1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == 1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == 1'b1);
always @(*)
begin
- if ( ( (x_bypass_enable_x == 1'b0)
- && ( ((read_enable_0_d == 1'b1) && (raw_x_0 == 1'b1))
- || ((read_enable_1_d == 1'b1) && (raw_x_1 == 1'b1))
+ if ( ( (x_bypass_enable_x == 1'b0)
+ && ( ((read_enable_0_d == 1'b1) && (raw_x_0 == 1'b1))
+ || ((read_enable_1_d == 1'b1) && (raw_x_1 == 1'b1))
)
)
- || ( (m_bypass_enable_m == 1'b0)
- && ( ((read_enable_0_d == 1'b1) && (raw_m_0 == 1'b1))
- || ((read_enable_1_d == 1'b1) && (raw_m_1 == 1'b1))
+ || ( (m_bypass_enable_m == 1'b0)
+ && ( ((read_enable_0_d == 1'b1) && (raw_m_0 == 1'b1))
+ || ((read_enable_1_d == 1'b1) && (raw_m_1 == 1'b1))
)
)
)
- interlock = 1'b1;
+ interlock = 1'b1;
else
- interlock = 1'b0;
+ interlock = 1'b0;
end
always @(*)
begin
- if (raw_x_0 == 1'b1)
+ if (raw_x_0 == 1'b1)
bypass_data_0 = x_result;
- else if (raw_m_0 == 1'b1)
+ else if (raw_m_0 == 1'b1)
bypass_data_0 = m_result;
- else if (raw_w_0 == 1'b1)
+ else if (raw_w_0 == 1'b1)
bypass_data_0 = w_result;
else
bypass_data_0 = reg_data_0;
@@ -3539,11 +3111,11 @@ end
always @(*)
begin
- if (raw_x_1 == 1'b1)
+ if (raw_x_1 == 1'b1)
bypass_data_1 = x_result;
- else if (raw_m_1 == 1'b1)
+ else if (raw_m_1 == 1'b1)
bypass_data_1 = m_result;
- else if (raw_w_1 == 1'b1)
+ else if (raw_w_1 == 1'b1)
bypass_data_1 = w_result;
else
bypass_data_1 = reg_data_1;
@@ -3571,51 +3143,47 @@ always @(*)
begin
d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
case (d_result_sel_1_d)
- 2'b00: d_result_1 = { 32{1'b0}};
- 2'b01: d_result_1 = bypass_data_1;
- 2'b10: d_result_1 = immediate_d;
- default: d_result_1 = { 32{1'bx}};
+ 2'b00: d_result_1 = {32{1'b0}};
+ 2'b01: d_result_1 = bypass_data_1;
+ 2'b10: d_result_1 = immediate_d;
+ default: d_result_1 = {32{1'bx}};
endcase
end
-
+
-
-
-
+
assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
-assign sext_result_x = size_x == 2'b00 ? sextb_result_x : sexth_result_x;
-
+assign sext_result_x = size_x == 2'b00 ? sextb_result_x : sexth_result_x;
-
+
-
assign cmp_zero = operand_0_x == operand_1_x;
-assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_negative = adder_result_x[32-1];
assign cmp_overflow = adder_overflow_x;
assign cmp_carry_n = adder_carry_n_x;
always @(*)
begin
case (condition_x)
- 3'b000: condition_met_x = 1'b1;
- 3'b110: condition_met_x = 1'b1;
- 3'b001: condition_met_x = cmp_zero;
- 3'b111: condition_met_x = !cmp_zero;
- 3'b010: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
- 3'b101: condition_met_x = cmp_carry_n && !cmp_zero;
- 3'b011: condition_met_x = cmp_negative == cmp_overflow;
- 3'b100: condition_met_x = cmp_carry_n;
+ 3'b000: condition_met_x = 1'b1;
+ 3'b110: condition_met_x = 1'b1;
+ 3'b001: condition_met_x = cmp_zero;
+ 3'b111: condition_met_x = !cmp_zero;
+ 3'b010: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+ 3'b101: condition_met_x = cmp_carry_n && !cmp_zero;
+ 3'b011: condition_met_x = cmp_negative == cmp_overflow;
+ 3'b100: condition_met_x = cmp_carry_n;
default: condition_met_x = 1'bx;
endcase
end
@@ -3625,23 +3193,17 @@ always @(*)
begin
x_result = x_result_sel_add_x ? adder_result_x
: x_result_sel_csr_x ? csr_read_data_x
-
-
- : x_result_sel_sext_x ? sext_result_x
+ : x_result_sel_sext_x ? sext_result_x
-
+
-
-
+
-
-
-
- : x_result_sel_mc_arith_x ? mc_result_x
+ : x_result_sel_mc_arith_x ? mc_result_x
: logic_result_x;
end
@@ -3649,11 +3211,9 @@ end
always @(*)
begin
- m_result = m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
-
-
- : m_result_sel_shift_m ? shifter_result_m
+ m_result = m_result_sel_compare_m ? {{32-1{1'b0}}, condition_met_m}
+ : m_result_sel_shift_m ? shifter_result_m
: operand_m;
end
@@ -3662,124 +3222,102 @@ end
always @(*)
begin
w_result = w_result_sel_load_w ? load_data_w
-
-
- : w_result_sel_mul_w ? multiplier_result_w
+ : w_result_sel_mul_w ? multiplier_result_w
: operand_w;
end
-
-
+
-assign branch_taken_x = (stall_x == 1'b0)
- && ( (branch_x == 1'b1)
- && ((condition_x == 3'b000) || (condition_x == 3'b110))
- && (valid_x == 1'b1)
- && (branch_predict_x == 1'b0)
+assign branch_taken_x = (stall_x == 1'b0)
+ && ( (branch_x == 1'b1)
+ && ((condition_x == 3'b000) || (condition_x == 3'b110))
+ && (valid_x == 1'b1)
+ && (branch_predict_x == 1'b0)
);
-
-assign branch_taken_m = (stall_m == 1'b0)
- && ( ( (branch_m == 1'b1)
- && (valid_m == 1'b1)
- && ( ( (condition_met_m == 1'b1)
- && (branch_predict_taken_m == 1'b0)
+assign branch_taken_m = (stall_m == 1'b0)
+ && ( ( (branch_m == 1'b1)
+ && (valid_m == 1'b1)
+ && ( ( (condition_met_m == 1'b1)
+ && (branch_predict_taken_m == 1'b0)
)
- || ( (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1)
+ || ( (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1)
)
)
)
- || (exception_m == 1'b1)
+ || (exception_m == 1'b1)
);
-assign branch_mispredict_taken_m = (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1);
+assign branch_mispredict_taken_m = (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1);
-assign branch_flushX_m = (stall_m == 1'b0)
- && ( ( (branch_m == 1'b1)
- && (valid_m == 1'b1)
- && ( (condition_met_m == 1'b1)
- || ( (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1)
+assign branch_flushX_m = (stall_m == 1'b0)
+ && ( ( (branch_m == 1'b1)
+ && (valid_m == 1'b1)
+ && ( (condition_met_m == 1'b1)
+ || ( (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1)
)
)
)
- || (exception_m == 1'b1)
+ || (exception_m == 1'b1)
);
-assign kill_f = ( (valid_d == 1'b1)
- && (branch_predict_taken_d == 1'b1)
+assign kill_f = ( (valid_d == 1'b1)
+ && (branch_predict_taken_d == 1'b1)
)
- || (branch_taken_m == 1'b1)
-
-
- || (branch_taken_x == 1'b1)
-
-
-
+ || (branch_taken_m == 1'b1)
+
+ || (branch_taken_x == 1'b1)
- || (icache_refill_request == 1'b1)
+ || (icache_refill_request == 1'b1)
-
-
- || (dcache_refill_request == 1'b1)
-
+
+ || (dcache_refill_request == 1'b1)
;
-assign kill_d = (branch_taken_m == 1'b1)
-
-
- || (branch_taken_x == 1'b1)
-
-
-
+assign kill_d = (branch_taken_m == 1'b1)
+
+ || (branch_taken_x == 1'b1)
- || (icache_refill_request == 1'b1)
+ || (icache_refill_request == 1'b1)
-
-
- || (dcache_refill_request == 1'b1)
-
+
+ || (dcache_refill_request == 1'b1)
;
-assign kill_x = (branch_flushX_m == 1'b1)
-
-
- || (dcache_refill_request == 1'b1)
-
+assign kill_x = (branch_flushX_m == 1'b1)
+
+ || (dcache_refill_request == 1'b1)
;
-assign kill_m = 1'b0
-
-
- || (dcache_refill_request == 1'b1)
-
+assign kill_m = 1'b0
+
+ || (dcache_refill_request == 1'b1)
;
-assign kill_w = 1'b0
-
-
- || (dcache_refill_request == 1'b1)
-
+assign kill_w = 1'b0
+
+ || (dcache_refill_request == 1'b1)
;
-
+
@@ -3791,36 +3329,28 @@ assign kill_w = 1'b0
-
-
+
-
-
-
-assign instruction_bus_error_exception = ( (bus_error_x == 1'b1)
- && (valid_x == 1'b1)
- );
-assign data_bus_error_exception = data_bus_error_seen == 1'b1;
+assign instruction_bus_error_exception = ( (bus_error_x == 1'b1)
+ && (valid_x == 1'b1)
+ );
+assign data_bus_error_exception = data_bus_error_seen == 1'b1;
-
-
-assign divide_by_zero_exception = divide_by_zero_x == 1'b1;
+assign divide_by_zero_exception = divide_by_zero_x == 1'b1;
-assign system_call_exception = ( (scall_x == 1'b1)
-
-
- && (valid_x == 1'b1)
+assign system_call_exception = ( (scall_x == 1'b1)
+ && (valid_x == 1'b1)
);
-
+
@@ -3851,43 +3381,32 @@ assign system_call_exception = ( (scall_x == 1'b1)
-
-assign exception_x = (system_call_exception == 1'b1)
-
-
- || (instruction_bus_error_exception == 1'b1)
- || (data_bus_error_exception == 1'b1)
+assign exception_x = (system_call_exception == 1'b1)
+ || (instruction_bus_error_exception == 1'b1)
+ || (data_bus_error_exception == 1'b1)
-
-
- || (divide_by_zero_exception == 1'b1)
+ || (divide_by_zero_exception == 1'b1)
-
-
- || ( (interrupt_exception == 1'b1)
-
+
+ || ( (interrupt_exception == 1'b1)
+
-
-
-
- && (store_q_m == 1'b0)
- && (D_CYC_O == 1'b0)
+ && (store_q_m == 1'b0)
+ && (D_CYC_O == 1'b0)
)
-
;
-
always @(*)
begin
-
+
@@ -3902,72 +3421,61 @@ begin
-
-
-
- if (data_bus_error_exception == 1'b1)
- eid_x = 3'h4;
+
+ if (data_bus_error_exception == 1'b1)
+ eid_x = 3'h4;
else
- if (instruction_bus_error_exception == 1'b1)
- eid_x = 3'h2;
+ if (instruction_bus_error_exception == 1'b1)
+ eid_x = 3'h2;
else
-
-
+
-
-
-
- if (divide_by_zero_exception == 1'b1)
- eid_x = 3'h5;
- else
+ if (divide_by_zero_exception == 1'b1)
+ eid_x = 3'h5;
+ else
-
-
- if ( (interrupt_exception == 1'b1)
-
+
+ if ( (interrupt_exception == 1'b1)
+
-
)
- eid_x = 3'h6;
+ eid_x = 3'h6;
else
-
- eid_x = 3'h7;
+ eid_x = 3'h7;
end
-assign stall_a = (stall_f == 1'b1);
+assign stall_a = (stall_f == 1'b1);
-assign stall_f = (stall_d == 1'b1);
+assign stall_f = (stall_d == 1'b1);
-assign stall_d = (stall_x == 1'b1)
- || ( (interlock == 1'b1)
- && (kill_d == 1'b0)
+assign stall_d = (stall_x == 1'b1)
+ || ( (interlock == 1'b1)
+ && (kill_d == 1'b0)
)
- || ( ( (eret_d == 1'b1)
- || (scall_d == 1'b1)
-
-
- || (bus_error_d == 1'b1)
+ || ( ( (eret_d == 1'b1)
+ || (scall_d == 1'b1)
+ || (bus_error_d == 1'b1)
)
- && ( (load_q_x == 1'b1)
- || (load_q_m == 1'b1)
- || (store_q_x == 1'b1)
- || (store_q_m == 1'b1)
- || (D_CYC_O == 1'b1)
+ && ( (load_q_x == 1'b1)
+ || (load_q_m == 1'b1)
+ || (store_q_x == 1'b1)
+ || (store_q_m == 1'b1)
+ || (D_CYC_O == 1'b1)
)
- && (kill_d == 1'b0)
+ && (kill_d == 1'b0)
)
-
+
@@ -3979,22 +3487,19 @@ assign stall_d = (stall_x == 1'b1)
-
- || ( (csr_write_enable_d == 1'b1)
- && (load_q_x == 1'b1)
+ || ( (csr_write_enable_d == 1'b1)
+ && (load_q_x == 1'b1)
)
;
-assign stall_x = (stall_m == 1'b1)
-
-
- || ( (mc_stall_request_x == 1'b1)
- && (kill_x == 1'b0)
- )
+assign stall_x = (stall_m == 1'b1)
+ || ( (mc_stall_request_x == 1'b1)
+ && (kill_x == 1'b0)
+ )
-
+
@@ -4003,16 +3508,14 @@ assign stall_x = (stall_m == 1'b1)
-
;
-assign stall_m = (stall_wb_load == 1'b1)
-
+assign stall_m = (stall_wb_load == 1'b1)
+
-
- || ( (D_CYC_O == 1'b1)
- && ( (store_m == 1'b1)
+ || ( (D_CYC_O == 1'b1)
+ && ( (store_m == 1'b1)
@@ -4026,279 +3529,220 @@ assign stall_m = (stall_wb_load == 1'b1)
-
-
- || ((store_x == 1'b1) && (interrupt_exception == 1'b1))
+ || ((store_x == 1'b1) && (interrupt_exception == 1'b1))
- || (load_m == 1'b1)
- || (load_x == 1'b1)
+ || (load_m == 1'b1)
+ || (load_x == 1'b1)
)
)
-
-
-
- || (dcache_stall_request == 1'b1)
+ || (dcache_stall_request == 1'b1)
-
-
- || (icache_stall_request == 1'b1)
- || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1)))
+ || (icache_stall_request == 1'b1)
+ || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1)))
+
-
-
+
-
;
-
-
-assign q_d = (valid_d == 1'b1) && (kill_d == 1'b0);
+assign q_d = (valid_d == 1'b1) && (kill_d == 1'b0);
-
+
-
-
+
-
-
-
-assign divide_q_d = (divide_d == 1'b1) && (q_d == 1'b1);
-assign modulus_q_d = (modulus_d == 1'b1) && (q_d == 1'b1);
+assign divide_q_d = (divide_d == 1'b1) && (q_d == 1'b1);
+assign modulus_q_d = (modulus_d == 1'b1) && (q_d == 1'b1);
-assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
-assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
-assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
-
+assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
+assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
+
-
-assign load_q_x = (load_x == 1'b1)
- && (q_x == 1'b1)
-
+assign load_q_x = (load_x == 1'b1)
+ && (q_x == 1'b1)
+
-
;
-assign store_q_x = (store_x == 1'b1)
- && (q_x == 1'b1)
-
+assign store_q_x = (store_x == 1'b1)
+ && (q_x == 1'b1)
+
-
;
-
+
-
-assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
-assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
-assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
+assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
+assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
+assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
+
-
-assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1));
-
+assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1));
-assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
-assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
-assign write_enable_q_w = (write_enable_w == 1'b1) && (valid_w == 1'b1);
+assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
+assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
+assign write_enable_q_w = (write_enable_w == 1'b1) && (valid_w == 1'b1);
-assign reg_write_enable_q_w = (write_enable_w == 1'b1) && (kill_w == 1'b0) && (valid_w == 1'b1);
+assign reg_write_enable_q_w = (write_enable_w == 1'b1) && (kill_w == 1'b0) && (valid_w == 1'b1);
assign cfg = {
- 6'h02,
+ 6'h02,
watchpoints[3:0],
breakpoints[3:0],
interrupts[5:0],
-
+
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
+ 1'b1,
-
-
- 1'b1,
-
+
+ 1'b1,
-
+
- 1'b1,
+ 1'b0,
-
+
+ 1'b0,
- 1'b0,
+ 1'b1,
-
-
- 1'b0,
+ 1'b1,
-
-
- 1'b1,
-
-
-
-
- 1'b1,
-
-
-
-
+ 1'b1,
- 1'b1,
-
-
-
- 1'b1
-
-
+ 1'b1
+
};
assign cfg2 = {
30'b0,
-
+
+ 1'b0,
- 1'b0,
-
-
-
- 1'b0
-
+ 1'b0
};
-
-
-assign iflush = ( (csr_write_enable_d == 1'b1)
- && (csr_d == 3'h3)
- && (stall_d == 1'b0)
- && (kill_d == 1'b0)
- && (valid_d == 1'b1))
+
+assign iflush = ( (csr_write_enable_d == 1'b1)
+ && (csr_d == 3'h3)
+ && (stall_d == 1'b0)
+ && (kill_d == 1'b0)
+ && (valid_d == 1'b1))
-
+
-
;
-
+assign dflush_x = ( (csr_write_enable_q_x == 1'b1)
+ && (csr_x == 3'h4))
-assign dflush_x = ( (csr_write_enable_q_x == 1'b1)
- && (csr_x == 3'h4))
-
-
+
-
;
-
-assign csr_d = read_idx_0_d[ (3-1):0];
+assign csr_d = read_idx_0_d[(3-1):0];
always @(*)
begin
case (csr_x)
-
-
- 3'h0,
- 3'h1,
- 3'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 3'h0,
+ 3'h1,
+ 3'h2: csr_read_data_x = interrupt_csr_read_data_x;
-
+
-
- 3'h6: csr_read_data_x = cfg;
- 3'h7: csr_read_data_x = {eba, 8'h00};
-
+ 3'h6: csr_read_data_x = cfg;
+ 3'h7: csr_read_data_x = {eba, 8'h00};
+
-
-
+
-
- 3'ha: csr_read_data_x = cfg2;
+ 3'ha: csr_read_data_x = cfg2;
- default: csr_read_data_x = { 32{1'bx}};
+ default: csr_read_data_x = {32{1'bx}};
endcase
end
@@ -4307,23 +3751,22 @@ end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if (rst_i == 1'b1)
+ eba <= eba_reset[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 3'h7) && (stall_x == 1'b0))
- eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 3'h7) && (stall_x == 1'b0))
+ eba <= operand_1_x[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
-
end
end
-
+
@@ -4342,8 +3785,7 @@ end
-
-
+
@@ -4353,47 +3795,42 @@ end
+
-
-
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- data_bus_error_seen <= 1'b0;
+ if (rst_i == 1'b1)
+ data_bus_error_seen <= 1'b0;
else
begin
- if ((D_ERR_I == 1'b1) && (D_CYC_O == 1'b1))
- data_bus_error_seen <= 1'b1;
+ if ((D_ERR_I == 1'b1) && (D_CYC_O == 1'b1))
+ data_bus_error_seen <= 1'b1;
- if ((exception_m == 1'b1) && (kill_m == 1'b0))
- data_bus_error_seen <= 1'b0;
+ if ((exception_m == 1'b1) && (kill_m == 1'b0))
+ data_bus_error_seen <= 1'b0;
end
end
-
-
-
-
-
+
+
always @(*)
begin
- if ( (icache_refill_request == 1'b1)
- || (dcache_refill_request == 1'b1)
+ if ( (icache_refill_request == 1'b1)
+ || (dcache_refill_request == 1'b1)
)
- valid_a = 1'b0;
- else if ( (icache_restart_request == 1'b1)
- || (dcache_restart_request == 1'b1)
+ valid_a = 1'b0;
+ else if ( (icache_restart_request == 1'b1)
+ || (dcache_restart_request == 1'b1)
)
- valid_a = 1'b1;
+ valid_a = 1'b1;
else
valid_a = !icache_refilling && !dcache_refilling;
end
-
+
@@ -4407,7 +3844,6 @@ end
-
@@ -4419,255 +3855,208 @@ end
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- valid_f <= 1'b0;
- valid_d <= 1'b0;
- valid_x <= 1'b0;
- valid_m <= 1'b0;
- valid_w <= 1'b0;
+ valid_f <= 1'b0;
+ valid_d <= 1'b0;
+ valid_x <= 1'b0;
+ valid_m <= 1'b0;
+ valid_w <= 1'b0;
end
else
begin
- if ((kill_f == 1'b1) || (stall_a == 1'b0))
-
-
- valid_f <= valid_a;
+ if ((kill_f == 1'b1) || (stall_a == 1'b0))
-
+ valid_f <= valid_a;
+
- else if (stall_f == 1'b0)
- valid_f <= 1'b0;
+ else if (stall_f == 1'b0)
+ valid_f <= 1'b0;
- if (kill_d == 1'b1)
- valid_d <= 1'b0;
- else if (stall_f == 1'b0)
+ if (kill_d == 1'b1)
+ valid_d <= 1'b0;
+ else if (stall_f == 1'b0)
valid_d <= valid_f & !kill_f;
- else if (stall_d == 1'b0)
- valid_d <= 1'b0;
+ else if (stall_d == 1'b0)
+ valid_d <= 1'b0;
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
valid_x <= valid_d & !kill_d;
- else if (kill_x == 1'b1)
- valid_x <= 1'b0;
- else if (stall_x == 1'b0)
- valid_x <= 1'b0;
-
- if (kill_m == 1'b1)
- valid_m <= 1'b0;
- else if (stall_x == 1'b0)
+ else if (kill_x == 1'b1)
+ valid_x <= 1'b0;
+ else if (stall_x == 1'b0)
+ valid_x <= 1'b0;
+
+ if (kill_m == 1'b1)
+ valid_m <= 1'b0;
+ else if (stall_x == 1'b0)
valid_m <= valid_x & !kill_x;
- else if (stall_m == 1'b0)
- valid_m <= 1'b0;
+ else if (stall_m == 1'b0)
+ valid_m <= 1'b0;
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
valid_w <= valid_m & !kill_m;
else
- valid_w <= 1'b0;
+ valid_w <= 1'b0;
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
-
+
-
- operand_0_x <= { 32{1'b0}};
- operand_1_x <= { 32{1'b0}};
- store_operand_x <= { 32{1'b0}};
- branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- x_result_sel_csr_x <= 1'b0;
-
-
- x_result_sel_mc_arith_x <= 1'b0;
+ operand_0_x <= {32{1'b0}};
+ operand_1_x <= {32{1'b0}};
+ store_operand_x <= {32{1'b0}};
+ branch_target_x <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ x_result_sel_csr_x <= 1'b0;
+ x_result_sel_mc_arith_x <= 1'b0;
-
+
-
-
-
- x_result_sel_sext_x <= 1'b0;
+ x_result_sel_sext_x <= 1'b0;
- x_result_sel_logic_x <= 1'b0;
-
+ x_result_sel_logic_x <= 1'b0;
+
-
- x_result_sel_add_x <= 1'b0;
- m_result_sel_compare_x <= 1'b0;
-
-
- m_result_sel_shift_x <= 1'b0;
+ x_result_sel_add_x <= 1'b0;
+ m_result_sel_compare_x <= 1'b0;
+ m_result_sel_shift_x <= 1'b0;
- w_result_sel_load_x <= 1'b0;
-
-
- w_result_sel_mul_x <= 1'b0;
+ w_result_sel_load_x <= 1'b0;
+ w_result_sel_mul_x <= 1'b0;
- x_bypass_enable_x <= 1'b0;
- m_bypass_enable_x <= 1'b0;
- write_enable_x <= 1'b0;
- write_idx_x <= { 5{1'b0}};
- csr_x <= { 3{1'b0}};
- load_x <= 1'b0;
- store_x <= 1'b0;
- size_x <= { 2{1'b0}};
- sign_extend_x <= 1'b0;
- adder_op_x <= 1'b0;
- adder_op_x_n <= 1'b0;
+ x_bypass_enable_x <= 1'b0;
+ m_bypass_enable_x <= 1'b0;
+ write_enable_x <= 1'b0;
+ write_idx_x <= {5{1'b0}};
+ csr_x <= {3{1'b0}};
+ load_x <= 1'b0;
+ store_x <= 1'b0;
+ size_x <= {2{1'b0}};
+ sign_extend_x <= 1'b0;
+ adder_op_x <= 1'b0;
+ adder_op_x_n <= 1'b0;
logic_op_x <= 4'h0;
-
-
- direction_x <= 1'b0;
+ direction_x <= 1'b0;
-
+
-
- branch_x <= 1'b0;
- branch_predict_x <= 1'b0;
- branch_predict_taken_x <= 1'b0;
- condition_x <= 3'b000;
-
+ branch_x <= 1'b0;
+ branch_predict_x <= 1'b0;
+ branch_predict_taken_x <= 1'b0;
+ condition_x <= 3'b000;
+
-
- scall_x <= 1'b0;
- eret_x <= 1'b0;
-
+ scall_x <= 1'b0;
+ eret_x <= 1'b0;
+
-
-
-
- bus_error_x <= 1'b0;
- data_bus_error_exception_m <= 1'b0;
+ bus_error_x <= 1'b0;
+ data_bus_error_exception_m <= 1'b0;
- csr_write_enable_x <= 1'b0;
- operand_m <= { 32{1'b0}};
- branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- m_result_sel_compare_m <= 1'b0;
-
-
- m_result_sel_shift_m <= 1'b0;
+ csr_write_enable_x <= 1'b0;
+ operand_m <= {32{1'b0}};
+ branch_target_m <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ m_result_sel_compare_m <= 1'b0;
+ m_result_sel_shift_m <= 1'b0;
- w_result_sel_load_m <= 1'b0;
-
-
- w_result_sel_mul_m <= 1'b0;
+ w_result_sel_load_m <= 1'b0;
+ w_result_sel_mul_m <= 1'b0;
- m_bypass_enable_m <= 1'b0;
- branch_m <= 1'b0;
- branch_predict_m <= 1'b0;
- branch_predict_taken_m <= 1'b0;
- exception_m <= 1'b0;
- load_m <= 1'b0;
- store_m <= 1'b0;
-
-
- direction_m <= 1'b0;
+ m_bypass_enable_m <= 1'b0;
+ branch_m <= 1'b0;
+ branch_predict_m <= 1'b0;
+ branch_predict_taken_m <= 1'b0;
+ exception_m <= 1'b0;
+ load_m <= 1'b0;
+ store_m <= 1'b0;
+ direction_m <= 1'b0;
- write_enable_m <= 1'b0;
- write_idx_m <= { 5{1'b0}};
- condition_met_m <= 1'b0;
-
-
- dflush_m <= 1'b0;
+ write_enable_m <= 1'b0;
+ write_idx_m <= {5{1'b0}};
+ condition_met_m <= 1'b0;
+ dflush_m <= 1'b0;
-
+
-
- operand_w <= { 32{1'b0}};
- w_result_sel_load_w <= 1'b0;
-
-
- w_result_sel_mul_w <= 1'b0;
+ operand_w <= {32{1'b0}};
+ w_result_sel_load_w <= 1'b0;
+ w_result_sel_mul_w <= 1'b0;
- write_idx_w <= { 5{1'b0}};
- write_enable_w <= 1'b0;
-
+ write_idx_w <= {5{1'b0}};
+ write_enable_w <= 1'b0;
+
+ exception_w <= 1'b0;
- exception_w <= 1'b0;
-
-
-
-
- memop_pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ memop_pc_w <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
end
else
begin
- if (stall_x == 1'b0)
+ if (stall_x == 1'b0)
begin
-
+
-
operand_0_x <= d_result_0;
operand_1_x <= d_result_1;
store_operand_x <= bypass_data_1;
- branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;
+ branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;
x_result_sel_csr_x <= x_result_sel_csr_d;
-
-
- x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
+ x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
-
+
-
-
-
- x_result_sel_sext_x <= x_result_sel_sext_d;
+ x_result_sel_sext_x <= x_result_sel_sext_d;
x_result_sel_logic_x <= x_result_sel_logic_d;
-
+
-
x_result_sel_add_x <= x_result_sel_add_d;
m_result_sel_compare_x <= m_result_sel_compare_d;
-
-
- m_result_sel_shift_x <= m_result_sel_shift_d;
+ m_result_sel_shift_x <= m_result_sel_shift_d;
w_result_sel_load_x <= w_result_sel_load_d;
-
-
- w_result_sel_mul_x <= w_result_sel_mul_d;
+ w_result_sel_mul_x <= w_result_sel_mul_d;
x_bypass_enable_x <= x_bypass_enable_d;
m_bypass_enable_x <= m_bypass_enable_d;
@@ -4683,82 +4072,65 @@ begin
adder_op_x <= adder_op_d;
adder_op_x_n <= ~adder_op_d;
logic_op_x <= logic_op_d;
-
-
- direction_x <= direction_d;
+ direction_x <= direction_d;
-
+
-
condition_x <= condition_d;
csr_write_enable_x <= csr_write_enable_d;
-
+
-
scall_x <= scall_d;
-
-
- bus_error_x <= bus_error_d;
+ bus_error_x <= bus_error_d;
eret_x <= eret_d;
-
+
-
write_enable_x <= write_enable_d;
end
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
operand_m <= x_result;
m_result_sel_compare_m <= m_result_sel_compare_x;
-
-
- m_result_sel_shift_m <= m_result_sel_shift_x;
+ m_result_sel_shift_m <= m_result_sel_shift_x;
- if (exception_x == 1'b1)
+ if (exception_x == 1'b1)
begin
- w_result_sel_load_m <= 1'b0;
-
-
- w_result_sel_mul_m <= 1'b0;
+ w_result_sel_load_m <= 1'b0;
+ w_result_sel_mul_m <= 1'b0;
end
else
begin
w_result_sel_load_m <= w_result_sel_load_x;
-
-
- w_result_sel_mul_m <= w_result_sel_mul_x;
+ w_result_sel_mul_m <= w_result_sel_mul_x;
end
m_bypass_enable_m <= m_bypass_enable_x;
-
-
- direction_m <= direction_x;
+ direction_m <= direction_x;
load_m <= load_x;
store_m <= store_x;
-
-
+
branch_m <= branch_x && !branch_taken_x;
-
+
-
-
+
@@ -4771,15 +4143,13 @@ begin
-
- if (exception_x == 1'b1)
- write_idx_m <= 5'd30;
+ if (exception_x == 1'b1)
+ write_idx_m <= 5'd30;
else
write_idx_m <= write_idx_x;
-
condition_met_m <= condition_met_x;
-
+
@@ -4790,119 +4160,99 @@ begin
+ branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
- branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
-
-
-
-
-
- dflush_m <= dflush_x;
+ dflush_m <= dflush_x;
eret_m <= eret_q_x;
-
+
-
- write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
-
+ write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
+
-
end
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
- if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
- exception_m <= 1'b1;
+ if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
+ exception_m <= 1'b1;
else
- exception_m <= 1'b0;
-
-
- data_bus_error_exception_m <= (data_bus_error_exception == 1'b1)
-
+ exception_m <= 1'b0;
+
+ data_bus_error_exception_m <= (data_bus_error_exception == 1'b1)
+
-
;
-
end
-
-
- operand_w <= exception_m == 1'b1 ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
-
+ operand_w <= exception_m == 1'b1 ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
+
w_result_sel_load_w <= w_result_sel_load_m;
-
-
- w_result_sel_mul_w <= w_result_sel_mul_m;
+ w_result_sel_mul_w <= w_result_sel_mul_m;
write_idx_w <= write_idx_m;
-
+
-
write_enable_w <= write_enable_m;
-
+
-
exception_w <= exception_m;
-
-
-
- if ( (stall_m == 1'b0)
- && ( (load_q_m == 1'b1)
- || (store_q_m == 1'b1)
+
+ if ( (stall_m == 1'b0)
+ && ( (load_q_m == 1'b1)
+ || (store_q_m == 1'b1)
)
)
memop_pc_w <= pc_m;
-
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- use_buf <= 1'b0;
- reg_data_buf_0 <= { 32{1'b0}};
- reg_data_buf_1 <= { 32{1'b0}};
+ use_buf <= 1'b0;
+ reg_data_buf_0 <= {32{1'b0}};
+ reg_data_buf_1 <= {32{1'b0}};
end
else
begin
- if (stall_d == 1'b0)
- use_buf <= 1'b0;
- else if (use_buf == 1'b0)
+ if (stall_d == 1'b0)
+ use_buf <= 1'b0;
+ else if (use_buf == 1'b0)
begin
reg_data_buf_0 <= reg_data_live_0;
reg_data_buf_1 <= reg_data_live_1;
- use_buf <= 1'b1;
+ use_buf <= 1'b1;
end
- if (reg_write_enable_q_w == 1'b1)
+ if (reg_write_enable_q_w == 1'b1)
begin
if (write_idx_w == read_idx_0_d)
reg_data_buf_0 <= w_result;
@@ -4911,13 +4261,11 @@ begin
end
end
end
-
-
-
+
@@ -4961,8 +4309,7 @@ end
-
-
+
@@ -5021,7 +4368,6 @@ end
-
@@ -5034,13 +4380,9 @@ end
initial
begin
-
-
- reg_0.ram[0] = { 32{1'b0}};
- reg_1.ram[0] = { 32{1'b0}};
-
+
end
@@ -5088,10 +4430,7 @@ endmodule
-
-
-
-
+
@@ -5121,9 +4460,9 @@ endmodule
-
+
@@ -5408,8 +4747,6 @@ endmodule
-
-
@@ -5436,15 +4773,12 @@ module lm32_load_store_unit_full (
store_q_m,
sign_extend_x,
size_x,
-
-
- dflush,
+ dflush,
-
+
-
d_dat_i,
d_ack_i,
@@ -5452,20 +4786,17 @@ module lm32_load_store_unit_full (
d_rty_i,
-
-
+
dcache_refill_request,
dcache_restart_request,
dcache_stall_request,
dcache_refilling,
-
-
+
-
load_data_w,
stall_wb_load,
@@ -5510,9 +4841,9 @@ input kill_x;
input kill_m;
input exception_m;
-input [ (32-1):0] store_operand_x;
-input [ (32-1):0] load_store_address_x;
-input [ (32-1):0] load_store_address_m;
+input [(32-1):0] store_operand_x;
+input [(32-1):0] load_store_address_x;
+input [(32-1):0] load_store_address_m;
input [1:0] load_store_address_w;
input load_x;
input store_x;
@@ -5521,20 +4852,17 @@ input store_q_x;
input load_q_m;
input store_q_m;
input sign_extend_x;
-input [ 1:0] size_x;
-
-
+input [1:0] size_x;
-input dflush;
+input dflush;
-
+
-
-input [ (32-1):0] d_dat_i;
+input [(32-1):0] d_dat_i;
input d_ack_i;
input d_err_i;
input d_rty_i;
@@ -5543,8 +4871,7 @@ input d_rty_i;
-
-
+
output dcache_refill_request;
wire dcache_refill_request;
output dcache_restart_request;
@@ -5553,10 +4880,9 @@ output dcache_stall_request;
wire dcache_stall_request;
output dcache_refilling;
wire dcache_refilling;
-
-
+
@@ -5566,62 +4892,59 @@ wire dcache_refilling;
-
-output [ (32-1):0] load_data_w;
-reg [ (32-1):0] load_data_w;
+output [(32-1):0] load_data_w;
+reg [(32-1):0] load_data_w;
output stall_wb_load;
reg stall_wb_load;
-output [ (32-1):0] d_dat_o;
-reg [ (32-1):0] d_dat_o;
-output [ (32-1):0] d_adr_o;
-reg [ (32-1):0] d_adr_o;
+output [(32-1):0] d_dat_o;
+reg [(32-1):0] d_dat_o;
+output [(32-1):0] d_adr_o;
+reg [(32-1):0] d_adr_o;
output d_cyc_o;
reg d_cyc_o;
-output [ (4-1):0] d_sel_o;
-reg [ (4-1):0] d_sel_o;
+output [(4-1):0] d_sel_o;
+reg [(4-1):0] d_sel_o;
output d_stb_o;
reg d_stb_o;
output d_we_o;
reg d_we_o;
-output [ (3-1):0] d_cti_o;
-reg [ (3-1):0] d_cti_o;
+output [(3-1):0] d_cti_o;
+reg [(3-1):0] d_cti_o;
output d_lock_o;
reg d_lock_o;
-output [ (2-1):0] d_bte_o;
-wire [ (2-1):0] d_bte_o;
+output [(2-1):0] d_bte_o;
+wire [(2-1):0] d_bte_o;
-reg [ 1:0] size_m;
-reg [ 1:0] size_w;
+reg [1:0] size_m;
+reg [1:0] size_w;
reg sign_extend_m;
reg sign_extend_w;
-reg [ (32-1):0] store_data_x;
-reg [ (32-1):0] store_data_m;
-reg [ (4-1):0] byte_enable_x;
-reg [ (4-1):0] byte_enable_m;
-wire [ (32-1):0] data_m;
-reg [ (32-1):0] data_w;
-
-
+reg [(32-1):0] store_data_x;
+reg [(32-1):0] store_data_m;
+reg [(4-1):0] byte_enable_x;
+reg [(4-1):0] byte_enable_m;
+wire [(32-1):0] data_m;
+reg [(32-1):0] data_w;
+
wire dcache_select_x;
reg dcache_select_m;
-wire [ (32-1):0] dcache_data_m;
-wire [ (32-1):0] dcache_refill_address;
+wire [(32-1):0] dcache_data_m;
+wire [(32-1):0] dcache_refill_address;
reg dcache_refill_ready;
-wire [ (3-1):0] first_cycle_type;
-wire [ (3-1):0] next_cycle_type;
+wire [(3-1):0] first_cycle_type;
+wire [(3-1):0] next_cycle_type;
wire last_word;
-wire [ (32-1):0] first_address;
-
+wire [(32-1):0] first_address;
-
+
@@ -5630,24 +4953,20 @@ wire [ (32-1):0] first_address;
-
wire wb_select_x;
-
+
-
reg wb_select_m;
-reg [ (32-1):0] wb_data_m;
+reg [(32-1):0] wb_data_m;
reg wb_load_complete;
-
-
-
+
@@ -5702,8 +5021,7 @@ endfunction
-
-
+
@@ -5787,9 +5105,7 @@ endfunction
-
-
-
+
lm32_dcache_full #(
.associativity (associativity),
@@ -5821,7 +5137,6 @@ lm32_dcache_full #(
.refilling (dcache_refilling),
.load_data (dcache_data_m)
);
-
@@ -5829,58 +5144,48 @@ lm32_dcache_full #(
-
+
-
-
+
-
-
-
- assign dcache_select_x = (load_store_address_x >= 32'h0)
- && (load_store_address_x <= 32'h7fffffff)
-
+
+ assign dcache_select_x = (load_store_address_x >= 32'h0)
+ && (load_store_address_x <= 32'h7fffffff)
+
-
-
+
-
;
-
- assign wb_select_x = 1'b1
-
-
- && !dcache_select_x
+ assign wb_select_x = 1'b1
+ && !dcache_select_x
-
+
-
-
+
-
;
always @(*)
begin
case (size_x)
- 2'b00: store_data_x = {4{store_operand_x[7:0]}};
- 2'b11: store_data_x = {2{store_operand_x[15:0]}};
- 2'b10: store_data_x = store_operand_x;
- default: store_data_x = { 32{1'bx}};
+ 2'b00: store_data_x = {4{store_operand_x[7:0]}};
+ 2'b11: store_data_x = {2{store_operand_x[15:0]}};
+ 2'b10: store_data_x = store_operand_x;
+ default: store_data_x = {32{1'bx}};
endcase
end
@@ -5888,18 +5193,18 @@ end
always @(*)
begin
casez ({size_x, load_store_address_x[1:0]})
- { 2'b00, 2'b11}: byte_enable_x = 4'b0001;
- { 2'b00, 2'b10}: byte_enable_x = 4'b0010;
- { 2'b00, 2'b01}: byte_enable_x = 4'b0100;
- { 2'b00, 2'b00}: byte_enable_x = 4'b1000;
- { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
- { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
- { 2'b10, 2'b??}: byte_enable_x = 4'b1111;
+ {2'b00, 2'b11}: byte_enable_x = 4'b0001;
+ {2'b00, 2'b10}: byte_enable_x = 4'b0010;
+ {2'b00, 2'b01}: byte_enable_x = 4'b0100;
+ {2'b00, 2'b00}: byte_enable_x = 4'b1000;
+ {2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+ {2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+ {2'b10, 2'b??}: byte_enable_x = 4'b1111;
default: byte_enable_x = 4'bxxxx;
endcase
end
-
+
@@ -5907,8 +5212,7 @@ end
-
-
+
@@ -5916,8 +5220,7 @@ end
-
-
+
@@ -5937,11 +5240,9 @@ end
-
+
-
-
@@ -5960,8 +5261,7 @@ end
-
-
+
@@ -5969,16 +5269,13 @@ end
-
- assign data_m = wb_select_m == 1'b1
+ assign data_m = wb_select_m == 1'b1
? wb_data_m
: dcache_data_m;
-
-
-
+
@@ -6005,55 +5302,52 @@ end
-
always @(*)
begin
casez ({size_w, load_store_address_w[1:0]})
- { 2'b00, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
- { 2'b00, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
- { 2'b00, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
- { 2'b00, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
- { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
- { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
- { 2'b10, 2'b??}: load_data_w = data_w;
- default: load_data_w = { 32{1'bx}};
+ {2'b00, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+ {2'b00, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+ {2'b00, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+ {2'b00, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+ {2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+ {2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+ {2'b10, 2'b??}: load_data_w = data_w;
+ default: load_data_w = {32{1'bx}};
endcase
end
-assign d_bte_o = 2'b00;
+assign d_bte_o = 2'b00;
-
-
+
generate
case (bytes_per_line)
4:
begin
-assign first_cycle_type = 3'b111;
-assign next_cycle_type = 3'b111;
-assign last_word = 1'b1;
-assign first_address = {dcache_refill_address[ 32-1:2], 2'b00};
+assign first_cycle_type = 3'b111;
+assign next_cycle_type = 3'b111;
+assign last_word = 1'b1;
+assign first_address = {dcache_refill_address[32-1:2], 2'b00};
end
8:
begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = 3'b111;
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = 3'b111;
assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
-assign first_address = {dcache_refill_address[ 32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
+assign first_address = {dcache_refill_address[32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
end
16:
begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
-assign first_address = {dcache_refill_address[ 32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
+assign first_address = {dcache_refill_address[32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
end
endcase
endgenerate
-
@@ -6061,63 +5355,55 @@ endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- d_cyc_o <= 1'b0;
- d_stb_o <= 1'b0;
- d_dat_o <= { 32{1'b0}};
- d_adr_o <= { 32{1'b0}};
- d_sel_o <= { 4{ 1'b0}};
- d_we_o <= 1'b0;
- d_cti_o <= 3'b111;
- d_lock_o <= 1'b0;
- wb_data_m <= { 32{1'b0}};
- wb_load_complete <= 1'b0;
- stall_wb_load <= 1'b0;
-
-
- dcache_refill_ready <= 1'b0;
-
+ d_cyc_o <= 1'b0;
+ d_stb_o <= 1'b0;
+ d_dat_o <= {32{1'b0}};
+ d_adr_o <= {32{1'b0}};
+ d_sel_o <= {4{1'b0}};
+ d_we_o <= 1'b0;
+ d_cti_o <= 3'b111;
+ d_lock_o <= 1'b0;
+ wb_data_m <= {32{1'b0}};
+ wb_load_complete <= 1'b0;
+ stall_wb_load <= 1'b0;
+
+ dcache_refill_ready <= 1'b0;
end
else
begin
-
- dcache_refill_ready <= 1'b0;
-
+ dcache_refill_ready <= 1'b0;
- if (d_cyc_o == 1'b1)
+ if (d_cyc_o == 1'b1)
begin
- if ((d_ack_i == 1'b1) || (d_err_i == 1'b1))
+ if ((d_ack_i == 1'b1) || (d_err_i == 1'b1))
begin
-
-
- if ((dcache_refilling == 1'b1) && (!last_word))
+
+ if ((dcache_refilling == 1'b1) && (!last_word))
begin
d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
end
else
-
begin
- d_cyc_o <= 1'b0;
- d_stb_o <= 1'b0;
- d_lock_o <= 1'b0;
+ d_cyc_o <= 1'b0;
+ d_stb_o <= 1'b0;
+ d_lock_o <= 1'b0;
end
-
-
+
d_cti_o <= next_cycle_type;
dcache_refill_ready <= dcache_refilling;
-
wb_data_m <= d_dat_i;
@@ -6125,137 +5411,125 @@ begin
wb_load_complete <= !d_we_o;
end
- if (d_err_i == 1'b1)
+ if (d_err_i == 1'b1)
$display ("Data bus error. Address: %x", d_adr_o);
end
else
begin
-
-
- if (dcache_refill_request == 1'b1)
+
+ if (dcache_refill_request == 1'b1)
begin
d_adr_o <= first_address;
- d_cyc_o <= 1'b1;
- d_sel_o <= { 32/8{ 1'b1}};
- d_stb_o <= 1'b1;
- d_we_o <= 1'b0;
+ d_cyc_o <= 1'b1;
+ d_sel_o <= {32/8{1'b1}};
+ d_stb_o <= 1'b1;
+ d_we_o <= 1'b0;
d_cti_o <= first_cycle_type;
end
else
-
- if ( (store_q_m == 1'b1)
- && (stall_m == 1'b0)
-
+ if ( (store_q_m == 1'b1)
+ && (stall_m == 1'b0)
+
-
-
+
-
)
begin
d_dat_o <= store_data_m;
d_adr_o <= load_store_address_m;
- d_cyc_o <= 1'b1;
+ d_cyc_o <= 1'b1;
d_sel_o <= byte_enable_m;
- d_stb_o <= 1'b1;
- d_we_o <= 1'b1;
- d_cti_o <= 3'b111;
+ d_stb_o <= 1'b1;
+ d_we_o <= 1'b1;
+ d_cti_o <= 3'b111;
end
- else if ( (load_q_m == 1'b1)
- && (wb_select_m == 1'b1)
- && (wb_load_complete == 1'b0)
+ else if ( (load_q_m == 1'b1)
+ && (wb_select_m == 1'b1)
+ && (wb_load_complete == 1'b0)
)
begin
- stall_wb_load <= 1'b0;
+ stall_wb_load <= 1'b0;
d_adr_o <= load_store_address_m;
- d_cyc_o <= 1'b1;
+ d_cyc_o <= 1'b1;
d_sel_o <= byte_enable_m;
- d_stb_o <= 1'b1;
- d_we_o <= 1'b0;
- d_cti_o <= 3'b111;
+ d_stb_o <= 1'b1;
+ d_we_o <= 1'b0;
+ d_cti_o <= 3'b111;
end
end
- if (stall_m == 1'b0)
- wb_load_complete <= 1'b0;
+ if (stall_m == 1'b0)
+ wb_load_complete <= 1'b0;
- if ((load_q_x == 1'b1) && (wb_select_x == 1'b1) && (stall_x == 1'b0))
- stall_wb_load <= 1'b1;
+ if ((load_q_x == 1'b1) && (wb_select_x == 1'b1) && (stall_x == 1'b0))
+ stall_wb_load <= 1'b1;
- if ((kill_m == 1'b1) || (exception_m == 1'b1))
- stall_wb_load <= 1'b0;
+ if ((kill_m == 1'b1) || (exception_m == 1'b1))
+ stall_wb_load <= 1'b0;
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- sign_extend_m <= 1'b0;
+ sign_extend_m <= 1'b0;
size_m <= 2'b00;
- byte_enable_m <= 1'b0;
- store_data_m <= { 32{1'b0}};
-
-
- dcache_select_m <= 1'b0;
+ byte_enable_m <= 1'b0;
+ store_data_m <= {32{1'b0}};
+ dcache_select_m <= 1'b0;
-
+
-
-
+
-
- wb_select_m <= 1'b0;
+ wb_select_m <= 1'b0;
end
else
begin
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
sign_extend_m <= sign_extend_x;
size_m <= size_x;
byte_enable_m <= byte_enable_x;
store_data_m <= store_data_x;
-
-
- dcache_select_m <= dcache_select_x;
+ dcache_select_m <= dcache_select_x;
-
+
-
-
+
-
wb_select_m <= wb_select_x;
end
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
size_w <= 2'b00;
- data_w <= { 32{1'b0}};
- sign_extend_w <= 1'b0;
+ data_w <= {32{1'b0}};
+ sign_extend_w <= 1'b0;
end
else
begin
@@ -6274,11 +5548,11 @@ end
always @(posedge clk_i)
begin
- if (((load_q_m == 1'b1) || (store_q_m == 1'b1)) && (stall_m == 1'b0))
+ if (((load_q_m == 1'b1) || (store_q_m == 1'b1)) && (stall_m == 1'b0))
begin
- if ((size_m === 2'b11) && (load_store_address_m[0] !== 1'b0))
+ if ((size_m === 2'b11) && (load_store_address_m[0] !== 1'b0))
$display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
- if ((size_m === 2'b10) && (load_store_address_m[1:0] !== 2'b00))
+ if ((size_m === 2'b10) && (load_store_address_m[1:0] !== 2'b00))
$display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
end
end
@@ -6320,10 +5594,7 @@ endmodule
-
-
-
-
+
@@ -6353,9 +5624,9 @@ endmodule
-
+
@@ -6640,104 +5911,55 @@ endmodule
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -6750,37 +5972,27 @@ module lm32_decoder_full (
d_result_sel_0,
d_result_sel_1,
x_result_sel_csr,
-
-
- x_result_sel_mc_arith,
+ x_result_sel_mc_arith,
-
+
-
-
-
- x_result_sel_sext,
+ x_result_sel_sext,
x_result_sel_logic,
-
+
-
x_result_sel_add,
m_result_sel_compare,
-
-
- m_result_sel_shift,
+ m_result_sel_shift,
w_result_sel_load,
-
-
- w_result_sel_mul,
+ w_result_sel_mul,
x_bypass_enable,
m_bypass_enable,
@@ -6798,45 +6010,36 @@ module lm32_decoder_full (
sign_extend,
adder_op,
logic_op,
-
-
- direction,
+ direction,
-
+
-
-
+
-
-
-
+
divide,
modulus,
-
branch,
branch_reg,
condition,
bi_conditional,
bi_unconditional,
-
+
-
scall,
eret,
-
+
-
-
+
-
csr_write_enable
);
@@ -6844,59 +6047,49 @@ module lm32_decoder_full (
-input [ (32-1):0] instruction;
+input [(32-1):0] instruction;
-output [ 0:0] d_result_sel_0;
-reg [ 0:0] d_result_sel_0;
-output [ 1:0] d_result_sel_1;
-reg [ 1:0] d_result_sel_1;
+output [0:0] d_result_sel_0;
+reg [0:0] d_result_sel_0;
+output [1:0] d_result_sel_1;
+reg [1:0] d_result_sel_1;
output x_result_sel_csr;
reg x_result_sel_csr;
-
-
+
output x_result_sel_mc_arith;
reg x_result_sel_mc_arith;
-
-
+
-
-
-
+
output x_result_sel_sext;
reg x_result_sel_sext;
-
output x_result_sel_logic;
reg x_result_sel_logic;
-
+
-
output x_result_sel_add;
reg x_result_sel_add;
output m_result_sel_compare;
reg m_result_sel_compare;
-
-
+
output m_result_sel_shift;
reg m_result_sel_shift;
-
output w_result_sel_load;
reg w_result_sel_load;
-
-
+
output w_result_sel_mul;
reg w_result_sel_mul;
-
output x_bypass_enable;
wire x_bypass_enable;
@@ -6904,87 +6097,78 @@ output m_bypass_enable;
wire m_bypass_enable;
output read_enable_0;
wire read_enable_0;
-output [ (5-1):0] read_idx_0;
-wire [ (5-1):0] read_idx_0;
+output [(5-1):0] read_idx_0;
+wire [(5-1):0] read_idx_0;
output read_enable_1;
wire read_enable_1;
-output [ (5-1):0] read_idx_1;
-wire [ (5-1):0] read_idx_1;
+output [(5-1):0] read_idx_1;
+wire [(5-1):0] read_idx_1;
output write_enable;
wire write_enable;
-output [ (5-1):0] write_idx;
-wire [ (5-1):0] write_idx;
-output [ (32-1):0] immediate;
-wire [ (32-1):0] immediate;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output [(5-1):0] write_idx;
+wire [(5-1):0] write_idx;
+output [(32-1):0] immediate;
+wire [(32-1):0] immediate;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
output load;
wire load;
output store;
wire store;
-output [ 1:0] size;
-wire [ 1:0] size;
+output [1:0] size;
+wire [1:0] size;
output sign_extend;
wire sign_extend;
output adder_op;
wire adder_op;
-output [ 3:0] logic_op;
-wire [ 3:0] logic_op;
-
-
+output [3:0] logic_op;
+wire [3:0] logic_op;
+
output direction;
wire direction;
-
-
+
-
-
+
-
-
-
+
output divide;
wire divide;
output modulus;
wire modulus;
-
output branch;
wire branch;
output branch_reg;
wire branch_reg;
-output [ (3-1):0] condition;
-wire [ (3-1):0] condition;
+output [(3-1):0] condition;
+wire [(3-1):0] condition;
output bi_conditional;
wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
-
+
-
output scall;
wire scall;
output eret;
wire eret;
-
+
-
-
+
-
output csr_write_enable;
wire csr_write_enable;
@@ -6992,10 +6176,10 @@ wire csr_write_enable;
-wire [ (32-1):0] extended_immediate;
-wire [ (32-1):0] high_immediate;
-wire [ (32-1):0] call_immediate;
-wire [ (32-1):0] branch_immediate;
+wire [(32-1):0] extended_immediate;
+wire [(32-1):0] high_immediate;
+wire [(32-1):0] call_immediate;
+wire [(32-1):0] branch_immediate;
wire sign_extend_immediate;
wire select_high_immediate;
wire select_call_immediate;
@@ -7004,9 +6188,7 @@ wire select_call_immediate;
-
-
-
+
@@ -7062,72 +6244,61 @@ endfunction
-
-assign op_add = instruction[ 30:26] == 5'b01101;
-assign op_and = instruction[ 30:26] == 5'b01000;
-assign op_andhi = instruction[ 31:26] == 6'b011000;
-assign op_b = instruction[ 31:26] == 6'b110000;
-assign op_bi = instruction[ 31:26] == 6'b111000;
-assign op_be = instruction[ 31:26] == 6'b010001;
-assign op_bg = instruction[ 31:26] == 6'b010010;
-assign op_bge = instruction[ 31:26] == 6'b010011;
-assign op_bgeu = instruction[ 31:26] == 6'b010100;
-assign op_bgu = instruction[ 31:26] == 6'b010101;
-assign op_bne = instruction[ 31:26] == 6'b010111;
-assign op_call = instruction[ 31:26] == 6'b110110;
-assign op_calli = instruction[ 31:26] == 6'b111110;
-assign op_cmpe = instruction[ 30:26] == 5'b11001;
-assign op_cmpg = instruction[ 30:26] == 5'b11010;
-assign op_cmpge = instruction[ 30:26] == 5'b11011;
-assign op_cmpgeu = instruction[ 30:26] == 5'b11100;
-assign op_cmpgu = instruction[ 30:26] == 5'b11101;
-assign op_cmpne = instruction[ 30:26] == 5'b11111;
-
-
-assign op_divu = instruction[ 31:26] == 6'b100011;
+assign op_add = instruction[30:26] == 5'b01101;
+assign op_and = instruction[30:26] == 5'b01000;
+assign op_andhi = instruction[31:26] == 6'b011000;
+assign op_b = instruction[31:26] == 6'b110000;
+assign op_bi = instruction[31:26] == 6'b111000;
+assign op_be = instruction[31:26] == 6'b010001;
+assign op_bg = instruction[31:26] == 6'b010010;
+assign op_bge = instruction[31:26] == 6'b010011;
+assign op_bgeu = instruction[31:26] == 6'b010100;
+assign op_bgu = instruction[31:26] == 6'b010101;
+assign op_bne = instruction[31:26] == 6'b010111;
+assign op_call = instruction[31:26] == 6'b110110;
+assign op_calli = instruction[31:26] == 6'b111110;
+assign op_cmpe = instruction[30:26] == 5'b11001;
+assign op_cmpg = instruction[30:26] == 5'b11010;
+assign op_cmpge = instruction[30:26] == 5'b11011;
+assign op_cmpgeu = instruction[30:26] == 5'b11100;
+assign op_cmpgu = instruction[30:26] == 5'b11101;
+assign op_cmpne = instruction[30:26] == 5'b11111;
+assign op_divu = instruction[31:26] == 6'b100011;
-assign op_lb = instruction[ 31:26] == 6'b000100;
-assign op_lbu = instruction[ 31:26] == 6'b010000;
-assign op_lh = instruction[ 31:26] == 6'b000111;
-assign op_lhu = instruction[ 31:26] == 6'b001011;
-assign op_lw = instruction[ 31:26] == 6'b001010;
-
-
-assign op_modu = instruction[ 31:26] == 6'b110001;
+assign op_lb = instruction[31:26] == 6'b000100;
+assign op_lbu = instruction[31:26] == 6'b010000;
+assign op_lh = instruction[31:26] == 6'b000111;
+assign op_lhu = instruction[31:26] == 6'b001011;
+assign op_lw = instruction[31:26] == 6'b001010;
+assign op_modu = instruction[31:26] == 6'b110001;
-
-
-assign op_mul = instruction[ 30:26] == 5'b00010;
+assign op_mul = instruction[30:26] == 5'b00010;
-assign op_nor = instruction[ 30:26] == 5'b00001;
-assign op_or = instruction[ 30:26] == 5'b01110;
-assign op_orhi = instruction[ 31:26] == 6'b011110;
-assign op_raise = instruction[ 31:26] == 6'b101011;
-assign op_rcsr = instruction[ 31:26] == 6'b100100;
-assign op_sb = instruction[ 31:26] == 6'b001100;
-
-
-assign op_sextb = instruction[ 31:26] == 6'b101100;
-assign op_sexth = instruction[ 31:26] == 6'b110111;
+assign op_nor = instruction[30:26] == 5'b00001;
+assign op_or = instruction[30:26] == 5'b01110;
+assign op_orhi = instruction[31:26] == 6'b011110;
+assign op_raise = instruction[31:26] == 6'b101011;
+assign op_rcsr = instruction[31:26] == 6'b100100;
+assign op_sb = instruction[31:26] == 6'b001100;
+assign op_sextb = instruction[31:26] == 6'b101100;
+assign op_sexth = instruction[31:26] == 6'b110111;
-assign op_sh = instruction[ 31:26] == 6'b000011;
-
-
-assign op_sl = instruction[ 30:26] == 5'b01111;
+assign op_sh = instruction[31:26] == 6'b000011;
+assign op_sl = instruction[30:26] == 5'b01111;
-assign op_sr = instruction[ 30:26] == 5'b00101;
-assign op_sru = instruction[ 30:26] == 5'b00000;
-assign op_sub = instruction[ 31:26] == 6'b110010;
-assign op_sw = instruction[ 31:26] == 6'b010110;
-assign op_user = instruction[ 31:26] == 6'b110011;
-assign op_wcsr = instruction[ 31:26] == 6'b110100;
-assign op_xnor = instruction[ 30:26] == 5'b01001;
-assign op_xor = instruction[ 30:26] == 5'b00110;
+assign op_sr = instruction[30:26] == 5'b00101;
+assign op_sru = instruction[30:26] == 5'b00000;
+assign op_sub = instruction[31:26] == 6'b110010;
+assign op_sw = instruction[31:26] == 6'b010110;
+assign op_user = instruction[31:26] == 6'b110011;
+assign op_wcsr = instruction[31:26] == 6'b110100;
+assign op_xnor = instruction[30:26] == 5'b01001;
+assign op_xor = instruction[30:26] == 5'b00110;
assign arith = op_add | op_sub;
@@ -7137,35 +6308,25 @@ assign bi_conditional = op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne;
assign bi_unconditional = op_bi;
assign bra = op_b | bi_unconditional | bi_conditional;
assign call = op_call | op_calli;
-
-
-assign shift = op_sl | op_sr | op_sru;
+assign shift = op_sl | op_sr | op_sru;
-
+
-
-
+
-
-
-
-assign sext = op_sextb | op_sexth;
+assign sext = op_sextb | op_sexth;
-
-
-assign multiply = op_mul;
+assign multiply = op_mul;
-
-
+
assign divide = op_divu;
assign modulus = op_modu;
-
assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
assign store = op_sb | op_sh | op_sw;
@@ -7175,137 +6336,107 @@ always @(*)
begin
if (call)
- d_result_sel_0 = 1'b1;
+ d_result_sel_0 = 1'b1;
else
- d_result_sel_0 = 1'b0;
+ d_result_sel_0 = 1'b0;
if (call)
- d_result_sel_1 = 2'b00;
+ d_result_sel_1 = 2'b00;
else if ((instruction[31] == 1'b0) && !bra)
- d_result_sel_1 = 2'b10;
+ d_result_sel_1 = 2'b10;
else
- d_result_sel_1 = 2'b01;
+ d_result_sel_1 = 2'b01;
- x_result_sel_csr = 1'b0;
-
-
- x_result_sel_mc_arith = 1'b0;
+ x_result_sel_csr = 1'b0;
+ x_result_sel_mc_arith = 1'b0;
-
+
-
-
-
- x_result_sel_sext = 1'b0;
+ x_result_sel_sext = 1'b0;
- x_result_sel_logic = 1'b0;
-
+ x_result_sel_logic = 1'b0;
+
-
- x_result_sel_add = 1'b0;
+ x_result_sel_add = 1'b0;
if (op_rcsr)
- x_result_sel_csr = 1'b1;
-
-
-
+ x_result_sel_csr = 1'b1;
+
+
-
-
-
- else if (divide | modulus)
- x_result_sel_mc_arith = 1'b1;
+ else if (divide | modulus)
+ x_result_sel_mc_arith = 1'b1;
-
+
-
-
-
-
-
- else if (sext)
- x_result_sel_sext = 1'b1;
+ else if (sext)
+ x_result_sel_sext = 1'b1;
else if (logical)
- x_result_sel_logic = 1'b1;
-
+ x_result_sel_logic = 1'b1;
+
-
else
- x_result_sel_add = 1'b1;
+ x_result_sel_add = 1'b1;
m_result_sel_compare = cmp;
-
-
- m_result_sel_shift = shift;
+ m_result_sel_shift = shift;
w_result_sel_load = load;
-
-
- w_result_sel_mul = op_mul;
+ w_result_sel_mul = op_mul;
end
assign x_bypass_enable = arith
| logical
-
+
-
-
+
-
-
-
+
| divide
| modulus
-
-
+
-
-
-
- | sext
+ | sext
-
+
-
| op_rcsr
;
assign m_bypass_enable = x_bypass_enable
-
-
- | shift
+ | shift
| cmp
;
@@ -7331,32 +6462,27 @@ assign sign_extend = instruction[28];
assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
assign logic_op = instruction[29:26];
-
-
+
assign direction = instruction[29];
-
assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
-
+
-
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
-
+
-
-
+
-
assign csr_write_enable = op_wcsr;
@@ -7370,11 +6496,11 @@ assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, inst
assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
-assign immediate = select_high_immediate == 1'b1
+assign immediate = select_high_immediate == 1'b1
? high_immediate
: extended_immediate;
-assign branch_offset = select_call_immediate == 1'b1
+assign branch_offset = select_call_immediate == 1'b1
? call_immediate
: branch_immediate;
@@ -7415,10 +6541,7 @@ endmodule
-
-
-
-
+
@@ -7448,9 +6571,9 @@ endmodule
-
+
@@ -7734,48 +6857,28 @@ endmodule
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
-
+
+
+
+
+
+
+
+
+
@@ -7793,10 +6896,9 @@ module lm32_icache_full (
refill_ready,
refill_data,
iflush,
-
+
-
valid_d,
branch_predict_taken_d,
@@ -7825,7 +6927,7 @@ localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
localparam addr_set_lsb = (addr_offset_msb+1);
localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
localparam addr_tag_lsb = (addr_set_msb+1);
-localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_msb = clogb2(32'h7fffffff-32'h0)-1;
localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
@@ -7841,18 +6943,17 @@ input stall_f;
input valid_d;
input branch_predict_taken_d;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;
input read_enable_f;
input refill_ready;
-input [ (32-1):0] refill_data;
+input [(32-1):0] refill_data;
input iflush;
-
+
-
@@ -7864,12 +6965,12 @@ output restart_request;
reg restart_request;
output refill_request;
wire refill_request;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
output refilling;
reg refilling;
-output [ (32-1):0] inst;
-wire [ (32-1):0] inst;
+output [(32-1):0] inst;
+wire [(32-1):0] inst;
@@ -7877,27 +6978,27 @@ wire [ (32-1):0] inst;
wire enable;
wire [0:associativity-1] way_mem_we;
-wire [ (32-1):0] way_data[0:associativity-1];
-wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [(32-1):0] way_data[0:associativity-1];
+wire [((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
wire [0:associativity-1] way_valid;
wire [0:associativity-1] way_match;
wire miss;
-wire [ (addr_set_width-1):0] tmem_read_address;
-wire [ (addr_set_width-1):0] tmem_write_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
-wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+wire [(addr_set_width-1):0] tmem_read_address;
+wire [(addr_set_width-1):0] tmem_write_address;
+wire [((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [((addr_tag_width+1)-1):0] tmem_write_data;
-reg [ 3:0] state;
+reg [3:0] state;
wire flushing;
wire check;
wire refill;
reg [associativity-1:0] refill_way_select;
-reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+reg [addr_offset_msb:addr_offset_lsb] refill_offset;
wire last_refill;
-reg [ (addr_set_width-1):0] flush_set;
+reg [(addr_set_width-1):0] flush_set;
genvar i;
@@ -7905,9 +7006,7 @@ genvar i;
-
-
-
+
@@ -7962,7 +7061,6 @@ endfunction
-
generate
for (i = 0; i < associativity; i = i + 1)
begin : memories
@@ -7971,7 +7069,7 @@ endfunction
#(
.data_width (32),
- .address_width ( (addr_offset_width+addr_set_width))
+ .address_width ((addr_offset_width+addr_set_width))
)
way_0_data_ram
@@ -7983,7 +7081,7 @@ endfunction
.read_address (dmem_read_address),
.enable_read (enable),
.write_address (dmem_write_address),
- .enable_write ( 1'b1),
+ .enable_write (1'b1),
.write_enable (way_mem_we[i]),
.write_data (refill_data),
@@ -7993,8 +7091,8 @@ endfunction
lm32_ram
#(
- .data_width ( (addr_tag_width+1)),
- .address_width ( addr_set_width)
+ .data_width ((addr_tag_width+1)),
+ .address_width (addr_set_width)
)
way_0_tag_ram
@@ -8006,7 +7104,7 @@ endfunction
.read_address (tmem_read_address),
.enable_read (enable),
.write_address (tmem_write_address),
- .enable_write ( 1'b1),
+ .enable_write (1'b1),
.write_enable (way_mem_we[i] | flushing),
.write_data (tmem_write_data),
@@ -8024,7 +7122,7 @@ endgenerate
generate
for (i = 0; i < associativity; i = i + 1)
begin : match
-assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb], 1'b1});
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[addr_tag_msb:addr_tag_lsb], 1'b1});
end
endgenerate
@@ -8043,55 +7141,55 @@ endgenerate
generate
if (bytes_per_line > 4)
-assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+assign dmem_write_address = {refill_address[addr_set_msb:addr_set_lsb], refill_offset};
else
-assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+assign dmem_write_address = refill_address[addr_set_msb:addr_set_lsb];
endgenerate
-assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+assign dmem_read_address = address_a[addr_set_msb:addr_offset_lsb];
-assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_read_address = address_a[addr_set_msb:addr_set_lsb];
assign tmem_write_address = flushing
? flush_set
- : refill_address[ addr_set_msb:addr_set_lsb];
+ : refill_address[addr_set_msb:addr_set_lsb];
generate
if (bytes_per_line > 4)
assign last_refill = refill_offset == {addr_offset_width{1'b1}};
else
-assign last_refill = 1'b1;
+assign last_refill = 1'b1;
endgenerate
-assign enable = (stall_a == 1'b0);
+assign enable = (stall_a == 1'b0);
generate
if (associativity == 1)
begin : we_1
-assign way_mem_we[0] = (refill_ready == 1'b1);
+assign way_mem_we[0] = (refill_ready == 1'b1);
end
else
begin : we_2
-assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1);
-assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1);
+assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1);
+assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1);
end
endgenerate
-assign tmem_write_data[ 0] = last_refill & !flushing;
-assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+assign tmem_write_data[0] = last_refill & !flushing;
+assign tmem_write_data[((addr_tag_width+1)-1):1] = refill_address[addr_tag_msb:addr_tag_lsb];
assign flushing = |state[1:0];
assign check = state[2];
assign refill = state[3];
-assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d);
-assign stall_request = (check == 1'b0);
-assign refill_request = (refill == 1'b1);
+assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check == 1'b0);
+assign refill_request = (refill == 1'b1);
@@ -8101,13 +7199,13 @@ assign refill_request = (refill == 1'b1);
generate
if (associativity >= 2)
begin : way_select
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
else
begin
- if (miss == 1'b1)
+ if (miss == 1'b1)
refill_way_select <= {refill_way_select[0], refill_way_select[1]};
end
end
@@ -8115,77 +7213,76 @@ end
endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- refilling <= 1'b0;
+ if (rst_i == 1'b1)
+ refilling <= 1'b0;
else
refilling <= refill;
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- state <= 4'b0001;
- flush_set <= { addr_set_width{1'b1}};
- refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
- restart_request <= 1'b0;
+ state <= 4'b0001;
+ flush_set <= {addr_set_width{1'b1}};
+ refill_address <= {(clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+ restart_request <= 1'b0;
end
else
begin
case (state)
- 4'b0001:
+ 4'b0001:
begin
- if (flush_set == { addr_set_width{1'b0}})
- state <= 4'b0100;
+ if (flush_set == {addr_set_width{1'b0}})
+ state <= 4'b0100;
flush_set <= flush_set - 1'b1;
end
- 4'b0010:
+ 4'b0010:
begin
- if (flush_set == { addr_set_width{1'b0}})
-
+ if (flush_set == {addr_set_width{1'b0}})
+
-
- state <= 4'b0100;
+ state <= 4'b0100;
flush_set <= flush_set - 1'b1;
end
- 4'b0100:
+ 4'b0100:
begin
- if (stall_a == 1'b0)
- restart_request <= 1'b0;
- if (iflush == 1'b1)
+ if (stall_a == 1'b0)
+ restart_request <= 1'b0;
+ if (iflush == 1'b1)
begin
refill_address <= address_f;
- state <= 4'b0010;
+ state <= 4'b0010;
end
- else if (miss == 1'b1)
+ else if (miss == 1'b1)
begin
refill_address <= address_f;
- state <= 4'b1000;
+ state <= 4'b1000;
end
end
- 4'b1000:
+ 4'b1000:
begin
- if (refill_ready == 1'b1)
+ if (refill_ready == 1'b1)
begin
- if (last_refill == 1'b1)
+ if (last_refill == 1'b1)
begin
- restart_request <= 1'b1;
- state <= 4'b0100;
+ restart_request <= 1'b1;
+ state <= 4'b0100;
end
end
end
@@ -8198,27 +7295,27 @@ generate
if (bytes_per_line > 4)
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
else
begin
case (state)
- 4'b0100:
+ 4'b0100:
begin
- if (iflush == 1'b1)
+ if (iflush == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
- else if (miss == 1'b1)
+ else if (miss == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
end
- 4'b1000:
+ 4'b1000:
begin
- if (refill_ready == 1'b1)
+ if (refill_ready == 1'b1)
refill_offset <= refill_offset + 1'b1;
end
@@ -8230,7 +7327,6 @@ endgenerate
endmodule
-
@@ -8263,10 +7359,7 @@ endmodule
-
-
-
-
+
@@ -8296,9 +7389,9 @@ endmodule
-
+
@@ -8582,46 +7675,27 @@ endmodule
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
-
+
+
+
+
+
+
+
+
@@ -8669,7 +7743,7 @@ localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
localparam addr_set_lsb = (addr_offset_msb+1);
localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
localparam addr_tag_lsb = (addr_set_msb+1);
-localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_msb = clogb2(32'h7fffffff-32'h0)-1;
localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
@@ -8683,15 +7757,15 @@ input stall_a;
input stall_x;
input stall_m;
-input [ (32-1):0] address_x;
-input [ (32-1):0] address_m;
+input [(32-1):0] address_x;
+input [(32-1):0] address_m;
input load_q_m;
input store_q_m;
-input [ (32-1):0] store_data;
-input [ (4-1):0] store_byte_select;
+input [(32-1):0] store_data;
+input [(4-1):0] store_byte_select;
input refill_ready;
-input [ (32-1):0] refill_data;
+input [(32-1):0] refill_data;
input dflush;
@@ -8705,12 +7779,12 @@ output restart_request;
reg restart_request;
output refill_request;
reg refill_request;
-output [ (32-1):0] refill_address;
-reg [ (32-1):0] refill_address;
+output [(32-1):0] refill_address;
+reg [(32-1):0] refill_address;
output refilling;
reg refilling;
-output [ (32-1):0] load_data;
-wire [ (32-1):0] load_data;
+output [(32-1):0] load_data;
+wire [(32-1):0] load_data;
@@ -8720,29 +7794,29 @@ wire read_port_enable;
wire write_port_enable;
wire [0:associativity-1] way_tmem_we;
wire [0:associativity-1] way_dmem_we;
-wire [ (32-1):0] way_data[0:associativity-1];
-wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [(32-1):0] way_data[0:associativity-1];
+wire [((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
wire [0:associativity-1] way_valid;
wire [0:associativity-1] way_match;
wire miss;
-wire [ (addr_set_width-1):0] tmem_read_address;
-wire [ (addr_set_width-1):0] tmem_write_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
-wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
-reg [ (32-1):0] dmem_write_data;
+wire [(addr_set_width-1):0] tmem_read_address;
+wire [(addr_set_width-1):0] tmem_write_address;
+wire [((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [((addr_tag_width+1)-1):0] tmem_write_data;
+reg [(32-1):0] dmem_write_data;
-reg [ 2:0] state;
+reg [2:0] state;
wire flushing;
wire check;
wire refill;
wire valid_store;
reg [associativity-1:0] refill_way_select;
-reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+reg [addr_offset_msb:addr_offset_lsb] refill_offset;
wire last_refill;
-reg [ (addr_set_width-1):0] flush_set;
+reg [(addr_set_width-1):0] flush_set;
genvar i, j;
@@ -8750,9 +7824,7 @@ genvar i, j;
-
-
-
+
@@ -8807,18 +7879,17 @@ endfunction
-
generate
for (i = 0; i < associativity; i = i + 1)
begin : memories
- if ( (addr_offset_width+addr_set_width) < 11)
+ if ((addr_offset_width+addr_set_width) < 11)
begin : data_memories
lm32_ram
#(
.data_width (32),
- .address_width ( (addr_offset_width+addr_set_width))
+ .address_width ((addr_offset_width+addr_set_width))
) way_0_data_ram
(
@@ -8844,7 +7915,7 @@ endfunction
#(
.data_width (8),
- .address_width ( (addr_offset_width+addr_set_width))
+ .address_width ((addr_offset_width+addr_set_width))
) way_0_data_ram
(
@@ -8868,8 +7939,8 @@ endfunction
lm32_ram
#(
- .data_width ( (addr_tag_width+1)),
- .address_width ( addr_set_width)
+ .data_width ((addr_tag_width+1)),
+ .address_width (addr_set_width)
) way_0_tag_ram
(
@@ -8880,7 +7951,7 @@ endfunction
.read_address (tmem_read_address),
.enable_read (read_port_enable),
.write_address (tmem_write_address),
- .enable_write ( 1'b1),
+ .enable_write (1'b1),
.write_enable (way_tmem_we[i]),
.write_data (tmem_write_data),
@@ -8898,7 +7969,7 @@ endfunction
generate
for (i = 0; i < associativity; i = i + 1)
begin : match
-assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[ addr_tag_msb:addr_tag_lsb], 1'b1});
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[addr_tag_msb:addr_tag_lsb], 1'b1});
end
endgenerate
@@ -8915,19 +7986,19 @@ assign load_data = way_match[0] ? way_data[0] : way_data[1];
endgenerate
generate
- if ( (addr_offset_width+addr_set_width) < 11)
+ if ((addr_offset_width+addr_set_width) < 11)
begin
always @(*)
begin
- if (refill == 1'b1)
+ if (refill == 1'b1)
dmem_write_data = refill_data;
else
begin
- dmem_write_data[ 7:0] = store_byte_select[0] ? store_data[ 7:0] : load_data[ 7:0];
- dmem_write_data[ 15:8] = store_byte_select[1] ? store_data[ 15:8] : load_data[ 15:8];
- dmem_write_data[ 23:16] = store_byte_select[2] ? store_data[ 23:16] : load_data[ 23:16];
- dmem_write_data[ 31:24] = store_byte_select[3] ? store_data[ 31:24] : load_data[ 31:24];
+ dmem_write_data[7:0] = store_byte_select[0] ? store_data[7:0] : load_data[7:0];
+ dmem_write_data[15:8] = store_byte_select[1] ? store_data[15:8] : load_data[15:8];
+ dmem_write_data[23:16] = store_byte_select[2] ? store_data[23:16] : load_data[23:16];
+ dmem_write_data[31:24] = store_byte_select[3] ? store_data[31:24] : load_data[31:24];
end
end
end
@@ -8936,7 +8007,7 @@ end
always @(*)
begin
- if (refill == 1'b1)
+ if (refill == 1'b1)
dmem_write_data = refill_data;
else
dmem_write_data = store_data;
@@ -8947,63 +8018,63 @@ endgenerate
generate
if (bytes_per_line > 4)
-assign dmem_write_address = (refill == 1'b1)
- ? {refill_address[ addr_set_msb:addr_set_lsb], refill_offset}
- : address_m[ addr_set_msb:addr_offset_lsb];
+assign dmem_write_address = (refill == 1'b1)
+ ? {refill_address[addr_set_msb:addr_set_lsb], refill_offset}
+ : address_m[addr_set_msb:addr_offset_lsb];
else
-assign dmem_write_address = (refill == 1'b1)
- ? refill_address[ addr_set_msb:addr_set_lsb]
- : address_m[ addr_set_msb:addr_offset_lsb];
+assign dmem_write_address = (refill == 1'b1)
+ ? refill_address[addr_set_msb:addr_set_lsb]
+ : address_m[addr_set_msb:addr_offset_lsb];
endgenerate
-assign dmem_read_address = address_x[ addr_set_msb:addr_offset_lsb];
+assign dmem_read_address = address_x[addr_set_msb:addr_offset_lsb];
-assign tmem_write_address = (flushing == 1'b1)
+assign tmem_write_address = (flushing == 1'b1)
? flush_set
- : refill_address[ addr_set_msb:addr_set_lsb];
-assign tmem_read_address = address_x[ addr_set_msb:addr_set_lsb];
+ : refill_address[addr_set_msb:addr_set_lsb];
+assign tmem_read_address = address_x[addr_set_msb:addr_set_lsb];
generate
if (bytes_per_line > 4)
assign last_refill = refill_offset == {addr_offset_width{1'b1}};
else
-assign last_refill = 1'b1;
+assign last_refill = 1'b1;
endgenerate
-assign read_port_enable = (stall_x == 1'b0);
-assign write_port_enable = (refill_ready == 1'b1) || !stall_m;
+assign read_port_enable = (stall_x == 1'b0);
+assign write_port_enable = (refill_ready == 1'b1) || !stall_m;
-assign valid_store = (store_q_m == 1'b1) && (check == 1'b1);
+assign valid_store = (store_q_m == 1'b1) && (check == 1'b1);
generate
if (associativity == 1)
begin : we_1
-assign way_dmem_we[0] = (refill_ready == 1'b1) || ((valid_store == 1'b1) && (way_match[0] == 1'b1));
-assign way_tmem_we[0] = (refill_ready == 1'b1) || (flushing == 1'b1);
+assign way_dmem_we[0] = (refill_ready == 1'b1) || ((valid_store == 1'b1) && (way_match[0] == 1'b1));
+assign way_tmem_we[0] = (refill_ready == 1'b1) || (flushing == 1'b1);
end
else
begin : we_2
-assign way_dmem_we[0] = ((refill_ready == 1'b1) && (refill_way_select[0] == 1'b1)) || ((valid_store == 1'b1) && (way_match[0] == 1'b1));
-assign way_dmem_we[1] = ((refill_ready == 1'b1) && (refill_way_select[1] == 1'b1)) || ((valid_store == 1'b1) && (way_match[1] == 1'b1));
-assign way_tmem_we[0] = ((refill_ready == 1'b1) && (refill_way_select[0] == 1'b1)) || (flushing == 1'b1);
-assign way_tmem_we[1] = ((refill_ready == 1'b1) && (refill_way_select[1] == 1'b1)) || (flushing == 1'b1);
+assign way_dmem_we[0] = ((refill_ready == 1'b1) && (refill_way_select[0] == 1'b1)) || ((valid_store == 1'b1) && (way_match[0] == 1'b1));
+assign way_dmem_we[1] = ((refill_ready == 1'b1) && (refill_way_select[1] == 1'b1)) || ((valid_store == 1'b1) && (way_match[1] == 1'b1));
+assign way_tmem_we[0] = ((refill_ready == 1'b1) && (refill_way_select[0] == 1'b1)) || (flushing == 1'b1);
+assign way_tmem_we[1] = ((refill_ready == 1'b1) && (refill_way_select[1] == 1'b1)) || (flushing == 1'b1);
end
endgenerate
-assign tmem_write_data[ 0] = ((last_refill == 1'b1) || (valid_store == 1'b1)) && (flushing == 1'b0);
-assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+assign tmem_write_data[0] = ((last_refill == 1'b1) || (valid_store == 1'b1)) && (flushing == 1'b0);
+assign tmem_write_data[((addr_tag_width+1)-1):1] = refill_address[addr_tag_msb:addr_tag_lsb];
assign flushing = state[0];
assign check = state[1];
assign refill = state[2];
-assign miss = (~(|way_match)) && (load_q_m == 1'b1) && (stall_m == 1'b0);
-assign stall_request = (check == 1'b0);
+assign miss = (~(|way_match)) && (load_q_m == 1'b1) && (stall_m == 1'b0);
+assign stall_request = (check == 1'b0);
@@ -9013,13 +8084,13 @@ assign stall_request = (check == 1'b0);
generate
if (associativity >= 2)
begin : way_select
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
else
begin
- if (refill_request == 1'b1)
+ if (refill_request == 1'b1)
refill_way_select <= {refill_way_select[0], refill_way_select[1]};
end
end
@@ -9027,62 +8098,62 @@ end
endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- refilling <= 1'b0;
+ if (rst_i == 1'b1)
+ refilling <= 1'b0;
else
refilling <= refill;
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- state <= 3'b001;
- flush_set <= { addr_set_width{1'b1}};
- refill_request <= 1'b0;
- refill_address <= { 32{1'bx}};
- restart_request <= 1'b0;
+ state <= 3'b001;
+ flush_set <= {addr_set_width{1'b1}};
+ refill_request <= 1'b0;
+ refill_address <= {32{1'bx}};
+ restart_request <= 1'b0;
end
else
begin
case (state)
- 3'b001:
+ 3'b001:
begin
- if (flush_set == { addr_set_width{1'b0}})
- state <= 3'b010;
+ if (flush_set == {addr_set_width{1'b0}})
+ state <= 3'b010;
flush_set <= flush_set - 1'b1;
end
- 3'b010:
+ 3'b010:
begin
- if (stall_a == 1'b0)
- restart_request <= 1'b0;
- if (miss == 1'b1)
+ if (stall_a == 1'b0)
+ restart_request <= 1'b0;
+ if (miss == 1'b1)
begin
- refill_request <= 1'b1;
+ refill_request <= 1'b1;
refill_address <= address_m;
- state <= 3'b100;
+ state <= 3'b100;
end
- else if (dflush == 1'b1)
- state <= 3'b001;
+ else if (dflush == 1'b1)
+ state <= 3'b001;
end
- 3'b100:
+ 3'b100:
begin
- refill_request <= 1'b0;
- if (refill_ready == 1'b1)
+ refill_request <= 1'b0;
+ if (refill_ready == 1'b1)
begin
- if (last_refill == 1'b1)
+ if (last_refill == 1'b1)
begin
- restart_request <= 1'b1;
- state <= 3'b010;
+ restart_request <= 1'b1;
+ state <= 3'b010;
end
end
end
@@ -9095,25 +8166,25 @@ generate
if (bytes_per_line > 4)
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
else
begin
case (state)
- 3'b010:
+ 3'b010:
begin
- if (miss == 1'b1)
+ if (miss == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
end
- 3'b100:
+ 3'b100:
begin
- if (refill_ready == 1'b1)
+ if (refill_ready == 1'b1)
refill_offset <= refill_offset + 1'b1;
end
@@ -9125,7 +8196,6 @@ endgenerate
endmodule
-
@@ -9159,7 +8229,7 @@ endmodule
-
+
@@ -9190,11 +8260,8 @@ endmodule
-
-
-
-
+
@@ -9478,9 +8545,7 @@ endmodule
-
-
-
+
@@ -9841,11 +8906,7 @@ endmodule
-
-
-
-
-
+
@@ -9875,9 +8936,9 @@ endmodule
-
+
@@ -10162,8 +9223,6 @@ endmodule
-
-
@@ -10182,50 +9241,40 @@ module lm32_instruction_unit_full (
kill_f,
branch_predict_taken_d,
branch_predict_address_d,
-
-
+
branch_taken_x,
branch_target_x,
-
exception_m,
branch_taken_m,
branch_mispredict_taken_m,
branch_target_m,
-
-
- iflush,
+ iflush,
-
-
+
dcache_restart_request,
dcache_refill_request,
dcache_refilling,
-
-
+
-
-
-
+
i_dat_i,
i_ack_i,
i_err_i,
i_rty_i,
-
-
+
-
pc_f,
@@ -10233,20 +9282,16 @@ module lm32_instruction_unit_full (
pc_x,
pc_m,
pc_w,
-
-
+
icache_stall_request,
icache_restart_request,
icache_refill_request,
icache_refilling,
-
-
+
-
-
-
+
i_dat_o,
i_adr_o,
@@ -10257,22 +9302,16 @@ module lm32_instruction_unit_full (
i_cti_o,
i_lock_o,
i_bte_o,
-
-
+
-
-
-
- bus_error_d,
+ bus_error_d,
-
-
- instruction_f,
+ instruction_f,
instruction_d
);
@@ -10309,49 +9348,40 @@ input valid_d;
input kill_f;
input branch_predict_taken_d;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
-
-
+
input branch_taken_x;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
-
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
input exception_m;
input branch_taken_m;
input branch_mispredict_taken_m;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
-
-
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
-input iflush;
+input iflush;
-
-
+
input dcache_restart_request;
input dcache_refill_request;
input dcache_refilling;
-
-
+
-
-
-
-input [ (32-1):0] i_dat_i;
+
+input [(32-1):0] i_dat_i;
input i_ack_i;
input i_err_i;
input i_rty_i;
-
-
+
@@ -10361,21 +9391,19 @@ input i_rty_i;
-
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-
-
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
output icache_stall_request;
wire icache_stall_request;
output icache_restart_request;
@@ -10384,127 +9412,103 @@ output icache_refill_request;
wire icache_refill_request;
output icache_refilling;
wire icache_refilling;
-
-
+
-
-
-
-output [ (32-1):0] i_dat_o;
-
+
+output [(32-1):0] i_dat_o;
+
+wire [(32-1):0] i_dat_o;
-wire [ (32-1):0] i_dat_o;
-
-
-output [ (32-1):0] i_adr_o;
-reg [ (32-1):0] i_adr_o;
+output [(32-1):0] i_adr_o;
+reg [(32-1):0] i_adr_o;
output i_cyc_o;
reg i_cyc_o;
-output [ (4-1):0] i_sel_o;
-
+output [(4-1):0] i_sel_o;
+
-
-wire [ (4-1):0] i_sel_o;
-
+wire [(4-1):0] i_sel_o;
output i_stb_o;
reg i_stb_o;
output i_we_o;
-
+
-
wire i_we_o;
-
-output [ (3-1):0] i_cti_o;
-reg [ (3-1):0] i_cti_o;
+output [(3-1):0] i_cti_o;
+reg [(3-1):0] i_cti_o;
output i_lock_o;
reg i_lock_o;
-output [ (2-1):0] i_bte_o;
-wire [ (2-1):0] i_bte_o;
-
+output [(2-1):0] i_bte_o;
+wire [(2-1):0] i_bte_o;
-
+
-
-
-
+
output bus_error_d;
reg bus_error_d;
-
-
-
-output [ (32-1):0] instruction_f;
-wire [ (32-1):0] instruction_f;
+output [(32-1):0] instruction_f;
+wire [(32-1):0] instruction_f;
-output [ (32-1):0] instruction_d;
-reg [ (32-1):0] instruction_d;
+output [(32-1):0] instruction_d;
+reg [(32-1):0] instruction_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;
-
-
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;
-
-
+
wire icache_read_enable_f;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;
reg icache_refill_ready;
-reg [ (32-1):0] icache_refill_data;
-wire [ (32-1):0] icache_data_f;
-wire [ (3-1):0] first_cycle_type;
-wire [ (3-1):0] next_cycle_type;
+reg [(32-1):0] icache_refill_data;
+wire [(32-1):0] icache_data_f;
+wire [(3-1):0] first_cycle_type;
+wire [(3-1):0] next_cycle_type;
wire last_word;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;
-
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;
+
-
-
+
-
-
-
-
+
-
-
-reg bus_error_f;
+reg bus_error_f;
-
+
@@ -10512,10 +9516,7 @@ reg bus_error_f;
-
-
-
-
+
@@ -10571,8 +9572,7 @@ endfunction
-
-
+
@@ -10618,11 +9618,9 @@ endfunction
-
-
-
+
lm32_icache_full #(
.associativity (associativity),
@@ -10652,84 +9650,68 @@ lm32_icache_full #(
.refilling (icache_refilling),
.inst (icache_data_f)
);
-
-
-
-
-assign icache_read_enable_f = (valid_f == 1'b1)
- && (kill_f == 1'b0)
-
+
- && (dcache_restart_request == 1'b0)
+assign icache_read_enable_f = (valid_f == 1'b1)
+ && (kill_f == 1'b0)
+ && (dcache_restart_request == 1'b0)
-
+
-
;
-
always @(*)
begin
-
-
- if (dcache_restart_request == 1'b1)
+
+ if (dcache_restart_request == 1'b1)
pc_a = restart_address;
else
-
- if (branch_taken_m == 1'b1)
- if ((branch_mispredict_taken_m == 1'b1) && (exception_m == 1'b0))
+ if (branch_taken_m == 1'b1)
+ if ((branch_mispredict_taken_m == 1'b1) && (exception_m == 1'b0))
pc_a = pc_x;
else
pc_a = branch_target_m;
-
-
- else if (branch_taken_x == 1'b1)
+
+ else if (branch_taken_x == 1'b1)
pc_a = branch_target_x;
-
else
- if ( (valid_d == 1'b1) && (branch_predict_taken_d == 1'b1) )
+ if ( (valid_d == 1'b1) && (branch_predict_taken_d == 1'b1) )
pc_a = branch_predict_address_d;
else
-
-
- if (icache_restart_request == 1'b1)
+
+ if (icache_restart_request == 1'b1)
pc_a = restart_address;
else
-
pc_a = pc_f + 1'b1;
end
-
+
-
-
-
-
+
+
-
assign instruction_f = icache_data_f;
-
-
+
@@ -10742,50 +9724,43 @@ assign instruction_f = icache_data_f;
-
-
-
-
-
+
+
assign i_dat_o = 32'd0;
-assign i_we_o = 1'b0;
+assign i_we_o = 1'b0;
assign i_sel_o = 4'b1111;
-
-
-assign i_bte_o = 2'b00;
-
+assign i_bte_o = 2'b00;
-
+
generate
case (bytes_per_line)
4:
begin
-assign first_cycle_type = 3'b111;
-assign next_cycle_type = 3'b111;
-assign last_word = 1'b1;
+assign first_cycle_type = 3'b111;
+assign next_cycle_type = 3'b111;
+assign last_word = 1'b1;
assign first_address = icache_refill_address;
end
8:
begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = 3'b111;
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = 3'b111;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
-assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+assign first_address = {icache_refill_address[(clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
end
16:
begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
-assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+assign first_address = {icache_refill_address[(clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
end
endcase
endgenerate
-
@@ -10793,67 +9768,61 @@ endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- pc_f <= ( 32'h00000000-4)/4;
- pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_f <= (32'h00000000-4)/4;
+ pc_d <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_x <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_m <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_w <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
end
else
begin
- if (stall_f == 1'b0)
+ if (stall_f == 1'b0)
pc_f <= pc_a;
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
pc_d <= pc_f;
- if (stall_x == 1'b0)
+ if (stall_x == 1'b0)
pc_x <= pc_d;
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
pc_m <= pc_x;
pc_w <= pc_m;
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ if (rst_i == 1'b1)
+ restart_address <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
else
begin
-
-
-
-
+
+
- if (dcache_refill_request == 1'b1)
+ if (dcache_refill_request == 1'b1)
restart_address <= pc_w;
- else if ((icache_refill_request == 1'b1) && (!dcache_refilling) && (!dcache_restart_request))
+ else if ((icache_refill_request == 1'b1) && (!dcache_refilling) && (!dcache_restart_request))
restart_address <= icache_refill_address;
-
+
-
-
end
end
-
-
+
@@ -10866,8 +9835,7 @@ end
-
-
+
@@ -10880,45 +9848,39 @@ end
+
-
-
-
-
-
-always @(posedge clk_i )
+
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_adr_o <= { 32{1'b0}};
- i_cti_o <= 3'b111;
- i_lock_o <= 1'b0;
- icache_refill_data <= { 32{1'b0}};
- icache_refill_ready <= 1'b0;
-
-
- bus_error_f <= 1'b0;
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_adr_o <= {32{1'b0}};
+ i_cti_o <= 3'b111;
+ i_lock_o <= 1'b0;
+ icache_refill_data <= {32{1'b0}};
+ icache_refill_ready <= 1'b0;
+ bus_error_f <= 1'b0;
-
+
-
end
else
begin
- icache_refill_ready <= 1'b0;
+ icache_refill_ready <= 1'b0;
- if (i_cyc_o == 1'b1)
+ if (i_cyc_o == 1'b1)
begin
- if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
+ if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
begin
-
+
@@ -10928,54 +9890,48 @@ begin
-
begin
- if (last_word == 1'b1)
+ if (last_word == 1'b1)
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_lock_o <= 1'b0;
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_lock_o <= 1'b0;
end
i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
i_cti_o <= next_cycle_type;
- icache_refill_ready <= 1'b1;
+ icache_refill_ready <= 1'b1;
icache_refill_data <= i_dat_i;
end
end
-
-
- if (i_err_i == 1'b1)
+
+ if (i_err_i == 1'b1)
begin
- bus_error_f <= 1'b1;
+ bus_error_f <= 1'b1;
$display ("Instruction bus error. Address: %x", i_adr_o);
end
-
end
else
begin
- if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
+ if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
begin
-
+
-
i_adr_o <= {first_address, 2'b00};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
i_cti_o <= first_cycle_type;
-
-
- bus_error_f <= 1'b0;
+ bus_error_f <= 1'b0;
end
-
+
@@ -10995,26 +9951,21 @@ begin
-
-
-
+
-
-
- if (branch_taken_x == 1'b1)
- bus_error_f <= 1'b0;
-
+
+ if (branch_taken_x == 1'b1)
+ bus_error_f <= 1'b0;
- if (branch_taken_m == 1'b1)
- bus_error_f <= 1'b0;
-
+ if (branch_taken_m == 1'b1)
+ bus_error_f <= 1'b0;
end
end
end
-
+
@@ -11088,31 +10039,25 @@ end
-
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- instruction_d <= { 32{1'b0}};
-
-
- bus_error_d <= 1'b0;
+ instruction_d <= {32{1'b0}};
+ bus_error_d <= 1'b0;
end
else
begin
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
begin
instruction_d <= instruction_f;
-
-
- bus_error_d <= bus_error_f;
+ bus_error_d <= bus_error_f;
end
end
@@ -11147,10 +10092,7 @@ endmodule
-
-
-
-
+
@@ -11180,9 +10122,9 @@ endmodule
-
+
@@ -11466,9 +10408,7 @@ endmodule
-
-
-
+
@@ -11935,11 +10875,7 @@ endmodule
-
-
-
-
-
+
@@ -11969,9 +10905,9 @@ endmodule
-
+
@@ -12256,8 +11192,6 @@ endmodule
-
-
@@ -12269,19 +11203,16 @@ module lm32_interrupt_full (
interrupt,
stall_x,
-
+
-
exception,
-
eret_q_x,
-
+
-
csr,
csr_write_data,
csr_write_enable,
@@ -12295,7 +11226,7 @@ module lm32_interrupt_full (
-parameter interrupts = 32;
+parameter interrupts = 32;
@@ -12308,22 +11239,19 @@ input [interrupts-1:0] interrupt;
input stall_x;
-
+
-
input exception;
-
input eret_q_x;
-
+
-
-input [ (3-1):0] csr;
-input [ (32-1):0] csr_write_data;
+input [(3-1):0] csr;
+input [(32-1):0] csr_write_data;
input csr_write_enable;
@@ -12333,8 +11261,8 @@ input csr_write_enable;
output interrupt_exception;
wire interrupt_exception;
-output [ (32-1):0] csr_read_data;
-reg [ (32-1):0] csr_read_data;
+output [(32-1):0] csr_read_data;
+reg [(32-1):0] csr_read_data;
@@ -12348,10 +11276,9 @@ wire [interrupts-1:0] interrupt_n_exception;
reg ie;
reg eie;
-
+
-
reg [interrupts-1:0] ip;
reg [interrupts-1:0] im;
@@ -12368,13 +11295,11 @@ assign interrupt_exception = (|interrupt_n_exception) & ie;
assign asserted = ip | interrupt;
-assign ie_csr_read_data = {{ 32-3{1'b0}},
-
+assign ie_csr_read_data = {{32-3{1'b0}},
+
-
1'b0,
-
eie,
ie
@@ -12388,20 +11313,18 @@ generate
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
-
+ 3'h0: csr_read_data = {{32-3{1'b0}},
+
-
1'b0,
-
eie,
ie
};
- 3'h2: csr_read_data = ip;
- 3'h1: csr_read_data = im;
- default: csr_read_data = { 32{1'bx}};
+ 3'h2: csr_read_data = ip;
+ 3'h1: csr_read_data = im;
+ default: csr_read_data = {32{1'bx}};
endcase
end
end
@@ -12411,19 +11334,17 @@ end
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
-
+ 3'h0: csr_read_data = {{32-3{1'b0}},
+
-
1'b0,
-
eie,
ie
};
- 3'h2: csr_read_data = ip;
- default: csr_read_data = { 32{1'bx}};
+ 3'h2: csr_read_data = ip;
+ default: csr_read_data = {32{1'bx}};
endcase
end
end
@@ -12433,9 +11354,8 @@ endgenerate
-
-
- reg [ 10:0] eie_delay = 0;
+
+ reg [10:0] eie_delay = 0;
generate
@@ -12444,16 +11364,15 @@ generate
if (interrupts > 1)
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- ie <= 1'b0;
- eie <= 1'b0;
-
+ ie <= 1'b0;
+ eie <= 1'b0;
+
-
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
eie_delay <= 0;
@@ -12463,7 +11382,7 @@ always @(posedge clk_i )
begin
ip <= asserted;
-
+
@@ -12477,52 +11396,48 @@ always @(posedge clk_i )
-
- if (exception == 1'b1)
+ if (exception == 1'b1)
begin
eie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
-
- else if (stall_x == 1'b0)
+ else if (stall_x == 1'b0)
begin
if(eie_delay[0])
ie <= eie;
- eie_delay <= {1'b0, eie_delay[ 10:1]};
+ eie_delay <= {1'b0, eie_delay[10:1]};
- if (eret_q_x == 1'b1) begin
+ if (eret_q_x == 1'b1) begin
- eie_delay[ 10] <= 1'b1;
- eie_delay[ 10-1:0] <= 0;
+ eie_delay[10] <= 1'b1;
+ eie_delay[10-1:0] <= 0;
end
-
+
-
- else if (csr_write_enable == 1'b1)
+ else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 3'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
+
-
end
- if (csr == 3'h1)
+ if (csr == 3'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 3'h2)
+ if (csr == 3'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -12532,16 +11447,15 @@ end
else
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- ie <= 1'b0;
- eie <= 1'b0;
-
+ ie <= 1'b0;
+ eie <= 1'b0;
+
-
ip <= {interrupts{1'b0}};
eie_delay <= 0;
end
@@ -12549,7 +11463,7 @@ always @(posedge clk_i )
begin
ip <= asserted;
-
+
@@ -12563,48 +11477,44 @@ always @(posedge clk_i )
-
- if (exception == 1'b1)
+ if (exception == 1'b1)
begin
eie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
-
- else if (stall_x == 1'b0)
+ else if (stall_x == 1'b0)
begin
if(eie_delay[0])
ie <= eie;
- eie_delay <= {1'b0, eie_delay[ 10:1]};
+ eie_delay <= {1'b0, eie_delay[10:1]};
- if (eret_q_x == 1'b1) begin
+ if (eret_q_x == 1'b1) begin
- eie_delay[ 10] <= 1'b1;
- eie_delay[ 10-1:0] <= 0;
+ eie_delay[10] <= 1'b1;
+ eie_delay[10-1:0] <= 0;
end
-
+
-
- else if (csr_write_enable == 1'b1)
+ else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 3'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
+
-
end
- if (csr == 3'h2)
+ if (csr == 3'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -12644,251 +11554,350 @@ endmodule
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
+
+
+
+
+
+
+
-
+
+
-
+
+
-
-
-
+
+
+
+
+
-
-
+
+
+
+
-
-
-
+
-
-
+
-
+
+
+
+
+
+
+
+
+
+
-
+
+
+
+
+
+
-
-
+
+
+
+
+
+
+
+
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
+
+
+
+
+
+
+
+
+
+
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
-
+
+
+
-
+
+
+
+
-
+
+
+
+
-
+
+
-
-
-
-
+
+
-
-
-
-
+
+
+
+
-
+
+
+
+
-
-
+
-
-
-
-
-
-
+
+
-
-
-
-
+
+
+
@@ -12897,496 +11906,181 @@ endmodule
-
-
-
-
-
+module lm32_top_full_debug (
+
+ clk_i,
+ rst_i,
+
+ interrupt,
-
+
+
+
+
+
+
+ I_DAT_I,
+ I_ACK_I,
+ I_ERR_I,
+ I_RTY_I,
+
+ D_DAT_I,
+ D_ACK_I,
+ D_ERR_I,
+ D_RTY_I,
+
+
+
+
+
+
+
+
+
+ I_DAT_O,
+ I_ADR_O,
+ I_CYC_O,
+ I_SEL_O,
+ I_STB_O,
+ I_WE_O,
+ I_CTI_O,
+ I_LOCK_O,
+ I_BTE_O,
+
+ D_DAT_O,
+ D_ADR_O,
+ D_CYC_O,
+ D_SEL_O,
+ D_STB_O,
+ D_WE_O,
+ D_CTI_O,
+ D_LOCK_O,
+ D_BTE_O
+ );
-
-
-
-
-
+input clk_i;
+input rst_i;
+input [(32-1):0] interrupt;
-
+
+
+
+
+
+input [(32-1):0] I_DAT_I;
+input I_ACK_I;
+input I_ERR_I;
+input I_RTY_I;
-
+input [(32-1):0] D_DAT_I;
+input D_ACK_I;
+input D_ERR_I;
+input D_RTY_I;
-
-
-
+
+
+
+
+
+
+
+
+
-
-
+
+output [(32-1):0] I_DAT_O;
+wire [(32-1):0] I_DAT_O;
+output [(32-1):0] I_ADR_O;
+wire [(32-1):0] I_ADR_O;
+output I_CYC_O;
+wire I_CYC_O;
+output [(4-1):0] I_SEL_O;
+wire [(4-1):0] I_SEL_O;
+output I_STB_O;
+wire I_STB_O;
+output I_WE_O;
+wire I_WE_O;
+output [(3-1):0] I_CTI_O;
+wire [(3-1):0] I_CTI_O;
+output I_LOCK_O;
+wire I_LOCK_O;
+output [(2-1):0] I_BTE_O;
+wire [(2-1):0] I_BTE_O;
-
+output [(32-1):0] D_DAT_O;
+wire [(32-1):0] D_DAT_O;
+output [(32-1):0] D_ADR_O;
+wire [(32-1):0] D_ADR_O;
+output D_CYC_O;
+wire D_CYC_O;
+output [(4-1):0] D_SEL_O;
+wire [(4-1):0] D_SEL_O;
+output D_STB_O;
+wire D_STB_O;
+output D_WE_O;
+wire D_WE_O;
+output [(3-1):0] D_CTI_O;
+wire [(3-1):0] D_CTI_O;
+output D_LOCK_O;
+wire D_LOCK_O;
+output [(2-1):0] D_BTE_O;
+wire [(2-1):0] D_BTE_O;
-
-
-
+
+
+wire [7:0] jtag_reg_d;
+wire [7:0] jtag_reg_q;
+wire jtag_update;
+wire [2:0] jtag_reg_addr_d;
+wire [2:0] jtag_reg_addr_q;
+wire jtck;
+wire jrstn;
-
-
+
-
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-module lm32_top_full_debug (
-
- clk_i,
- rst_i,
-
-
- interrupt,
-
-
-
-
-
-
-
-
-
-
- I_DAT_I,
- I_ACK_I,
- I_ERR_I,
- I_RTY_I,
-
-
-
- D_DAT_I,
- D_ACK_I,
- D_ERR_I,
- D_RTY_I,
-
-
-
-
-
-
-
-
-
-
-
- I_DAT_O,
- I_ADR_O,
- I_CYC_O,
- I_SEL_O,
- I_STB_O,
- I_WE_O,
- I_CTI_O,
- I_LOCK_O,
- I_BTE_O,
-
-
-
- D_DAT_O,
- D_ADR_O,
- D_CYC_O,
- D_SEL_O,
- D_STB_O,
- D_WE_O,
- D_CTI_O,
- D_LOCK_O,
- D_BTE_O
- );
-
-
-
-
-
-input clk_i;
-input rst_i;
-
-
-input [ (32-1):0] interrupt;
-
-
-
-
-
-
-
-
-
-
-input [ (32-1):0] I_DAT_I;
-input I_ACK_I;
-input I_ERR_I;
-input I_RTY_I;
-
-
-
-input [ (32-1):0] D_DAT_I;
-input D_ACK_I;
-input D_ERR_I;
-input D_RTY_I;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-output [ (32-1):0] I_DAT_O;
-wire [ (32-1):0] I_DAT_O;
-output [ (32-1):0] I_ADR_O;
-wire [ (32-1):0] I_ADR_O;
-output I_CYC_O;
-wire I_CYC_O;
-output [ (4-1):0] I_SEL_O;
-wire [ (4-1):0] I_SEL_O;
-output I_STB_O;
-wire I_STB_O;
-output I_WE_O;
-wire I_WE_O;
-output [ (3-1):0] I_CTI_O;
-wire [ (3-1):0] I_CTI_O;
-output I_LOCK_O;
-wire I_LOCK_O;
-output [ (2-1):0] I_BTE_O;
-wire [ (2-1):0] I_BTE_O;
-
-
-
-output [ (32-1):0] D_DAT_O;
-wire [ (32-1):0] D_DAT_O;
-output [ (32-1):0] D_ADR_O;
-wire [ (32-1):0] D_ADR_O;
-output D_CYC_O;
-wire D_CYC_O;
-output [ (4-1):0] D_SEL_O;
-wire [ (4-1):0] D_SEL_O;
-output D_STB_O;
-wire D_STB_O;
-output D_WE_O;
-wire D_WE_O;
-output [ (3-1):0] D_CTI_O;
-wire [ (3-1):0] D_CTI_O;
-output D_LOCK_O;
-wire D_LOCK_O;
-output [ (2-1):0] D_BTE_O;
-wire [ (2-1):0] D_BTE_O;
-
-
-
-
-
-
-
-
-wire [ 7:0] jtag_reg_d;
-wire [ 7:0] jtag_reg_q;
-wire jtag_update;
-wire [2:0] jtag_reg_addr_d;
-wire [2:0] jtag_reg_addr_q;
-wire jtck;
-wire jrstn;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
@@ -13439,46 +12133,37 @@ endfunction
-
lm32_cpu_full_debug cpu (
.clk_i (clk_i),
-
+
-
.rst_i (rst_i),
-
-
- .interrupt (interrupt),
+ .interrupt (interrupt),
-
+
-
-
-
+
.jtag_clk (jtck),
.jtag_update (jtag_update),
.jtag_reg_q (jtag_reg_q),
.jtag_reg_addr_q (jtag_reg_addr_q),
-
-
-
+
.I_DAT_I (I_DAT_I),
.I_ACK_I (I_ACK_I),
.I_ERR_I (I_ERR_I),
.I_RTY_I (I_RTY_I),
-
.D_DAT_I (D_DAT_I),
@@ -13486,7 +12171,7 @@ lm32_cpu_full_debug cpu (
.D_ERR_I (D_ERR_I),
.D_RTY_I (D_RTY_I),
-
+
@@ -13496,22 +12181,17 @@ lm32_cpu_full_debug cpu (
-
-
-
+
.jtag_reg_d (jtag_reg_d),
.jtag_reg_addr_d (jtag_reg_addr_d),
-
-
+
-
-
-
+
.I_DAT_O (I_DAT_O),
.I_ADR_O (I_ADR_O),
@@ -13522,8 +12202,7 @@ lm32_cpu_full_debug cpu (
.I_CTI_O (I_CTI_O),
.I_LOCK_O (I_LOCK_O),
.I_BTE_O (I_BTE_O),
-
-
+
.D_DAT_O (D_DAT_O),
.D_ADR_O (D_ADR_O),
@@ -13536,8 +12215,7 @@ lm32_cpu_full_debug cpu (
.D_BTE_O (D_BTE_O)
);
-
-
+
jtag_cores jtag_cores (
@@ -13550,7 +12228,6 @@ jtag_cores jtag_cores (
.jtck (jtck),
.jrstn (jrstn)
);
-
endmodule
@@ -13582,10 +12259,7 @@ endmodule
-
-
-
-
+
@@ -13615,9 +12289,9 @@ endmodule
-
+
@@ -13899,24 +12573,15 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
@@ -13928,30 +12593,24 @@ module lm32_mc_arithmetic_full_debug (
rst_i,
stall_d,
kill_x,
-
-
+
divide_d,
modulus_d,
-
-
+
-
-
+
-
operand_0_d,
operand_1_d,
result_x,
-
-
- divide_by_zero_x,
+ divide_by_zero_x,
stall_request_x
);
@@ -13964,36 +12623,30 @@ input clk_i;
input rst_i;
input stall_d;
input kill_x;
-
-
+
input divide_d;
input modulus_d;
-
-
+
-
-
+
-
-input [ (32-1):0] operand_0_d;
-input [ (32-1):0] operand_1_d;
-
+input [(32-1):0] operand_0_d;
+input [(32-1):0] operand_1_d;
-output [ (32-1):0] result_x;
-reg [ (32-1):0] result_x;
-
+output [(32-1):0] result_x;
+reg [(32-1):0] result_x;
+
output divide_by_zero_x;
reg divide_by_zero_x;
-
output stall_request_x;
wire stall_request_x;
@@ -14002,19 +12655,17 @@ wire stall_request_x;
-reg [ (32-1):0] p;
-reg [ (32-1):0] a;
-reg [ (32-1):0] b;
-
-
-wire [32:0] t;
+reg [(32-1):0] p;
+reg [(32-1):0] a;
+reg [(32-1):0] b;
+wire [32:0] t;
-reg [ 2:0] state;
+reg [2:0] state;
reg [5:0] cycles;
-
+
@@ -14024,18 +12675,15 @@ reg [5:0] cycles;
+assign stall_request_x = state != 3'b000;
-assign stall_request_x = state != 3'b000;
+
-
+assign t = {p[32-2:0], a[32-1]} - b;
-assign t = {p[ 32-2:0], a[ 32-1]} - b;
-
-
-
@@ -14044,57 +12692,48 @@ assign t = {p[ 32-2:0], a[ 32-1]} - b;
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
cycles <= {6{1'b0}};
- p <= { 32{1'b0}};
- a <= { 32{1'b0}};
- b <= { 32{1'b0}};
-
+ p <= {32{1'b0}};
+ a <= {32{1'b0}};
+ b <= {32{1'b0}};
+
-
-
-
- divide_by_zero_x <= 1'b0;
+ divide_by_zero_x <= 1'b0;
- result_x <= { 32{1'b0}};
- state <= 3'b000;
+ result_x <= {32{1'b0}};
+ state <= 3'b000;
end
else
begin
-
-
- divide_by_zero_x <= 1'b0;
+ divide_by_zero_x <= 1'b0;
case (state)
- 3'b000:
+ 3'b000:
begin
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
begin
- cycles <= 32;
+ cycles <= 32;
p <= 32'b0;
a <= operand_0_d;
b <= operand_1_d;
-
-
- if (divide_d == 1'b1)
- state <= 3'b011 ;
- if (modulus_d == 1'b1)
- state <= 3'b010 ;
+ if (divide_d == 1'b1)
+ state <= 3'b011 ;
+ if (modulus_d == 1'b1)
+ state <= 3'b010 ;
-
+
-
-
+
@@ -14111,57 +12750,54 @@ begin
-
end
end
-
-
- 3'b011 :
+
+ 3'b011 :
begin
if (t[32] == 1'b0)
begin
p <= t[31:0];
- a <= {a[ 32-2:0], 1'b1};
+ a <= {a[32-2:0], 1'b1};
end
else
begin
- p <= {p[ 32-2:0], a[ 32-1]};
- a <= {a[ 32-2:0], 1'b0};
+ p <= {p[32-2:0], a[32-1]};
+ a <= {a[32-2:0], 1'b0};
end
result_x <= a;
- if ((cycles == 32'd0) || (kill_x == 1'b1))
+ if ((cycles == 32'd0) || (kill_x == 1'b1))
begin
- divide_by_zero_x <= b == { 32{1'b0}};
- state <= 3'b000;
+ divide_by_zero_x <= b == {32{1'b0}};
+ state <= 3'b000;
end
cycles <= cycles - 1'b1;
end
- 3'b010 :
+ 3'b010 :
begin
if (t[32] == 1'b0)
begin
p <= t[31:0];
- a <= {a[ 32-2:0], 1'b1};
+ a <= {a[32-2:0], 1'b1};
end
else
begin
- p <= {p[ 32-2:0], a[ 32-1]};
- a <= {a[ 32-2:0], 1'b0};
+ p <= {p[32-2:0], a[32-1]};
+ a <= {a[32-2:0], 1'b0};
end
result_x <= p;
- if ((cycles == 32'd0) || (kill_x == 1'b1))
+ if ((cycles == 32'd0) || (kill_x == 1'b1))
begin
- divide_by_zero_x <= b == { 32{1'b0}};
- state <= 3'b000;
+ divide_by_zero_x <= b == {32{1'b0}};
+ state <= 3'b000;
end
cycles <= cycles - 1'b1;
end
-
-
+
@@ -14173,9 +12809,8 @@ begin
-
-
+
@@ -14192,7 +12827,6 @@ begin
-
endcase
end
@@ -14263,10 +12897,7 @@ endmodule
-
-
-
-
+
@@ -14296,9 +12927,9 @@ endmodule
-
+
@@ -14583,48 +13214,38 @@ endmodule
-
-
module lm32_cpu_full_debug (
clk_i,
-
+
-
rst_i,
-
-
- interrupt,
+ interrupt,
-
+
-
-
-
+
jtag_clk,
jtag_update,
jtag_reg_q,
jtag_reg_addr_q,
-
-
-
+
I_DAT_I,
I_ACK_I,
I_ERR_I,
I_RTY_I,
-
D_DAT_I,
@@ -14632,7 +13253,7 @@ module lm32_cpu_full_debug (
D_ERR_I,
D_RTY_I,
-
+
@@ -14642,22 +13263,17 @@ module lm32_cpu_full_debug (
-
-
-
+
jtag_reg_d,
jtag_reg_addr_d,
-
-
+
-
-
-
+
I_DAT_O,
I_ADR_O,
@@ -14668,7 +13284,6 @@ module lm32_cpu_full_debug (
I_CTI_O,
I_LOCK_O,
I_BTE_O,
-
D_DAT_O,
@@ -14686,21 +13301,18 @@ module lm32_cpu_full_debug (
-parameter eba_reset = 32'h00000000;
-
-
-parameter deba_reset = 32'h10000000;
+parameter eba_reset = 32'h00000000;
+parameter deba_reset = 32'h10000000;
-
-
-parameter icache_associativity = 1;
-parameter icache_sets = 256;
-parameter icache_bytes_per_line = 16;
-parameter icache_base_address = 32'h0;
-parameter icache_limit = 32'h7fffffff;
+parameter icache_associativity = 1;
+parameter icache_sets = 256;
+parameter icache_bytes_per_line = 16;
+parameter icache_base_address = 32'h0;
+parameter icache_limit = 32'h7fffffff;
+
@@ -14708,15 +13320,13 @@ parameter icache_limit = 32'h7fffffff;
-
-
-
-parameter dcache_associativity = 1;
-parameter dcache_sets = 256;
-parameter dcache_bytes_per_line = 16;
-parameter dcache_base_address = 32'h0;
-parameter dcache_limit = 32'h7fffffff;
+parameter dcache_associativity = 1;
+parameter dcache_sets = 256;
+parameter dcache_bytes_per_line = 16;
+parameter dcache_base_address = 32'h0;
+parameter dcache_limit = 32'h7fffffff;
+
@@ -14724,28 +13334,21 @@ parameter dcache_limit = 32'h7fffffff;
-
-
-
-parameter watchpoints = 32'h4;
-
+parameter watchpoints = 32'h4;
+
-
+
-
parameter breakpoints = 0;
-
-
-
-parameter interrupts = 32;
-
+parameter interrupts = 32;
+
@@ -14753,43 +13356,35 @@ parameter interrupts = 32;
input clk_i;
-
+
-
input rst_i;
-
-
-input [ (32-1):0] interrupt;
+input [(32-1):0] interrupt;
-
+
-
-
-
+
input jtag_clk;
input jtag_update;
-input [ 7:0] jtag_reg_q;
+input [7:0] jtag_reg_q;
input [2:0] jtag_reg_addr_q;
-
-
-
-input [ (32-1):0] I_DAT_I;
+
+input [(32-1):0] I_DAT_I;
input I_ACK_I;
input I_ERR_I;
input I_RTY_I;
-
-input [ (32-1):0] D_DAT_I;
+input [(32-1):0] D_DAT_I;
input D_ACK_I;
input D_ERR_I;
input D_RTY_I;
@@ -14798,7 +13393,7 @@ input D_RTY_I;
-
+
@@ -14815,17 +13410,14 @@ input D_RTY_I;
-
-
-
-output [ 7:0] jtag_reg_d;
-wire [ 7:0] jtag_reg_d;
+
+output [7:0] jtag_reg_d;
+wire [7:0] jtag_reg_d;
output [2:0] jtag_reg_addr_d;
wire [2:0] jtag_reg_addr_d;
-
-
+
@@ -14836,59 +13428,54 @@ wire [2:0] jtag_reg_addr_d;
-
-
-
-output [ (32-1):0] I_DAT_O;
-wire [ (32-1):0] I_DAT_O;
-output [ (32-1):0] I_ADR_O;
-wire [ (32-1):0] I_ADR_O;
+
+output [(32-1):0] I_DAT_O;
+wire [(32-1):0] I_DAT_O;
+output [(32-1):0] I_ADR_O;
+wire [(32-1):0] I_ADR_O;
output I_CYC_O;
wire I_CYC_O;
-output [ (4-1):0] I_SEL_O;
-wire [ (4-1):0] I_SEL_O;
+output [(4-1):0] I_SEL_O;
+wire [(4-1):0] I_SEL_O;
output I_STB_O;
wire I_STB_O;
output I_WE_O;
wire I_WE_O;
-output [ (3-1):0] I_CTI_O;
-wire [ (3-1):0] I_CTI_O;
+output [(3-1):0] I_CTI_O;
+wire [(3-1):0] I_CTI_O;
output I_LOCK_O;
wire I_LOCK_O;
-output [ (2-1):0] I_BTE_O;
-wire [ (2-1):0] I_BTE_O;
-
+output [(2-1):0] I_BTE_O;
+wire [(2-1):0] I_BTE_O;
-output [ (32-1):0] D_DAT_O;
-wire [ (32-1):0] D_DAT_O;
-output [ (32-1):0] D_ADR_O;
-wire [ (32-1):0] D_ADR_O;
+output [(32-1):0] D_DAT_O;
+wire [(32-1):0] D_DAT_O;
+output [(32-1):0] D_ADR_O;
+wire [(32-1):0] D_ADR_O;
output D_CYC_O;
wire D_CYC_O;
-output [ (4-1):0] D_SEL_O;
-wire [ (4-1):0] D_SEL_O;
+output [(4-1):0] D_SEL_O;
+wire [(4-1):0] D_SEL_O;
output D_STB_O;
wire D_STB_O;
output D_WE_O;
wire D_WE_O;
-output [ (3-1):0] D_CTI_O;
-wire [ (3-1):0] D_CTI_O;
+output [(3-1):0] D_CTI_O;
+wire [(3-1):0] D_CTI_O;
output D_LOCK_O;
wire D_LOCK_O;
-output [ (2-1):0] D_BTE_O;
-wire [ (2-1):0] D_BTE_O;
-
+output [(2-1):0] D_BTE_O;
+wire [(2-1):0] D_BTE_O;
-
-reg valid_a;
+reg valid_a;
reg valid_f;
reg valid_d;
@@ -14897,7 +13484,7 @@ reg valid_m;
reg valid_w;
wire q_x;
-wire [ (32-1):0] immediate_d;
+wire [(32-1):0] immediate_d;
wire load_d;
reg load_x;
reg load_m;
@@ -14906,13 +13493,13 @@ wire store_q_x;
wire store_d;
reg store_x;
reg store_m;
-wire [ 1:0] size_d;
-reg [ 1:0] size_x;
+wire [1:0] size_d;
+reg [1:0] size_x;
wire branch_d;
wire branch_predict_d;
wire branch_predict_taken_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
wire bi_unconditional;
wire bi_conditional;
reg branch_x;
@@ -14924,61 +13511,51 @@ reg branch_predict_taken_m;
wire branch_mispredict_taken_m;
wire branch_flushX_m;
wire branch_reg_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
-wire [ 0:0] d_result_sel_0_d;
-wire [ 1:0] d_result_sel_1_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [0:0] d_result_sel_0_d;
+wire [1:0] d_result_sel_1_d;
wire x_result_sel_csr_d;
reg x_result_sel_csr_x;
-
-
+
wire x_result_sel_mc_arith_d;
reg x_result_sel_mc_arith_x;
-
-
+
-
-
-
+
wire x_result_sel_sext_d;
reg x_result_sel_sext_x;
-
wire x_result_sel_logic_d;
reg x_result_sel_logic_x;
-
+
-
wire x_result_sel_add_d;
reg x_result_sel_add_x;
wire m_result_sel_compare_d;
reg m_result_sel_compare_x;
reg m_result_sel_compare_m;
-
-
+
wire m_result_sel_shift_d;
reg m_result_sel_shift_x;
reg m_result_sel_shift_m;
-
wire w_result_sel_load_d;
reg w_result_sel_load_x;
reg w_result_sel_load_m;
reg w_result_sel_load_w;
-
-
+
wire w_result_sel_mul_d;
reg w_result_sel_mul_x;
reg w_result_sel_mul_m;
reg w_result_sel_mul_w;
-
wire x_bypass_enable_d;
reg x_bypass_enable_x;
@@ -14995,22 +13572,20 @@ wire write_enable_q_m;
reg write_enable_w;
wire write_enable_q_w;
wire read_enable_0_d;
-wire [ (5-1):0] read_idx_0_d;
+wire [(5-1):0] read_idx_0_d;
wire read_enable_1_d;
-wire [ (5-1):0] read_idx_1_d;
-wire [ (5-1):0] write_idx_d;
-reg [ (5-1):0] write_idx_x;
-reg [ (5-1):0] write_idx_m;
-reg [ (5-1):0] write_idx_w;
-wire [ (5-1):0] csr_d;
-reg [ (5-1):0] csr_x;
-wire [ (3-1):0] condition_d;
-reg [ (3-1):0] condition_x;
-
-
+wire [(5-1):0] read_idx_1_d;
+wire [(5-1):0] write_idx_d;
+reg [(5-1):0] write_idx_x;
+reg [(5-1):0] write_idx_m;
+reg [(5-1):0] write_idx_w;
+wire [(5-1):0] csr_d;
+reg [(5-1):0] csr_x;
+wire [(3-1):0] condition_d;
+reg [(3-1):0] condition_x;
+
wire break_d;
reg break_x;
-
wire scall_d;
reg scall_x;
@@ -15018,71 +13593,60 @@ wire eret_d;
reg eret_x;
wire eret_q_x;
reg eret_m;
-
+
-
-
-
+
wire bret_d;
reg bret_x;
wire bret_q_x;
reg bret_m;
-
-
-
+
wire csr_write_enable_d;
reg csr_write_enable_x;
wire csr_write_enable_q_x;
-
+
-
-
-
+
wire bus_error_d;
reg bus_error_x;
reg data_bus_error_exception_m;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] memop_pc_w;
-
-
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] memop_pc_w;
-reg [ (32-1):0] d_result_0;
-reg [ (32-1):0] d_result_1;
-reg [ (32-1):0] x_result;
-reg [ (32-1):0] m_result;
-reg [ (32-1):0] w_result;
-reg [ (32-1):0] operand_0_x;
-reg [ (32-1):0] operand_1_x;
-reg [ (32-1):0] store_operand_x;
-reg [ (32-1):0] operand_m;
-reg [ (32-1):0] operand_w;
+reg [(32-1):0] d_result_0;
+reg [(32-1):0] d_result_1;
+reg [(32-1):0] x_result;
+reg [(32-1):0] m_result;
+reg [(32-1):0] w_result;
+reg [(32-1):0] operand_0_x;
+reg [(32-1):0] operand_1_x;
+reg [(32-1):0] store_operand_x;
+reg [(32-1):0] operand_m;
+reg [(32-1):0] operand_w;
-
-reg [ (32-1):0] reg_data_live_0;
-reg [ (32-1):0] reg_data_live_1;
-reg use_buf;
-reg [ (32-1):0] reg_data_buf_0;
-reg [ (32-1):0] reg_data_buf_1;
-
-
+reg [(32-1):0] reg_data_live_0;
+reg [(32-1):0] reg_data_live_1;
+reg use_buf;
+reg [(32-1):0] reg_data_buf_0;
+reg [(32-1):0] reg_data_buf_1;
-
+
-wire [ (32-1):0] reg_data_0;
-wire [ (32-1):0] reg_data_1;
-reg [ (32-1):0] bypass_data_0;
-reg [ (32-1):0] bypass_data_1;
+wire [(32-1):0] reg_data_0;
+wire [(32-1):0] reg_data_1;
+reg [(32-1):0] bypass_data_0;
+reg [(32-1):0] bypass_data_1;
wire reg_write_enable_q_w;
reg interlock;
@@ -15097,123 +13661,101 @@ wire stall_m;
wire adder_op_d;
reg adder_op_x;
reg adder_op_x_n;
-wire [ (32-1):0] adder_result_x;
+wire [(32-1):0] adder_result_x;
wire adder_overflow_x;
wire adder_carry_n_x;
-wire [ 3:0] logic_op_d;
-reg [ 3:0] logic_op_x;
-wire [ (32-1):0] logic_result_x;
-
-
-
+wire [3:0] logic_op_d;
+reg [3:0] logic_op_x;
+wire [(32-1):0] logic_result_x;
-wire [ (32-1):0] sextb_result_x;
-wire [ (32-1):0] sexth_result_x;
-wire [ (32-1):0] sext_result_x;
+wire [(32-1):0] sextb_result_x;
+wire [(32-1):0] sexth_result_x;
+wire [(32-1):0] sext_result_x;
-
-
+
+
-
wire direction_d;
reg direction_x;
reg direction_m;
-wire [ (32-1):0] shifter_result_m;
-
+wire [(32-1):0] shifter_result_m;
-
+
-
-
+
-
-
-
-wire [ (32-1):0] multiplier_result_w;
+wire [(32-1):0] multiplier_result_w;
-
+
-
-
-
+
wire divide_d;
wire divide_q_d;
wire modulus_d;
wire modulus_q_d;
wire divide_by_zero_x;
-
-
-
-wire mc_stall_request_x;
-wire [ (32-1):0] mc_result_x;
+wire mc_stall_request_x;
+wire [(32-1):0] mc_result_x;
-
-
-wire [ (32-1):0] interrupt_csr_read_data_x;
+wire [(32-1):0] interrupt_csr_read_data_x;
-wire [ (32-1):0] cfg;
-wire [ (32-1):0] cfg2;
-
+wire [(32-1):0] cfg;
+wire [(32-1):0] cfg2;
+
-
-reg [ (32-1):0] csr_read_data_x;
+reg [(32-1):0] csr_read_data_x;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
-
-
-
-wire [ (32-1):0] instruction_f;
+wire [(32-1):0] instruction_f;
-wire [ (32-1):0] instruction_d;
-
-
+wire [(32-1):0] instruction_d;
+
wire iflush;
wire icache_stall_request;
wire icache_restart_request;
wire icache_refill_request;
wire icache_refilling;
-
-
+
@@ -15222,48 +13764,37 @@ wire icache_refilling;
-
-
-
+
wire dflush_x;
reg dflush_m;
wire dcache_stall_request;
wire dcache_restart_request;
wire dcache_refill_request;
wire dcache_refilling;
-
-wire [ (32-1):0] load_data_w;
+wire [(32-1):0] load_data_w;
wire stall_wb_load;
-
-
-
-
-wire [ (32-1):0] jtx_csr_read_data;
-wire [ (32-1):0] jrx_csr_read_data;
+
+wire [(32-1):0] jtx_csr_read_data;
+wire [(32-1):0] jrx_csr_read_data;
-
-
+
wire jtag_csr_write_enable;
-wire [ (32-1):0] jtag_csr_write_data;
-wire [ (5-1):0] jtag_csr;
+wire [(32-1):0] jtag_csr_write_data;
+wire [(5-1):0] jtag_csr;
wire jtag_read_enable;
-wire [ 7:0] jtag_read_data;
+wire [7:0] jtag_read_data;
wire jtag_write_enable;
-wire [ 7:0] jtag_write_data;
-wire [ (32-1):0] jtag_address;
+wire [7:0] jtag_write_data;
+wire [(32-1):0] jtag_address;
wire jtag_access_complete;
-
-
-
-wire jtag_break;
+wire jtag_break;
-
@@ -15281,10 +13812,8 @@ wire cmp_overflow;
wire cmp_carry_n;
reg condition_met_x;
reg condition_met_m;
-
-
+
wire branch_taken_x;
-
wire branch_taken_m;
@@ -15294,25 +13823,19 @@ wire kill_x;
wire kill_m;
wire kill_w;
-reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
-
-
-reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;
+reg [(clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
+reg [(clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;
-reg [ (3-1):0] eid_x;
-
+reg [(3-1):0] eid_x;
+
-
-
-
-
-
-wire dc_ss;
+
+wire dc_ss;
wire dc_re;
wire exception_x;
@@ -15325,60 +13848,43 @@ wire non_debug_exception_x;
reg non_debug_exception_m;
reg non_debug_exception_w;
wire non_debug_exception_q_w;
-
+
-
-
-
-
-
-wire reset_exception;
-
+wire reset_exception;
-
-wire interrupt_exception;
+wire interrupt_exception;
-
-
+
wire breakpoint_exception;
wire watchpoint_exception;
-
-
-
+
wire instruction_bus_error_exception;
wire data_bus_error_exception;
-
-
-
-wire divide_by_zero_exception;
+wire divide_by_zero_exception;
wire system_call_exception;
-
-
-reg data_bus_error_seen;
+reg data_bus_error_seen;
-
-
-
+
@@ -15434,7 +13940,6 @@ endfunction
-
lm32_instruction_unit_full_debug #(
.associativity (icache_associativity),
.sets (icache_sets),
@@ -15456,50 +13961,39 @@ lm32_instruction_unit_full_debug #(
.kill_f (kill_f),
.branch_predict_taken_d (branch_predict_taken_d),
.branch_predict_address_d (branch_predict_address_d),
-
-
+
.branch_taken_x (branch_taken_x),
.branch_target_x (branch_target_x),
-
.exception_m (exception_m),
.branch_taken_m (branch_taken_m),
.branch_mispredict_taken_m (branch_mispredict_taken_m),
.branch_target_m (branch_target_m),
-
-
- .iflush (iflush),
+ .iflush (iflush),
-
+
-
-
-
+
.dcache_restart_request (dcache_restart_request),
.dcache_refill_request (dcache_refill_request),
.dcache_refilling (dcache_refilling),
-
-
-
+
.i_dat_i (I_DAT_I),
.i_ack_i (I_ACK_I),
.i_err_i (I_ERR_I),
.i_rty_i (I_RTY_I),
-
-
-
+
.jtag_read_enable (jtag_read_enable),
.jtag_write_enable (jtag_write_enable),
.jtag_write_data (jtag_write_data),
.jtag_address (jtag_address),
-
@@ -15508,20 +14002,16 @@ lm32_instruction_unit_full_debug #(
.pc_x (pc_x),
.pc_m (pc_m),
.pc_w (pc_w),
-
-
+
.icache_stall_request (icache_stall_request),
.icache_restart_request (icache_restart_request),
.icache_refill_request (icache_refill_request),
.icache_refilling (icache_refilling),
-
-
+
-
-
-
+
.i_dat_o (I_DAT_O),
.i_adr_o (I_ADR_O),
@@ -15532,23 +14022,16 @@ lm32_instruction_unit_full_debug #(
.i_cti_o (I_CTI_O),
.i_lock_o (I_LOCK_O),
.i_bte_o (I_BTE_O),
-
-
-
+
.jtag_read_data (jtag_read_data),
.jtag_access_complete (jtag_access_complete),
-
-
-
- .bus_error_d (bus_error_d),
+ .bus_error_d (bus_error_d),
-
-
- .instruction_f (instruction_f),
+ .instruction_f (instruction_f),
.instruction_d (instruction_d)
);
@@ -15561,37 +14044,27 @@ lm32_decoder_full_debug decoder (
.d_result_sel_0 (d_result_sel_0_d),
.d_result_sel_1 (d_result_sel_1_d),
.x_result_sel_csr (x_result_sel_csr_d),
-
-
- .x_result_sel_mc_arith (x_result_sel_mc_arith_d),
+ .x_result_sel_mc_arith (x_result_sel_mc_arith_d),
-
+
-
-
-
- .x_result_sel_sext (x_result_sel_sext_d),
+ .x_result_sel_sext (x_result_sel_sext_d),
.x_result_sel_logic (x_result_sel_logic_d),
-
+
-
.x_result_sel_add (x_result_sel_add_d),
.m_result_sel_compare (m_result_sel_compare_d),
-
-
- .m_result_sel_shift (m_result_sel_shift_d),
+ .m_result_sel_shift (m_result_sel_shift_d),
.w_result_sel_load (w_result_sel_load_d),
-
-
- .w_result_sel_mul (w_result_sel_mul_d),
+ .w_result_sel_mul (w_result_sel_mul_d),
.x_bypass_enable (x_bypass_enable_d),
.m_bypass_enable (m_bypass_enable_d),
@@ -15609,47 +14082,36 @@ lm32_decoder_full_debug decoder (
.sign_extend (sign_extend_d),
.adder_op (adder_op_d),
.logic_op (logic_op_d),
-
-
- .direction (direction_d),
+ .direction (direction_d),
-
+
-
-
+
-
-
-
+
.divide (divide_d),
.modulus (modulus_d),
-
.branch (branch_d),
.bi_unconditional (bi_unconditional),
.bi_conditional (bi_conditional),
.branch_reg (branch_reg_d),
.condition (condition_d),
-
-
- .break_opcode (break_d),
+ .break_opcode (break_d),
.scall (scall_d),
.eret (eret_d),
-
-
- .bret (bret_d),
+ .bret (bret_d),
-
+
-
.csr_write_enable (csr_write_enable_d)
);
@@ -15683,15 +14145,12 @@ lm32_load_store_unit_full_debug #(
.store_q_m (store_q_m),
.sign_extend_x (sign_extend_x),
.size_x (size_x),
-
-
- .dflush (dflush_m),
+ .dflush (dflush_m),
-
+
-
.d_dat_i (D_DAT_I),
.d_ack_i (D_ACK_I),
@@ -15699,21 +14158,18 @@ lm32_load_store_unit_full_debug #(
.d_rty_i (D_RTY_I),
-
-
+
.dcache_refill_request (dcache_refill_request),
.dcache_restart_request (dcache_restart_request),
.dcache_stall_request (dcache_stall_request),
.dcache_refilling (dcache_refilling),
-
-
+
-
.load_data_w (load_data_w),
.stall_wb_load (stall_wb_load),
@@ -15752,8 +14208,7 @@ lm32_logic_op logic_op (
.logic_result_x (logic_result_x)
);
-
-
+
lm32_shifter shifter (
@@ -15767,11 +14222,9 @@ lm32_shifter shifter (
.shifter_result_m (shifter_result_m)
);
-
-
-
+
lm32_multiplier multiplier (
@@ -15784,11 +14237,9 @@ lm32_multiplier multiplier (
.result (multiplier_result_w)
);
-
-
-
+
lm32_mc_arithmetic_full_debug mc_arithmetic (
@@ -15796,38 +14247,30 @@ lm32_mc_arithmetic_full_debug mc_arithmetic (
.rst_i (rst_i),
.stall_d (stall_d),
.kill_x (kill_x),
-
-
+
.divide_d (divide_q_d),
.modulus_d (modulus_q_d),
-
-
+
-
-
+
-
.operand_0_d (d_result_0),
.operand_1_d (d_result_1),
.result_x (mc_result_x),
-
-
+
.divide_by_zero_x (divide_by_zero_x),
-
.stall_request_x (mc_stall_request_x)
);
-
-
-
+
lm32_interrupt_full_debug interrupt_unit (
@@ -15837,19 +14280,15 @@ lm32_interrupt_full_debug interrupt_unit (
.interrupt (interrupt),
.stall_x (stall_x),
-
-
+
.non_debug_exception (non_debug_exception_q_w),
.debug_exception (debug_exception_q_w),
-
-
+
.eret_q_x (eret_q_x),
-
-
- .bret_q_x (bret_q_x),
+ .bret_q_x (bret_q_x),
.csr (csr_x),
.csr_write_data (operand_1_x),
@@ -15859,11 +14298,9 @@ lm32_interrupt_full_debug interrupt_unit (
.csr_read_data (interrupt_csr_read_data_x)
);
-
-
-
+
lm32_jtag_full_debug jtag (
@@ -15875,35 +14312,26 @@ lm32_jtag_full_debug jtag (
.jtag_reg_q (jtag_reg_q),
.jtag_reg_addr_q (jtag_reg_addr_q),
-
-
+
.csr (csr_x),
.csr_write_data (operand_1_x),
.csr_write_enable (csr_write_enable_q_x),
.stall_x (stall_x),
-
-
-
+
.jtag_read_data (jtag_read_data),
.jtag_access_complete (jtag_access_complete),
-
-
-
- .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
+ .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
-
-
+
.jtx_csr_read_data (jtx_csr_read_data),
.jrx_csr_read_data (jrx_csr_read_data),
-
-
-
+
.jtag_csr_write_enable (jtag_csr_write_enable),
.jtag_csr_write_data (jtag_csr_write_data),
.jtag_csr (jtag_csr),
@@ -15911,23 +14339,18 @@ lm32_jtag_full_debug jtag (
.jtag_write_enable (jtag_write_enable),
.jtag_write_data (jtag_write_data),
.jtag_address (jtag_address),
-
-
-
+
.jtag_break (jtag_break),
.jtag_reset (reset_exception),
-
.jtag_reg_d (jtag_reg_d),
.jtag_reg_addr_d (jtag_reg_addr_d)
);
-
-
-
+
lm32_debug_full_debug #(
.breakpoints (breakpoints),
@@ -15943,44 +14366,34 @@ lm32_debug_full_debug #(
.csr_write_enable_x (csr_write_enable_q_x),
.csr_write_data (operand_1_x),
.csr_x (csr_x),
-
-
+
.jtag_csr_write_enable (jtag_csr_write_enable),
.jtag_csr_write_data (jtag_csr_write_data),
.jtag_csr (jtag_csr),
-
-
-
+
.eret_q_x (eret_q_x),
.bret_q_x (bret_q_x),
.stall_x (stall_x),
.exception_x (exception_x),
.q_x (q_x),
-
-
- .dcache_refill_request (dcache_refill_request),
+ .dcache_refill_request (dcache_refill_request),
-
-
-
- .dc_ss (dc_ss),
+ .dc_ss (dc_ss),
.dc_re (dc_re),
.bp_match (bp_match),
.wp_match (wp_match)
);
-
-
-
+
@@ -16041,8 +14454,8 @@ lm32_debug_full_debug #(
- always @(posedge clk_i )
- if (rst_i == 1'b1)
+ always @(posedge clk_i )
+ if (rst_i == 1'b1)
begin
regfile_raw_0 <= 1'b0;
regfile_raw_1 <= 1'b0;
@@ -16097,10 +14510,9 @@ lm32_debug_full_debug #(
.rdata_o (regfile_data_1)
);
-
-
+
@@ -16173,58 +14585,53 @@ lm32_debug_full_debug #(
-
-
-
+
assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
-
-
-
+
-
-assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == 1'b1);
-assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == 1'b1);
-assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == 1'b1);
-assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == 1'b1);
-assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == 1'b1);
-assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == 1'b1);
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == 1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == 1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == 1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == 1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == 1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == 1'b1);
always @(*)
begin
- if ( ( (x_bypass_enable_x == 1'b0)
- && ( ((read_enable_0_d == 1'b1) && (raw_x_0 == 1'b1))
- || ((read_enable_1_d == 1'b1) && (raw_x_1 == 1'b1))
+ if ( ( (x_bypass_enable_x == 1'b0)
+ && ( ((read_enable_0_d == 1'b1) && (raw_x_0 == 1'b1))
+ || ((read_enable_1_d == 1'b1) && (raw_x_1 == 1'b1))
)
)
- || ( (m_bypass_enable_m == 1'b0)
- && ( ((read_enable_0_d == 1'b1) && (raw_m_0 == 1'b1))
- || ((read_enable_1_d == 1'b1) && (raw_m_1 == 1'b1))
+ || ( (m_bypass_enable_m == 1'b0)
+ && ( ((read_enable_0_d == 1'b1) && (raw_m_0 == 1'b1))
+ || ((read_enable_1_d == 1'b1) && (raw_m_1 == 1'b1))
)
)
)
- interlock = 1'b1;
+ interlock = 1'b1;
else
- interlock = 1'b0;
+ interlock = 1'b0;
end
always @(*)
begin
- if (raw_x_0 == 1'b1)
+ if (raw_x_0 == 1'b1)
bypass_data_0 = x_result;
- else if (raw_m_0 == 1'b1)
+ else if (raw_m_0 == 1'b1)
bypass_data_0 = m_result;
- else if (raw_w_0 == 1'b1)
+ else if (raw_w_0 == 1'b1)
bypass_data_0 = w_result;
else
bypass_data_0 = reg_data_0;
@@ -16233,11 +14640,11 @@ end
always @(*)
begin
- if (raw_x_1 == 1'b1)
+ if (raw_x_1 == 1'b1)
bypass_data_1 = x_result;
- else if (raw_m_1 == 1'b1)
+ else if (raw_m_1 == 1'b1)
bypass_data_1 = m_result;
- else if (raw_w_1 == 1'b1)
+ else if (raw_w_1 == 1'b1)
bypass_data_1 = w_result;
else
bypass_data_1 = reg_data_1;
@@ -16265,51 +14672,47 @@ always @(*)
begin
d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
case (d_result_sel_1_d)
- 2'b00: d_result_1 = { 32{1'b0}};
- 2'b01: d_result_1 = bypass_data_1;
- 2'b10: d_result_1 = immediate_d;
- default: d_result_1 = { 32{1'bx}};
+ 2'b00: d_result_1 = {32{1'b0}};
+ 2'b01: d_result_1 = bypass_data_1;
+ 2'b10: d_result_1 = immediate_d;
+ default: d_result_1 = {32{1'bx}};
endcase
end
-
+
-
-
-
+
assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
-assign sext_result_x = size_x == 2'b00 ? sextb_result_x : sexth_result_x;
-
+assign sext_result_x = size_x == 2'b00 ? sextb_result_x : sexth_result_x;
-
+
-
assign cmp_zero = operand_0_x == operand_1_x;
-assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_negative = adder_result_x[32-1];
assign cmp_overflow = adder_overflow_x;
assign cmp_carry_n = adder_carry_n_x;
always @(*)
begin
case (condition_x)
- 3'b000: condition_met_x = 1'b1;
- 3'b110: condition_met_x = 1'b1;
- 3'b001: condition_met_x = cmp_zero;
- 3'b111: condition_met_x = !cmp_zero;
- 3'b010: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
- 3'b101: condition_met_x = cmp_carry_n && !cmp_zero;
- 3'b011: condition_met_x = cmp_negative == cmp_overflow;
- 3'b100: condition_met_x = cmp_carry_n;
+ 3'b000: condition_met_x = 1'b1;
+ 3'b110: condition_met_x = 1'b1;
+ 3'b001: condition_met_x = cmp_zero;
+ 3'b111: condition_met_x = !cmp_zero;
+ 3'b010: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+ 3'b101: condition_met_x = cmp_carry_n && !cmp_zero;
+ 3'b011: condition_met_x = cmp_negative == cmp_overflow;
+ 3'b100: condition_met_x = cmp_carry_n;
default: condition_met_x = 1'bx;
endcase
end
@@ -16319,23 +14722,17 @@ always @(*)
begin
x_result = x_result_sel_add_x ? adder_result_x
: x_result_sel_csr_x ? csr_read_data_x
-
-
- : x_result_sel_sext_x ? sext_result_x
+ : x_result_sel_sext_x ? sext_result_x
-
+
-
-
+
-
-
-
- : x_result_sel_mc_arith_x ? mc_result_x
+ : x_result_sel_mc_arith_x ? mc_result_x
: logic_result_x;
end
@@ -16343,11 +14740,9 @@ end
always @(*)
begin
- m_result = m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
-
-
- : m_result_sel_shift_m ? shifter_result_m
+ m_result = m_result_sel_compare_m ? {{32-1{1'b0}}, condition_met_m}
+ : m_result_sel_shift_m ? shifter_result_m
: operand_m;
end
@@ -16356,212 +14751,165 @@ end
always @(*)
begin
w_result = w_result_sel_load_w ? load_data_w
-
-
- : w_result_sel_mul_w ? multiplier_result_w
+ : w_result_sel_mul_w ? multiplier_result_w
: operand_w;
end
-
-
+
-assign branch_taken_x = (stall_x == 1'b0)
- && ( (branch_x == 1'b1)
- && ((condition_x == 3'b000) || (condition_x == 3'b110))
- && (valid_x == 1'b1)
- && (branch_predict_x == 1'b0)
+assign branch_taken_x = (stall_x == 1'b0)
+ && ( (branch_x == 1'b1)
+ && ((condition_x == 3'b000) || (condition_x == 3'b110))
+ && (valid_x == 1'b1)
+ && (branch_predict_x == 1'b0)
);
-
-assign branch_taken_m = (stall_m == 1'b0)
- && ( ( (branch_m == 1'b1)
- && (valid_m == 1'b1)
- && ( ( (condition_met_m == 1'b1)
- && (branch_predict_taken_m == 1'b0)
+assign branch_taken_m = (stall_m == 1'b0)
+ && ( ( (branch_m == 1'b1)
+ && (valid_m == 1'b1)
+ && ( ( (condition_met_m == 1'b1)
+ && (branch_predict_taken_m == 1'b0)
)
- || ( (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1)
+ || ( (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1)
)
)
)
- || (exception_m == 1'b1)
+ || (exception_m == 1'b1)
);
-assign branch_mispredict_taken_m = (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1);
+assign branch_mispredict_taken_m = (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1);
-assign branch_flushX_m = (stall_m == 1'b0)
- && ( ( (branch_m == 1'b1)
- && (valid_m == 1'b1)
- && ( (condition_met_m == 1'b1)
- || ( (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1)
+assign branch_flushX_m = (stall_m == 1'b0)
+ && ( ( (branch_m == 1'b1)
+ && (valid_m == 1'b1)
+ && ( (condition_met_m == 1'b1)
+ || ( (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1)
)
)
)
- || (exception_m == 1'b1)
+ || (exception_m == 1'b1)
);
-assign kill_f = ( (valid_d == 1'b1)
- && (branch_predict_taken_d == 1'b1)
+assign kill_f = ( (valid_d == 1'b1)
+ && (branch_predict_taken_d == 1'b1)
)
- || (branch_taken_m == 1'b1)
-
-
- || (branch_taken_x == 1'b1)
-
-
-
+ || (branch_taken_m == 1'b1)
+
+ || (branch_taken_x == 1'b1)
- || (icache_refill_request == 1'b1)
+ || (icache_refill_request == 1'b1)
-
-
- || (dcache_refill_request == 1'b1)
-
+
+ || (dcache_refill_request == 1'b1)
;
-assign kill_d = (branch_taken_m == 1'b1)
-
-
- || (branch_taken_x == 1'b1)
-
-
-
+assign kill_d = (branch_taken_m == 1'b1)
+
+ || (branch_taken_x == 1'b1)
- || (icache_refill_request == 1'b1)
+ || (icache_refill_request == 1'b1)
-
-
- || (dcache_refill_request == 1'b1)
-
+
+ || (dcache_refill_request == 1'b1)
;
-assign kill_x = (branch_flushX_m == 1'b1)
-
-
- || (dcache_refill_request == 1'b1)
-
+assign kill_x = (branch_flushX_m == 1'b1)
+
+ || (dcache_refill_request == 1'b1)
;
-assign kill_m = 1'b0
-
-
- || (dcache_refill_request == 1'b1)
-
+assign kill_m = 1'b0
+
+ || (dcache_refill_request == 1'b1)
;
-assign kill_w = 1'b0
-
-
- || (dcache_refill_request == 1'b1)
-
+assign kill_w = 1'b0
+
+ || (dcache_refill_request == 1'b1)
;
-
-
-assign breakpoint_exception = ( ( (break_x == 1'b1)
- || (bp_match == 1'b1)
+
+assign breakpoint_exception = ( ( (break_x == 1'b1)
+ || (bp_match == 1'b1)
)
- && (valid_x == 1'b1)
+ && (valid_x == 1'b1)
)
-
-
- || (jtag_break == 1'b1)
+ || (jtag_break == 1'b1)
;
-
-
-
-assign watchpoint_exception = wp_match == 1'b1;
+assign watchpoint_exception = wp_match == 1'b1;
-
-
-assign instruction_bus_error_exception = ( (bus_error_x == 1'b1)
- && (valid_x == 1'b1)
- );
-assign data_bus_error_exception = data_bus_error_seen == 1'b1;
+assign instruction_bus_error_exception = ( (bus_error_x == 1'b1)
+ && (valid_x == 1'b1)
+ );
+assign data_bus_error_exception = data_bus_error_seen == 1'b1;
-
-
-assign divide_by_zero_exception = divide_by_zero_x == 1'b1;
+assign divide_by_zero_exception = divide_by_zero_x == 1'b1;
-assign system_call_exception = ( (scall_x == 1'b1)
-
-
- && (valid_x == 1'b1)
+assign system_call_exception = ( (scall_x == 1'b1)
+ && (valid_x == 1'b1)
);
-
-
-assign debug_exception_x = (breakpoint_exception == 1'b1)
- || (watchpoint_exception == 1'b1)
+
+assign debug_exception_x = (breakpoint_exception == 1'b1)
+ || (watchpoint_exception == 1'b1)
;
-assign non_debug_exception_x = (system_call_exception == 1'b1)
-
-
- || (reset_exception == 1'b1)
+assign non_debug_exception_x = (system_call_exception == 1'b1)
+ || (reset_exception == 1'b1)
-
-
- || (instruction_bus_error_exception == 1'b1)
- || (data_bus_error_exception == 1'b1)
+ || (instruction_bus_error_exception == 1'b1)
+ || (data_bus_error_exception == 1'b1)
-
-
- || (divide_by_zero_exception == 1'b1)
+ || (divide_by_zero_exception == 1'b1)
-
-
- || ( (interrupt_exception == 1'b1)
-
-
- && (dc_ss == 1'b0)
+ || ( (interrupt_exception == 1'b1)
+
+ && (dc_ss == 1'b0)
-
-
- && (store_q_m == 1'b0)
- && (D_CYC_O == 1'b0)
+ && (store_q_m == 1'b0)
+ && (D_CYC_O == 1'b0)
)
-
;
-assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1);
-
+assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1);
+
@@ -16583,127 +14931,104 @@ assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x ==
-
always @(*)
begin
-
-
-
-
- if (reset_exception == 1'b1)
- eid_x = 3'h0;
- else
-
-
-
- if (data_bus_error_exception == 1'b1)
- eid_x = 3'h4;
- else
-
- if (breakpoint_exception == 1'b1)
- eid_x = 3'd1;
+ if (reset_exception == 1'b1)
+ eid_x = 3'h0;
else
+
+ if (data_bus_error_exception == 1'b1)
+ eid_x = 3'h4;
+ else
-
+ if (breakpoint_exception == 1'b1)
+ eid_x = 3'd1;
+ else
- if (data_bus_error_exception == 1'b1)
- eid_x = 3'h4;
+
+ if (data_bus_error_exception == 1'b1)
+ eid_x = 3'h4;
else
- if (instruction_bus_error_exception == 1'b1)
- eid_x = 3'h2;
+ if (instruction_bus_error_exception == 1'b1)
+ eid_x = 3'h2;
else
-
-
-
- if (watchpoint_exception == 1'b1)
- eid_x = 3'd3;
- else
+ if (watchpoint_exception == 1'b1)
+ eid_x = 3'd3;
+ else
-
-
- if (divide_by_zero_exception == 1'b1)
- eid_x = 3'h5;
- else
+ if (divide_by_zero_exception == 1'b1)
+ eid_x = 3'h5;
+ else
-
-
- if ( (interrupt_exception == 1'b1)
-
-
- && (dc_ss == 1'b0)
+ if ( (interrupt_exception == 1'b1)
+
+ && (dc_ss == 1'b0)
)
- eid_x = 3'h6;
+ eid_x = 3'h6;
else
-
- eid_x = 3'h7;
+ eid_x = 3'h7;
end
-assign stall_a = (stall_f == 1'b1);
+assign stall_a = (stall_f == 1'b1);
-assign stall_f = (stall_d == 1'b1);
+assign stall_f = (stall_d == 1'b1);
-assign stall_d = (stall_x == 1'b1)
- || ( (interlock == 1'b1)
- && (kill_d == 1'b0)
+assign stall_d = (stall_x == 1'b1)
+ || ( (interlock == 1'b1)
+ && (kill_d == 1'b0)
)
- || ( ( (eret_d == 1'b1)
- || (scall_d == 1'b1)
-
-
- || (bus_error_d == 1'b1)
+ || ( ( (eret_d == 1'b1)
+ || (scall_d == 1'b1)
+ || (bus_error_d == 1'b1)
)
- && ( (load_q_x == 1'b1)
- || (load_q_m == 1'b1)
- || (store_q_x == 1'b1)
- || (store_q_m == 1'b1)
- || (D_CYC_O == 1'b1)
+ && ( (load_q_x == 1'b1)
+ || (load_q_m == 1'b1)
+ || (store_q_x == 1'b1)
+ || (store_q_m == 1'b1)
+ || (D_CYC_O == 1'b1)
)
- && (kill_d == 1'b0)
+ && (kill_d == 1'b0)
)
-
-
- || ( ( (break_d == 1'b1)
- || (bret_d == 1'b1)
+
+ || ( ( (break_d == 1'b1)
+ || (bret_d == 1'b1)
)
- && ( (load_q_x == 1'b1)
- || (store_q_x == 1'b1)
- || (load_q_m == 1'b1)
- || (store_q_m == 1'b1)
- || (D_CYC_O == 1'b1)
+ && ( (load_q_x == 1'b1)
+ || (store_q_x == 1'b1)
+ || (load_q_m == 1'b1)
+ || (store_q_m == 1'b1)
+ || (D_CYC_O == 1'b1)
)
- && (kill_d == 1'b0)
+ && (kill_d == 1'b0)
)
-
- || ( (csr_write_enable_d == 1'b1)
- && (load_q_x == 1'b1)
+ || ( (csr_write_enable_d == 1'b1)
+ && (load_q_x == 1'b1)
)
;
-assign stall_x = (stall_m == 1'b1)
-
-
- || ( (mc_stall_request_x == 1'b1)
- && (kill_x == 1'b0)
- )
+assign stall_x = (stall_m == 1'b1)
+ || ( (mc_stall_request_x == 1'b1)
+ && (kill_x == 1'b0)
+ )
-
+
@@ -16712,16 +15037,14 @@ assign stall_x = (stall_m == 1'b1)
-
;
-assign stall_m = (stall_wb_load == 1'b1)
-
+assign stall_m = (stall_wb_load == 1'b1)
+
-
- || ( (D_CYC_O == 1'b1)
- && ( (store_m == 1'b1)
+ || ( (D_CYC_O == 1'b1)
+ && ( (store_m == 1'b1)
@@ -16735,286 +15058,220 @@ assign stall_m = (stall_wb_load == 1'b1)
-
-
- || ((store_x == 1'b1) && (interrupt_exception == 1'b1))
+ || ((store_x == 1'b1) && (interrupt_exception == 1'b1))
- || (load_m == 1'b1)
- || (load_x == 1'b1)
+ || (load_m == 1'b1)
+ || (load_x == 1'b1)
)
)
-
-
-
- || (dcache_stall_request == 1'b1)
+ || (dcache_stall_request == 1'b1)
-
-
- || (icache_stall_request == 1'b1)
- || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1)))
+ || (icache_stall_request == 1'b1)
+ || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1)))
+
-
-
+
-
;
-
-
-assign q_d = (valid_d == 1'b1) && (kill_d == 1'b0);
+assign q_d = (valid_d == 1'b1) && (kill_d == 1'b0);
-
+
-
-
+
-
-
-
-assign divide_q_d = (divide_d == 1'b1) && (q_d == 1'b1);
-assign modulus_q_d = (modulus_d == 1'b1) && (q_d == 1'b1);
+assign divide_q_d = (divide_d == 1'b1) && (q_d == 1'b1);
+assign modulus_q_d = (modulus_d == 1'b1) && (q_d == 1'b1);
-assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
-assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
-assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
-
-
-assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1);
+assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
+assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
+assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1);
-assign load_q_x = (load_x == 1'b1)
- && (q_x == 1'b1)
-
-
- && (bp_match == 1'b0)
+assign load_q_x = (load_x == 1'b1)
+ && (q_x == 1'b1)
+ && (bp_match == 1'b0)
;
-assign store_q_x = (store_x == 1'b1)
- && (q_x == 1'b1)
-
-
- && (bp_match == 1'b0)
+assign store_q_x = (store_x == 1'b1)
+ && (q_x == 1'b1)
+ && (bp_match == 1'b0)
;
-
+
-
-assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
-assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
-assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
-
-assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1));
-assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1));
+assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
+assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
+assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
+assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1));
+assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1));
+
-assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
-assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
-assign write_enable_q_w = (write_enable_w == 1'b1) && (valid_w == 1'b1);
+assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
+assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
+assign write_enable_q_w = (write_enable_w == 1'b1) && (valid_w == 1'b1);
-assign reg_write_enable_q_w = (write_enable_w == 1'b1) && (kill_w == 1'b0) && (valid_w == 1'b1);
+assign reg_write_enable_q_w = (write_enable_w == 1'b1) && (kill_w == 1'b0) && (valid_w == 1'b1);
assign cfg = {
- 6'h02,
+ 6'h02,
watchpoints[3:0],
breakpoints[3:0],
interrupts[5:0],
-
-
- 1'b1,
-
-
+ 1'b1,
-
-
- 1'b0,
-
-
-
-
- 1'b1,
+ 1'b0,
-
-
- 1'b1,
-
-
+ 1'b1,
-
-
- 1'b1,
-
-
-
-
- 1'b1,
+ 1'b1,
+
+
+ 1'b1,
-
-
- 1'b0,
+ 1'b1,
-
-
- 1'b0,
+
-
+ 1'b0,
- 1'b1,
+ 1'b0,
-
-
- 1'b1,
+ 1'b1,
+
+
+ 1'b1,
-
+
- 1'b1,
-
+ 1'b1,
+
-
- 1'b1
-
-
+ 1'b1
+
};
assign cfg2 = {
30'b0,
-
+
+ 1'b0,
- 1'b0,
-
-
-
- 1'b0
-
+ 1'b0
};
-
-
-assign iflush = ( (csr_write_enable_d == 1'b1)
- && (csr_d == 5'h3)
- && (stall_d == 1'b0)
- && (kill_d == 1'b0)
- && (valid_d == 1'b1))
-
-
+
+assign iflush = ( (csr_write_enable_d == 1'b1)
+ && (csr_d == 5'h3)
+ && (stall_d == 1'b0)
+ && (kill_d == 1'b0)
+ && (valid_d == 1'b1))
- ||
- ( (jtag_csr_write_enable == 1'b1)
- && (jtag_csr == 5'h3))
+ ||
+ ( (jtag_csr_write_enable == 1'b1)
+ && (jtag_csr == 5'h3))
;
-
+assign dflush_x = ( (csr_write_enable_q_x == 1'b1)
+ && (csr_x == 5'h4))
-assign dflush_x = ( (csr_write_enable_q_x == 1'b1)
- && (csr_x == 5'h4))
-
-
-
- ||
- ( (jtag_csr_write_enable == 1'b1)
- && (jtag_csr == 5'h4))
+ ||
+ ( (jtag_csr_write_enable == 1'b1)
+ && (jtag_csr == 5'h4))
;
-
-assign csr_d = read_idx_0_d[ (5-1):0];
+assign csr_d = read_idx_0_d[(5-1):0];
always @(*)
begin
case (csr_x)
-
-
- 5'h0,
- 5'h1,
- 5'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 5'h0,
+ 5'h1,
+ 5'h2: csr_read_data_x = interrupt_csr_read_data_x;
-
+
-
- 5'h6: csr_read_data_x = cfg;
- 5'h7: csr_read_data_x = {eba, 8'h00};
-
-
- 5'h9: csr_read_data_x = {deba, 8'h00};
+ 5'h6: csr_read_data_x = cfg;
+ 5'h7: csr_read_data_x = {eba, 8'h00};
+ 5'h9: csr_read_data_x = {deba, 8'h00};
-
-
- 5'he: csr_read_data_x = jtx_csr_read_data;
- 5'hf: csr_read_data_x = jrx_csr_read_data;
+ 5'he: csr_read_data_x = jtx_csr_read_data;
+ 5'hf: csr_read_data_x = jrx_csr_read_data;
- 5'ha: csr_read_data_x = cfg2;
+ 5'ha: csr_read_data_x = cfg2;
- default: csr_read_data_x = { 32{1'bx}};
+ default: csr_read_data_x = {32{1'bx}};
endcase
end
@@ -17023,47 +15280,41 @@ end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if (rst_i == 1'b1)
+ eba <= eba_reset[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0))
- eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
-
- if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7))
- eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0))
+ eba <= operand_1_x[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7))
+ eba <= jtag_csr_write_data[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if (rst_i == 1'b1)
+ deba <= deba_reset[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0))
- deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
-
- if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9))
- deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0))
+ deba <= operand_1_x[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9))
+ deba <= jtag_csr_write_data[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
end
end
-
-
+
@@ -17073,47 +15324,42 @@ end
+
-
-
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- data_bus_error_seen <= 1'b0;
+ if (rst_i == 1'b1)
+ data_bus_error_seen <= 1'b0;
else
begin
- if ((D_ERR_I == 1'b1) && (D_CYC_O == 1'b1))
- data_bus_error_seen <= 1'b1;
+ if ((D_ERR_I == 1'b1) && (D_CYC_O == 1'b1))
+ data_bus_error_seen <= 1'b1;
- if ((exception_m == 1'b1) && (kill_m == 1'b0))
- data_bus_error_seen <= 1'b0;
+ if ((exception_m == 1'b1) && (kill_m == 1'b0))
+ data_bus_error_seen <= 1'b0;
end
end
-
-
-
-
-
+
+
always @(*)
begin
- if ( (icache_refill_request == 1'b1)
- || (dcache_refill_request == 1'b1)
+ if ( (icache_refill_request == 1'b1)
+ || (dcache_refill_request == 1'b1)
)
- valid_a = 1'b0;
- else if ( (icache_restart_request == 1'b1)
- || (dcache_restart_request == 1'b1)
+ valid_a = 1'b0;
+ else if ( (icache_restart_request == 1'b1)
+ || (dcache_restart_request == 1'b1)
)
- valid_a = 1'b1;
+ valid_a = 1'b1;
else
valid_a = !icache_refilling && !dcache_refilling;
end
-
+
@@ -17127,7 +15373,6 @@ end
-
@@ -17139,258 +15384,208 @@ end
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- valid_f <= 1'b0;
- valid_d <= 1'b0;
- valid_x <= 1'b0;
- valid_m <= 1'b0;
- valid_w <= 1'b0;
+ valid_f <= 1'b0;
+ valid_d <= 1'b0;
+ valid_x <= 1'b0;
+ valid_m <= 1'b0;
+ valid_w <= 1'b0;
end
else
begin
- if ((kill_f == 1'b1) || (stall_a == 1'b0))
-
-
- valid_f <= valid_a;
+ if ((kill_f == 1'b1) || (stall_a == 1'b0))
-
+ valid_f <= valid_a;
+
- else if (stall_f == 1'b0)
- valid_f <= 1'b0;
+ else if (stall_f == 1'b0)
+ valid_f <= 1'b0;
- if (kill_d == 1'b1)
- valid_d <= 1'b0;
- else if (stall_f == 1'b0)
+ if (kill_d == 1'b1)
+ valid_d <= 1'b0;
+ else if (stall_f == 1'b0)
valid_d <= valid_f & !kill_f;
- else if (stall_d == 1'b0)
- valid_d <= 1'b0;
+ else if (stall_d == 1'b0)
+ valid_d <= 1'b0;
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
valid_x <= valid_d & !kill_d;
- else if (kill_x == 1'b1)
- valid_x <= 1'b0;
- else if (stall_x == 1'b0)
- valid_x <= 1'b0;
-
- if (kill_m == 1'b1)
- valid_m <= 1'b0;
- else if (stall_x == 1'b0)
+ else if (kill_x == 1'b1)
+ valid_x <= 1'b0;
+ else if (stall_x == 1'b0)
+ valid_x <= 1'b0;
+
+ if (kill_m == 1'b1)
+ valid_m <= 1'b0;
+ else if (stall_x == 1'b0)
valid_m <= valid_x & !kill_x;
- else if (stall_m == 1'b0)
- valid_m <= 1'b0;
+ else if (stall_m == 1'b0)
+ valid_m <= 1'b0;
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
valid_w <= valid_m & !kill_m;
else
- valid_w <= 1'b0;
+ valid_w <= 1'b0;
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
-
+
-
- operand_0_x <= { 32{1'b0}};
- operand_1_x <= { 32{1'b0}};
- store_operand_x <= { 32{1'b0}};
- branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- x_result_sel_csr_x <= 1'b0;
-
-
- x_result_sel_mc_arith_x <= 1'b0;
+ operand_0_x <= {32{1'b0}};
+ operand_1_x <= {32{1'b0}};
+ store_operand_x <= {32{1'b0}};
+ branch_target_x <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ x_result_sel_csr_x <= 1'b0;
+ x_result_sel_mc_arith_x <= 1'b0;
-
+
-
-
-
- x_result_sel_sext_x <= 1'b0;
+ x_result_sel_sext_x <= 1'b0;
- x_result_sel_logic_x <= 1'b0;
-
+ x_result_sel_logic_x <= 1'b0;
+
-
- x_result_sel_add_x <= 1'b0;
- m_result_sel_compare_x <= 1'b0;
-
-
- m_result_sel_shift_x <= 1'b0;
+ x_result_sel_add_x <= 1'b0;
+ m_result_sel_compare_x <= 1'b0;
+ m_result_sel_shift_x <= 1'b0;
- w_result_sel_load_x <= 1'b0;
-
-
- w_result_sel_mul_x <= 1'b0;
+ w_result_sel_load_x <= 1'b0;
+ w_result_sel_mul_x <= 1'b0;
- x_bypass_enable_x <= 1'b0;
- m_bypass_enable_x <= 1'b0;
- write_enable_x <= 1'b0;
- write_idx_x <= { 5{1'b0}};
- csr_x <= { 5{1'b0}};
- load_x <= 1'b0;
- store_x <= 1'b0;
- size_x <= { 2{1'b0}};
- sign_extend_x <= 1'b0;
- adder_op_x <= 1'b0;
- adder_op_x_n <= 1'b0;
+ x_bypass_enable_x <= 1'b0;
+ m_bypass_enable_x <= 1'b0;
+ write_enable_x <= 1'b0;
+ write_idx_x <= {5{1'b0}};
+ csr_x <= {5{1'b0}};
+ load_x <= 1'b0;
+ store_x <= 1'b0;
+ size_x <= {2{1'b0}};
+ sign_extend_x <= 1'b0;
+ adder_op_x <= 1'b0;
+ adder_op_x_n <= 1'b0;
logic_op_x <= 4'h0;
-
-
- direction_x <= 1'b0;
+ direction_x <= 1'b0;
-
+
-
- branch_x <= 1'b0;
- branch_predict_x <= 1'b0;
- branch_predict_taken_x <= 1'b0;
- condition_x <= 3'b000;
-
-
- break_x <= 1'b0;
+ branch_x <= 1'b0;
+ branch_predict_x <= 1'b0;
+ branch_predict_taken_x <= 1'b0;
+ condition_x <= 3'b000;
+ break_x <= 1'b0;
- scall_x <= 1'b0;
- eret_x <= 1'b0;
-
-
- bret_x <= 1'b0;
+ scall_x <= 1'b0;
+ eret_x <= 1'b0;
+ bret_x <= 1'b0;
-
-
- bus_error_x <= 1'b0;
- data_bus_error_exception_m <= 1'b0;
+ bus_error_x <= 1'b0;
+ data_bus_error_exception_m <= 1'b0;
- csr_write_enable_x <= 1'b0;
- operand_m <= { 32{1'b0}};
- branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- m_result_sel_compare_m <= 1'b0;
-
-
- m_result_sel_shift_m <= 1'b0;
+ csr_write_enable_x <= 1'b0;
+ operand_m <= {32{1'b0}};
+ branch_target_m <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ m_result_sel_compare_m <= 1'b0;
+ m_result_sel_shift_m <= 1'b0;
- w_result_sel_load_m <= 1'b0;
-
-
- w_result_sel_mul_m <= 1'b0;
+ w_result_sel_load_m <= 1'b0;
+ w_result_sel_mul_m <= 1'b0;
- m_bypass_enable_m <= 1'b0;
- branch_m <= 1'b0;
- branch_predict_m <= 1'b0;
- branch_predict_taken_m <= 1'b0;
- exception_m <= 1'b0;
- load_m <= 1'b0;
- store_m <= 1'b0;
-
-
- direction_m <= 1'b0;
+ m_bypass_enable_m <= 1'b0;
+ branch_m <= 1'b0;
+ branch_predict_m <= 1'b0;
+ branch_predict_taken_m <= 1'b0;
+ exception_m <= 1'b0;
+ load_m <= 1'b0;
+ store_m <= 1'b0;
+ direction_m <= 1'b0;
- write_enable_m <= 1'b0;
- write_idx_m <= { 5{1'b0}};
- condition_met_m <= 1'b0;
-
-
- dflush_m <= 1'b0;
+ write_enable_m <= 1'b0;
+ write_idx_m <= {5{1'b0}};
+ condition_met_m <= 1'b0;
+ dflush_m <= 1'b0;
-
-
- debug_exception_m <= 1'b0;
- non_debug_exception_m <= 1'b0;
+ debug_exception_m <= 1'b0;
+ non_debug_exception_m <= 1'b0;
- operand_w <= { 32{1'b0}};
- w_result_sel_load_w <= 1'b0;
-
-
- w_result_sel_mul_w <= 1'b0;
+ operand_w <= {32{1'b0}};
+ w_result_sel_load_w <= 1'b0;
+ w_result_sel_mul_w <= 1'b0;
- write_idx_w <= { 5{1'b0}};
- write_enable_w <= 1'b0;
-
-
- debug_exception_w <= 1'b0;
- non_debug_exception_w <= 1'b0;
+ write_idx_w <= {5{1'b0}};
+ write_enable_w <= 1'b0;
-
-
+ debug_exception_w <= 1'b0;
+ non_debug_exception_w <= 1'b0;
-
+
- memop_pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ memop_pc_w <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
end
else
begin
- if (stall_x == 1'b0)
+ if (stall_x == 1'b0)
begin
-
+
-
operand_0_x <= d_result_0;
operand_1_x <= d_result_1;
store_operand_x <= bypass_data_1;
- branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;
+ branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;
x_result_sel_csr_x <= x_result_sel_csr_d;
-
-
- x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
+ x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
-
+
-
-
-
- x_result_sel_sext_x <= x_result_sel_sext_d;
+ x_result_sel_sext_x <= x_result_sel_sext_d;
x_result_sel_logic_x <= x_result_sel_logic_d;
-
+
-
x_result_sel_add_x <= x_result_sel_add_d;
m_result_sel_compare_x <= m_result_sel_compare_d;
-
-
- m_result_sel_shift_x <= m_result_sel_shift_d;
+ m_result_sel_shift_x <= m_result_sel_shift_d;
w_result_sel_load_x <= w_result_sel_load_d;
-
-
- w_result_sel_mul_x <= w_result_sel_mul_d;
+ w_result_sel_mul_x <= w_result_sel_mul_d;
x_bypass_enable_x <= x_bypass_enable_d;
m_bypass_enable_x <= m_bypass_enable_d;
@@ -17406,231 +15601,187 @@ begin
adder_op_x <= adder_op_d;
adder_op_x_n <= ~adder_op_d;
logic_op_x <= logic_op_d;
-
-
- direction_x <= direction_d;
+ direction_x <= direction_d;
-
+
-
condition_x <= condition_d;
csr_write_enable_x <= csr_write_enable_d;
-
-
- break_x <= break_d;
+ break_x <= break_d;
scall_x <= scall_d;
-
-
- bus_error_x <= bus_error_d;
+ bus_error_x <= bus_error_d;
eret_x <= eret_d;
-
-
- bret_x <= bret_d;
+ bret_x <= bret_d;
write_enable_x <= write_enable_d;
end
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
operand_m <= x_result;
m_result_sel_compare_m <= m_result_sel_compare_x;
-
-
- m_result_sel_shift_m <= m_result_sel_shift_x;
+ m_result_sel_shift_m <= m_result_sel_shift_x;
- if (exception_x == 1'b1)
+ if (exception_x == 1'b1)
begin
- w_result_sel_load_m <= 1'b0;
-
-
- w_result_sel_mul_m <= 1'b0;
+ w_result_sel_load_m <= 1'b0;
+ w_result_sel_mul_m <= 1'b0;
end
else
begin
w_result_sel_load_m <= w_result_sel_load_x;
-
-
- w_result_sel_mul_m <= w_result_sel_mul_x;
+ w_result_sel_mul_m <= w_result_sel_mul_x;
end
m_bypass_enable_m <= m_bypass_enable_x;
-
-
- direction_m <= direction_x;
+ direction_m <= direction_x;
load_m <= load_x;
store_m <= store_x;
-
-
+
branch_m <= branch_x && !branch_taken_x;
-
+
-
-
-
+
- if (non_debug_exception_x == 1'b1)
- write_idx_m <= 5'd30;
- else if (debug_exception_x == 1'b1)
- write_idx_m <= 5'd31;
+ if (non_debug_exception_x == 1'b1)
+ write_idx_m <= 5'd30;
+ else if (debug_exception_x == 1'b1)
+ write_idx_m <= 5'd31;
else
write_idx_m <= write_idx_x;
-
+
-
condition_met_m <= condition_met_x;
-
-
- if (exception_x == 1'b1)
- if ((dc_re == 1'b1)
- || ((debug_exception_x == 1'b1)
- && (non_debug_exception_x == 1'b0)))
+
+ if (exception_x == 1'b1)
+ if ((dc_re == 1'b1)
+ || ((debug_exception_x == 1'b1)
+ && (non_debug_exception_x == 1'b0)))
branch_target_m <= {deba, eid_x, {3{1'b0}}};
else
branch_target_m <= {eba, eid_x, {3{1'b0}}};
else
branch_target_m <= branch_target_x;
-
-
+
-
+
-
-
-
- dflush_m <= dflush_x;
+ dflush_m <= dflush_x;
eret_m <= eret_q_x;
-
-
- bret_m <= bret_q_x;
+ bret_m <= bret_q_x;
- write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
-
-
+ write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
+
debug_exception_m <= debug_exception_x;
non_debug_exception_m <= non_debug_exception_x;
-
end
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
- if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
- exception_m <= 1'b1;
+ if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
+ exception_m <= 1'b1;
else
- exception_m <= 1'b0;
-
-
- data_bus_error_exception_m <= (data_bus_error_exception == 1'b1)
-
-
- && (reset_exception == 1'b0)
+ exception_m <= 1'b0;
+
+ data_bus_error_exception_m <= (data_bus_error_exception == 1'b1)
+ && (reset_exception == 1'b0)
;
-
end
-
-
- operand_w <= exception_m == 1'b1 ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
-
+ operand_w <= exception_m == 1'b1 ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
+
w_result_sel_load_w <= w_result_sel_load_m;
-
-
- w_result_sel_mul_w <= w_result_sel_mul_m;
+ w_result_sel_mul_w <= w_result_sel_mul_m;
write_idx_w <= write_idx_m;
-
+
-
write_enable_w <= write_enable_m;
-
-
+
debug_exception_w <= debug_exception_m;
non_debug_exception_w <= non_debug_exception_m;
-
-
+
-
-
- if ( (stall_m == 1'b0)
- && ( (load_q_m == 1'b1)
- || (store_q_m == 1'b1)
+
+ if ( (stall_m == 1'b0)
+ && ( (load_q_m == 1'b1)
+ || (store_q_m == 1'b1)
)
)
memop_pc_w <= pc_m;
-
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- use_buf <= 1'b0;
- reg_data_buf_0 <= { 32{1'b0}};
- reg_data_buf_1 <= { 32{1'b0}};
+ use_buf <= 1'b0;
+ reg_data_buf_0 <= {32{1'b0}};
+ reg_data_buf_1 <= {32{1'b0}};
end
else
begin
- if (stall_d == 1'b0)
- use_buf <= 1'b0;
- else if (use_buf == 1'b0)
+ if (stall_d == 1'b0)
+ use_buf <= 1'b0;
+ else if (use_buf == 1'b0)
begin
reg_data_buf_0 <= reg_data_live_0;
reg_data_buf_1 <= reg_data_live_1;
- use_buf <= 1'b1;
+ use_buf <= 1'b1;
end
- if (reg_write_enable_q_w == 1'b1)
+ if (reg_write_enable_q_w == 1'b1)
begin
if (write_idx_w == read_idx_0_d)
reg_data_buf_0 <= w_result;
@@ -17639,13 +15790,11 @@ begin
end
end
end
-
-
-
+
@@ -17689,8 +15838,7 @@ end
-
-
+
@@ -17749,7 +15897,6 @@ end
-
@@ -17762,13 +15909,9 @@ end
initial
begin
-
-
- reg_0.ram[0] = { 32{1'b0}};
- reg_1.ram[0] = { 32{1'b0}};
-
+
end
@@ -17816,9 +15959,7 @@ endmodule
-
-
-
+
@@ -17849,9 +15990,8 @@ endmodule
-
-
+
@@ -18136,8 +16276,6 @@ endmodule
-
-
@@ -18164,15 +16302,12 @@ module lm32_load_store_unit_full_debug (
store_q_m,
sign_extend_x,
size_x,
-
-
- dflush,
+ dflush,
-
+
-
d_dat_i,
d_ack_i,
@@ -18180,20 +16315,17 @@ module lm32_load_store_unit_full_debug (
d_rty_i,
-
-
+
dcache_refill_request,
dcache_restart_request,
dcache_stall_request,
dcache_refilling,
-
-
+
-
load_data_w,
stall_wb_load,
@@ -18238,9 +16370,9 @@ input kill_x;
input kill_m;
input exception_m;
-input [ (32-1):0] store_operand_x;
-input [ (32-1):0] load_store_address_x;
-input [ (32-1):0] load_store_address_m;
+input [(32-1):0] store_operand_x;
+input [(32-1):0] load_store_address_x;
+input [(32-1):0] load_store_address_m;
input [1:0] load_store_address_w;
input load_x;
input store_x;
@@ -18249,20 +16381,17 @@ input store_q_x;
input load_q_m;
input store_q_m;
input sign_extend_x;
-input [ 1:0] size_x;
+input [1:0] size_x;
-
-
-input dflush;
+input dflush;
-
+
-
-input [ (32-1):0] d_dat_i;
+input [(32-1):0] d_dat_i;
input d_ack_i;
input d_err_i;
input d_rty_i;
@@ -18271,8 +16400,7 @@ input d_rty_i;
-
-
+
output dcache_refill_request;
wire dcache_refill_request;
output dcache_restart_request;
@@ -18281,10 +16409,9 @@ output dcache_stall_request;
wire dcache_stall_request;
output dcache_refilling;
wire dcache_refilling;
-
-
+
@@ -18294,62 +16421,59 @@ wire dcache_refilling;
-
-output [ (32-1):0] load_data_w;
-reg [ (32-1):0] load_data_w;
+output [(32-1):0] load_data_w;
+reg [(32-1):0] load_data_w;
output stall_wb_load;
reg stall_wb_load;
-output [ (32-1):0] d_dat_o;
-reg [ (32-1):0] d_dat_o;
-output [ (32-1):0] d_adr_o;
-reg [ (32-1):0] d_adr_o;
+output [(32-1):0] d_dat_o;
+reg [(32-1):0] d_dat_o;
+output [(32-1):0] d_adr_o;
+reg [(32-1):0] d_adr_o;
output d_cyc_o;
reg d_cyc_o;
-output [ (4-1):0] d_sel_o;
-reg [ (4-1):0] d_sel_o;
+output [(4-1):0] d_sel_o;
+reg [(4-1):0] d_sel_o;
output d_stb_o;
reg d_stb_o;
output d_we_o;
reg d_we_o;
-output [ (3-1):0] d_cti_o;
-reg [ (3-1):0] d_cti_o;
+output [(3-1):0] d_cti_o;
+reg [(3-1):0] d_cti_o;
output d_lock_o;
reg d_lock_o;
-output [ (2-1):0] d_bte_o;
-wire [ (2-1):0] d_bte_o;
+output [(2-1):0] d_bte_o;
+wire [(2-1):0] d_bte_o;
-reg [ 1:0] size_m;
-reg [ 1:0] size_w;
+reg [1:0] size_m;
+reg [1:0] size_w;
reg sign_extend_m;
reg sign_extend_w;
-reg [ (32-1):0] store_data_x;
-reg [ (32-1):0] store_data_m;
-reg [ (4-1):0] byte_enable_x;
-reg [ (4-1):0] byte_enable_m;
-wire [ (32-1):0] data_m;
-reg [ (32-1):0] data_w;
-
-
+reg [(32-1):0] store_data_x;
+reg [(32-1):0] store_data_m;
+reg [(4-1):0] byte_enable_x;
+reg [(4-1):0] byte_enable_m;
+wire [(32-1):0] data_m;
+reg [(32-1):0] data_w;
+
wire dcache_select_x;
reg dcache_select_m;
-wire [ (32-1):0] dcache_data_m;
-wire [ (32-1):0] dcache_refill_address;
+wire [(32-1):0] dcache_data_m;
+wire [(32-1):0] dcache_refill_address;
reg dcache_refill_ready;
-wire [ (3-1):0] first_cycle_type;
-wire [ (3-1):0] next_cycle_type;
+wire [(3-1):0] first_cycle_type;
+wire [(3-1):0] next_cycle_type;
wire last_word;
-wire [ (32-1):0] first_address;
-
+wire [(32-1):0] first_address;
-
+
@@ -18358,24 +16482,20 @@ wire [ (32-1):0] first_address;
-
wire wb_select_x;
-
+
-
reg wb_select_m;
-reg [ (32-1):0] wb_data_m;
+reg [(32-1):0] wb_data_m;
reg wb_load_complete;
-
-
-
+
@@ -18430,8 +16550,7 @@ endfunction
-
-
+
@@ -18515,9 +16634,7 @@ endfunction
-
-
-
+
lm32_dcache_full_debug #(
.associativity (associativity),
@@ -18549,7 +16666,6 @@ lm32_dcache_full_debug #(
.refilling (dcache_refilling),
.load_data (dcache_data_m)
);
-
@@ -18557,58 +16673,48 @@ lm32_dcache_full_debug #(
-
+
-
-
+
-
-
-
- assign dcache_select_x = (load_store_address_x >= 32'h0)
- && (load_store_address_x <= 32'h7fffffff)
-
+
+ assign dcache_select_x = (load_store_address_x >= 32'h0)
+ && (load_store_address_x <= 32'h7fffffff)
+
-
-
+
-
;
-
- assign wb_select_x = 1'b1
-
-
- && !dcache_select_x
+ assign wb_select_x = 1'b1
+ && !dcache_select_x
-
+
-
-
+
-
;
always @(*)
begin
case (size_x)
- 2'b00: store_data_x = {4{store_operand_x[7:0]}};
- 2'b11: store_data_x = {2{store_operand_x[15:0]}};
- 2'b10: store_data_x = store_operand_x;
- default: store_data_x = { 32{1'bx}};
+ 2'b00: store_data_x = {4{store_operand_x[7:0]}};
+ 2'b11: store_data_x = {2{store_operand_x[15:0]}};
+ 2'b10: store_data_x = store_operand_x;
+ default: store_data_x = {32{1'bx}};
endcase
end
@@ -18616,18 +16722,18 @@ end
always @(*)
begin
casez ({size_x, load_store_address_x[1:0]})
- { 2'b00, 2'b11}: byte_enable_x = 4'b0001;
- { 2'b00, 2'b10}: byte_enable_x = 4'b0010;
- { 2'b00, 2'b01}: byte_enable_x = 4'b0100;
- { 2'b00, 2'b00}: byte_enable_x = 4'b1000;
- { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
- { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
- { 2'b10, 2'b??}: byte_enable_x = 4'b1111;
+ {2'b00, 2'b11}: byte_enable_x = 4'b0001;
+ {2'b00, 2'b10}: byte_enable_x = 4'b0010;
+ {2'b00, 2'b01}: byte_enable_x = 4'b0100;
+ {2'b00, 2'b00}: byte_enable_x = 4'b1000;
+ {2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+ {2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+ {2'b10, 2'b??}: byte_enable_x = 4'b1111;
default: byte_enable_x = 4'bxxxx;
endcase
end
-
+
@@ -18635,8 +16741,7 @@ end
-
-
+
@@ -18644,8 +16749,7 @@ end
-
-
+
@@ -18665,11 +16769,9 @@ end
-
+
-
-
@@ -18688,8 +16790,7 @@ end
-
-
+
@@ -18697,16 +16798,13 @@ end
-
- assign data_m = wb_select_m == 1'b1
+ assign data_m = wb_select_m == 1'b1
? wb_data_m
: dcache_data_m;
-
-
-
+
@@ -18733,55 +16831,52 @@ end
-
always @(*)
begin
casez ({size_w, load_store_address_w[1:0]})
- { 2'b00, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
- { 2'b00, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
- { 2'b00, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
- { 2'b00, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
- { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
- { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
- { 2'b10, 2'b??}: load_data_w = data_w;
- default: load_data_w = { 32{1'bx}};
+ {2'b00, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+ {2'b00, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+ {2'b00, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+ {2'b00, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+ {2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+ {2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+ {2'b10, 2'b??}: load_data_w = data_w;
+ default: load_data_w = {32{1'bx}};
endcase
end
-assign d_bte_o = 2'b00;
+assign d_bte_o = 2'b00;
-
-
+
generate
case (bytes_per_line)
4:
begin
-assign first_cycle_type = 3'b111;
-assign next_cycle_type = 3'b111;
-assign last_word = 1'b1;
-assign first_address = {dcache_refill_address[ 32-1:2], 2'b00};
+assign first_cycle_type = 3'b111;
+assign next_cycle_type = 3'b111;
+assign last_word = 1'b1;
+assign first_address = {dcache_refill_address[32-1:2], 2'b00};
end
8:
begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = 3'b111;
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = 3'b111;
assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
-assign first_address = {dcache_refill_address[ 32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
+assign first_address = {dcache_refill_address[32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
end
16:
begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
-assign first_address = {dcache_refill_address[ 32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
+assign first_address = {dcache_refill_address[32-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
end
endcase
endgenerate
-
@@ -18789,63 +16884,55 @@ endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- d_cyc_o <= 1'b0;
- d_stb_o <= 1'b0;
- d_dat_o <= { 32{1'b0}};
- d_adr_o <= { 32{1'b0}};
- d_sel_o <= { 4{ 1'b0}};
- d_we_o <= 1'b0;
- d_cti_o <= 3'b111;
- d_lock_o <= 1'b0;
- wb_data_m <= { 32{1'b0}};
- wb_load_complete <= 1'b0;
- stall_wb_load <= 1'b0;
-
-
- dcache_refill_ready <= 1'b0;
-
+ d_cyc_o <= 1'b0;
+ d_stb_o <= 1'b0;
+ d_dat_o <= {32{1'b0}};
+ d_adr_o <= {32{1'b0}};
+ d_sel_o <= {4{1'b0}};
+ d_we_o <= 1'b0;
+ d_cti_o <= 3'b111;
+ d_lock_o <= 1'b0;
+ wb_data_m <= {32{1'b0}};
+ wb_load_complete <= 1'b0;
+ stall_wb_load <= 1'b0;
+
+ dcache_refill_ready <= 1'b0;
end
else
begin
-
- dcache_refill_ready <= 1'b0;
-
+ dcache_refill_ready <= 1'b0;
- if (d_cyc_o == 1'b1)
+ if (d_cyc_o == 1'b1)
begin
- if ((d_ack_i == 1'b1) || (d_err_i == 1'b1))
+ if ((d_ack_i == 1'b1) || (d_err_i == 1'b1))
begin
-
-
- if ((dcache_refilling == 1'b1) && (!last_word))
+
+ if ((dcache_refilling == 1'b1) && (!last_word))
begin
d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
end
else
-
begin
- d_cyc_o <= 1'b0;
- d_stb_o <= 1'b0;
- d_lock_o <= 1'b0;
+ d_cyc_o <= 1'b0;
+ d_stb_o <= 1'b0;
+ d_lock_o <= 1'b0;
end
-
-
+
d_cti_o <= next_cycle_type;
dcache_refill_ready <= dcache_refilling;
-
wb_data_m <= d_dat_i;
@@ -18853,137 +16940,125 @@ begin
wb_load_complete <= !d_we_o;
end
- if (d_err_i == 1'b1)
+ if (d_err_i == 1'b1)
$display ("Data bus error. Address: %x", d_adr_o);
end
else
begin
-
-
- if (dcache_refill_request == 1'b1)
+
+ if (dcache_refill_request == 1'b1)
begin
d_adr_o <= first_address;
- d_cyc_o <= 1'b1;
- d_sel_o <= { 32/8{ 1'b1}};
- d_stb_o <= 1'b1;
- d_we_o <= 1'b0;
+ d_cyc_o <= 1'b1;
+ d_sel_o <= {32/8{1'b1}};
+ d_stb_o <= 1'b1;
+ d_we_o <= 1'b0;
d_cti_o <= first_cycle_type;
end
else
-
- if ( (store_q_m == 1'b1)
- && (stall_m == 1'b0)
-
+ if ( (store_q_m == 1'b1)
+ && (stall_m == 1'b0)
+
-
-
+
-
)
begin
d_dat_o <= store_data_m;
d_adr_o <= load_store_address_m;
- d_cyc_o <= 1'b1;
+ d_cyc_o <= 1'b1;
d_sel_o <= byte_enable_m;
- d_stb_o <= 1'b1;
- d_we_o <= 1'b1;
- d_cti_o <= 3'b111;
+ d_stb_o <= 1'b1;
+ d_we_o <= 1'b1;
+ d_cti_o <= 3'b111;
end
- else if ( (load_q_m == 1'b1)
- && (wb_select_m == 1'b1)
- && (wb_load_complete == 1'b0)
+ else if ( (load_q_m == 1'b1)
+ && (wb_select_m == 1'b1)
+ && (wb_load_complete == 1'b0)
)
begin
- stall_wb_load <= 1'b0;
+ stall_wb_load <= 1'b0;
d_adr_o <= load_store_address_m;
- d_cyc_o <= 1'b1;
+ d_cyc_o <= 1'b1;
d_sel_o <= byte_enable_m;
- d_stb_o <= 1'b1;
- d_we_o <= 1'b0;
- d_cti_o <= 3'b111;
+ d_stb_o <= 1'b1;
+ d_we_o <= 1'b0;
+ d_cti_o <= 3'b111;
end
end
- if (stall_m == 1'b0)
- wb_load_complete <= 1'b0;
+ if (stall_m == 1'b0)
+ wb_load_complete <= 1'b0;
- if ((load_q_x == 1'b1) && (wb_select_x == 1'b1) && (stall_x == 1'b0))
- stall_wb_load <= 1'b1;
+ if ((load_q_x == 1'b1) && (wb_select_x == 1'b1) && (stall_x == 1'b0))
+ stall_wb_load <= 1'b1;
- if ((kill_m == 1'b1) || (exception_m == 1'b1))
- stall_wb_load <= 1'b0;
+ if ((kill_m == 1'b1) || (exception_m == 1'b1))
+ stall_wb_load <= 1'b0;
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- sign_extend_m <= 1'b0;
+ sign_extend_m <= 1'b0;
size_m <= 2'b00;
- byte_enable_m <= 1'b0;
- store_data_m <= { 32{1'b0}};
-
-
- dcache_select_m <= 1'b0;
+ byte_enable_m <= 1'b0;
+ store_data_m <= {32{1'b0}};
+ dcache_select_m <= 1'b0;
-
+
-
-
+
-
- wb_select_m <= 1'b0;
+ wb_select_m <= 1'b0;
end
else
begin
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
sign_extend_m <= sign_extend_x;
size_m <= size_x;
byte_enable_m <= byte_enable_x;
store_data_m <= store_data_x;
-
-
- dcache_select_m <= dcache_select_x;
+ dcache_select_m <= dcache_select_x;
-
+
-
-
+
-
wb_select_m <= wb_select_x;
end
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
size_w <= 2'b00;
- data_w <= { 32{1'b0}};
- sign_extend_w <= 1'b0;
+ data_w <= {32{1'b0}};
+ sign_extend_w <= 1'b0;
end
else
begin
@@ -19002,11 +17077,11 @@ end
always @(posedge clk_i)
begin
- if (((load_q_m == 1'b1) || (store_q_m == 1'b1)) && (stall_m == 1'b0))
+ if (((load_q_m == 1'b1) || (store_q_m == 1'b1)) && (stall_m == 1'b0))
begin
- if ((size_m === 2'b11) && (load_store_address_m[0] !== 1'b0))
+ if ((size_m === 2'b11) && (load_store_address_m[0] !== 1'b0))
$display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
- if ((size_m === 2'b10) && (load_store_address_m[1:0] !== 2'b00))
+ if ((size_m === 2'b10) && (load_store_address_m[1:0] !== 2'b00))
$display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
end
end
@@ -19048,10 +17123,7 @@ endmodule
-
-
-
-
+
@@ -19081,9 +17153,9 @@ endmodule
-
+
@@ -19368,104 +17440,55 @@ endmodule
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
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-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -19478,37 +17501,27 @@ module lm32_decoder_full_debug (
d_result_sel_0,
d_result_sel_1,
x_result_sel_csr,
-
-
- x_result_sel_mc_arith,
+ x_result_sel_mc_arith,
-
+
-
-
-
- x_result_sel_sext,
+ x_result_sel_sext,
x_result_sel_logic,
-
+
-
x_result_sel_add,
m_result_sel_compare,
-
-
- m_result_sel_shift,
+ m_result_sel_shift,
w_result_sel_load,
-
-
- w_result_sel_mul,
+ w_result_sel_mul,
x_bypass_enable,
m_bypass_enable,
@@ -19526,47 +17539,36 @@ module lm32_decoder_full_debug (
sign_extend,
adder_op,
logic_op,
-
-
- direction,
+ direction,
-
+
-
-
+
-
-
-
+
divide,
modulus,
-
branch,
branch_reg,
condition,
bi_conditional,
bi_unconditional,
-
-
- break_opcode,
+ break_opcode,
scall,
eret,
-
-
- bret,
+ bret,
-
+
-
csr_write_enable
);
@@ -19574,59 +17576,49 @@ module lm32_decoder_full_debug (
-input [ (32-1):0] instruction;
+input [(32-1):0] instruction;
-output [ 0:0] d_result_sel_0;
-reg [ 0:0] d_result_sel_0;
-output [ 1:0] d_result_sel_1;
-reg [ 1:0] d_result_sel_1;
+output [0:0] d_result_sel_0;
+reg [0:0] d_result_sel_0;
+output [1:0] d_result_sel_1;
+reg [1:0] d_result_sel_1;
output x_result_sel_csr;
reg x_result_sel_csr;
-
-
+
output x_result_sel_mc_arith;
reg x_result_sel_mc_arith;
-
-
+
-
-
-
+
output x_result_sel_sext;
reg x_result_sel_sext;
-
output x_result_sel_logic;
reg x_result_sel_logic;
-
+
-
output x_result_sel_add;
reg x_result_sel_add;
output m_result_sel_compare;
reg m_result_sel_compare;
-
-
+
output m_result_sel_shift;
reg m_result_sel_shift;
-
output w_result_sel_load;
reg w_result_sel_load;
-
-
+
output w_result_sel_mul;
reg w_result_sel_mul;
-
output x_bypass_enable;
wire x_bypass_enable;
@@ -19634,89 +17626,78 @@ output m_bypass_enable;
wire m_bypass_enable;
output read_enable_0;
wire read_enable_0;
-output [ (5-1):0] read_idx_0;
-wire [ (5-1):0] read_idx_0;
+output [(5-1):0] read_idx_0;
+wire [(5-1):0] read_idx_0;
output read_enable_1;
wire read_enable_1;
-output [ (5-1):0] read_idx_1;
-wire [ (5-1):0] read_idx_1;
+output [(5-1):0] read_idx_1;
+wire [(5-1):0] read_idx_1;
output write_enable;
wire write_enable;
-output [ (5-1):0] write_idx;
-wire [ (5-1):0] write_idx;
-output [ (32-1):0] immediate;
-wire [ (32-1):0] immediate;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output [(5-1):0] write_idx;
+wire [(5-1):0] write_idx;
+output [(32-1):0] immediate;
+wire [(32-1):0] immediate;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
output load;
wire load;
output store;
wire store;
-output [ 1:0] size;
-wire [ 1:0] size;
+output [1:0] size;
+wire [1:0] size;
output sign_extend;
wire sign_extend;
output adder_op;
wire adder_op;
-output [ 3:0] logic_op;
-wire [ 3:0] logic_op;
-
-
+output [3:0] logic_op;
+wire [3:0] logic_op;
+
output direction;
wire direction;
-
-
+
-
-
+
-
-
-
+
output divide;
wire divide;
output modulus;
wire modulus;
-
output branch;
wire branch;
output branch_reg;
wire branch_reg;
-output [ (3-1):0] condition;
-wire [ (3-1):0] condition;
+output [(3-1):0] condition;
+wire [(3-1):0] condition;
output bi_conditional;
wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
-
-
+
output break_opcode;
wire break_opcode;
-
output scall;
wire scall;
output eret;
wire eret;
-
-
+
output bret;
wire bret;
-
-
+
-
output csr_write_enable;
wire csr_write_enable;
@@ -19724,10 +17705,10 @@ wire csr_write_enable;
-wire [ (32-1):0] extended_immediate;
-wire [ (32-1):0] high_immediate;
-wire [ (32-1):0] call_immediate;
-wire [ (32-1):0] branch_immediate;
+wire [(32-1):0] extended_immediate;
+wire [(32-1):0] high_immediate;
+wire [(32-1):0] call_immediate;
+wire [(32-1):0] branch_immediate;
wire sign_extend_immediate;
wire select_high_immediate;
wire select_call_immediate;
@@ -19736,9 +17717,7 @@ wire select_call_immediate;
-
-
-
+
@@ -19794,72 +17773,61 @@ endfunction
-
-assign op_add = instruction[ 30:26] == 5'b01101;
-assign op_and = instruction[ 30:26] == 5'b01000;
-assign op_andhi = instruction[ 31:26] == 6'b011000;
-assign op_b = instruction[ 31:26] == 6'b110000;
-assign op_bi = instruction[ 31:26] == 6'b111000;
-assign op_be = instruction[ 31:26] == 6'b010001;
-assign op_bg = instruction[ 31:26] == 6'b010010;
-assign op_bge = instruction[ 31:26] == 6'b010011;
-assign op_bgeu = instruction[ 31:26] == 6'b010100;
-assign op_bgu = instruction[ 31:26] == 6'b010101;
-assign op_bne = instruction[ 31:26] == 6'b010111;
-assign op_call = instruction[ 31:26] == 6'b110110;
-assign op_calli = instruction[ 31:26] == 6'b111110;
-assign op_cmpe = instruction[ 30:26] == 5'b11001;
-assign op_cmpg = instruction[ 30:26] == 5'b11010;
-assign op_cmpge = instruction[ 30:26] == 5'b11011;
-assign op_cmpgeu = instruction[ 30:26] == 5'b11100;
-assign op_cmpgu = instruction[ 30:26] == 5'b11101;
-assign op_cmpne = instruction[ 30:26] == 5'b11111;
-
-
-assign op_divu = instruction[ 31:26] == 6'b100011;
+assign op_add = instruction[30:26] == 5'b01101;
+assign op_and = instruction[30:26] == 5'b01000;
+assign op_andhi = instruction[31:26] == 6'b011000;
+assign op_b = instruction[31:26] == 6'b110000;
+assign op_bi = instruction[31:26] == 6'b111000;
+assign op_be = instruction[31:26] == 6'b010001;
+assign op_bg = instruction[31:26] == 6'b010010;
+assign op_bge = instruction[31:26] == 6'b010011;
+assign op_bgeu = instruction[31:26] == 6'b010100;
+assign op_bgu = instruction[31:26] == 6'b010101;
+assign op_bne = instruction[31:26] == 6'b010111;
+assign op_call = instruction[31:26] == 6'b110110;
+assign op_calli = instruction[31:26] == 6'b111110;
+assign op_cmpe = instruction[30:26] == 5'b11001;
+assign op_cmpg = instruction[30:26] == 5'b11010;
+assign op_cmpge = instruction[30:26] == 5'b11011;
+assign op_cmpgeu = instruction[30:26] == 5'b11100;
+assign op_cmpgu = instruction[30:26] == 5'b11101;
+assign op_cmpne = instruction[30:26] == 5'b11111;
+assign op_divu = instruction[31:26] == 6'b100011;
-assign op_lb = instruction[ 31:26] == 6'b000100;
-assign op_lbu = instruction[ 31:26] == 6'b010000;
-assign op_lh = instruction[ 31:26] == 6'b000111;
-assign op_lhu = instruction[ 31:26] == 6'b001011;
-assign op_lw = instruction[ 31:26] == 6'b001010;
-
-
-assign op_modu = instruction[ 31:26] == 6'b110001;
+assign op_lb = instruction[31:26] == 6'b000100;
+assign op_lbu = instruction[31:26] == 6'b010000;
+assign op_lh = instruction[31:26] == 6'b000111;
+assign op_lhu = instruction[31:26] == 6'b001011;
+assign op_lw = instruction[31:26] == 6'b001010;
+assign op_modu = instruction[31:26] == 6'b110001;
-
-
-assign op_mul = instruction[ 30:26] == 5'b00010;
+assign op_mul = instruction[30:26] == 5'b00010;
-assign op_nor = instruction[ 30:26] == 5'b00001;
-assign op_or = instruction[ 30:26] == 5'b01110;
-assign op_orhi = instruction[ 31:26] == 6'b011110;
-assign op_raise = instruction[ 31:26] == 6'b101011;
-assign op_rcsr = instruction[ 31:26] == 6'b100100;
-assign op_sb = instruction[ 31:26] == 6'b001100;
-
-
-assign op_sextb = instruction[ 31:26] == 6'b101100;
-assign op_sexth = instruction[ 31:26] == 6'b110111;
+assign op_nor = instruction[30:26] == 5'b00001;
+assign op_or = instruction[30:26] == 5'b01110;
+assign op_orhi = instruction[31:26] == 6'b011110;
+assign op_raise = instruction[31:26] == 6'b101011;
+assign op_rcsr = instruction[31:26] == 6'b100100;
+assign op_sb = instruction[31:26] == 6'b001100;
+assign op_sextb = instruction[31:26] == 6'b101100;
+assign op_sexth = instruction[31:26] == 6'b110111;
-assign op_sh = instruction[ 31:26] == 6'b000011;
-
-
-assign op_sl = instruction[ 30:26] == 5'b01111;
+assign op_sh = instruction[31:26] == 6'b000011;
+assign op_sl = instruction[30:26] == 5'b01111;
-assign op_sr = instruction[ 30:26] == 5'b00101;
-assign op_sru = instruction[ 30:26] == 5'b00000;
-assign op_sub = instruction[ 31:26] == 6'b110010;
-assign op_sw = instruction[ 31:26] == 6'b010110;
-assign op_user = instruction[ 31:26] == 6'b110011;
-assign op_wcsr = instruction[ 31:26] == 6'b110100;
-assign op_xnor = instruction[ 30:26] == 5'b01001;
-assign op_xor = instruction[ 30:26] == 5'b00110;
+assign op_sr = instruction[30:26] == 5'b00101;
+assign op_sru = instruction[30:26] == 5'b00000;
+assign op_sub = instruction[31:26] == 6'b110010;
+assign op_sw = instruction[31:26] == 6'b010110;
+assign op_user = instruction[31:26] == 6'b110011;
+assign op_wcsr = instruction[31:26] == 6'b110100;
+assign op_xnor = instruction[30:26] == 5'b01001;
+assign op_xor = instruction[30:26] == 5'b00110;
assign arith = op_add | op_sub;
@@ -19869,35 +17837,25 @@ assign bi_conditional = op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne;
assign bi_unconditional = op_bi;
assign bra = op_b | bi_unconditional | bi_conditional;
assign call = op_call | op_calli;
-
-
-assign shift = op_sl | op_sr | op_sru;
+assign shift = op_sl | op_sr | op_sru;
-
+
-
-
+
-
-
-
-assign sext = op_sextb | op_sexth;
+assign sext = op_sextb | op_sexth;
-
-
-assign multiply = op_mul;
+assign multiply = op_mul;
-
-
+
assign divide = op_divu;
assign modulus = op_modu;
-
assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
assign store = op_sb | op_sh | op_sw;
@@ -19907,137 +17865,107 @@ always @(*)
begin
if (call)
- d_result_sel_0 = 1'b1;
+ d_result_sel_0 = 1'b1;
else
- d_result_sel_0 = 1'b0;
+ d_result_sel_0 = 1'b0;
if (call)
- d_result_sel_1 = 2'b00;
+ d_result_sel_1 = 2'b00;
else if ((instruction[31] == 1'b0) && !bra)
- d_result_sel_1 = 2'b10;
+ d_result_sel_1 = 2'b10;
else
- d_result_sel_1 = 2'b01;
+ d_result_sel_1 = 2'b01;
- x_result_sel_csr = 1'b0;
-
-
- x_result_sel_mc_arith = 1'b0;
+ x_result_sel_csr = 1'b0;
+ x_result_sel_mc_arith = 1'b0;
-
+
-
-
-
- x_result_sel_sext = 1'b0;
+ x_result_sel_sext = 1'b0;
- x_result_sel_logic = 1'b0;
-
+ x_result_sel_logic = 1'b0;
+
-
- x_result_sel_add = 1'b0;
+ x_result_sel_add = 1'b0;
if (op_rcsr)
- x_result_sel_csr = 1'b1;
-
-
-
+ x_result_sel_csr = 1'b1;
+
+
-
-
-
- else if (divide | modulus)
- x_result_sel_mc_arith = 1'b1;
+ else if (divide | modulus)
+ x_result_sel_mc_arith = 1'b1;
-
+
-
-
-
-
-
- else if (sext)
- x_result_sel_sext = 1'b1;
+ else if (sext)
+ x_result_sel_sext = 1'b1;
else if (logical)
- x_result_sel_logic = 1'b1;
-
+ x_result_sel_logic = 1'b1;
+
-
else
- x_result_sel_add = 1'b1;
+ x_result_sel_add = 1'b1;
m_result_sel_compare = cmp;
-
-
- m_result_sel_shift = shift;
+ m_result_sel_shift = shift;
w_result_sel_load = load;
-
-
- w_result_sel_mul = op_mul;
+ w_result_sel_mul = op_mul;
end
assign x_bypass_enable = arith
| logical
-
+
-
-
+
-
-
-
+
| divide
| modulus
-
-
+
-
-
-
- | sext
+ | sext
-
+
-
| op_rcsr
;
assign m_bypass_enable = x_bypass_enable
-
-
- | shift
+ | shift
| cmp
;
@@ -20063,34 +17991,27 @@ assign sign_extend = instruction[28];
assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
assign logic_op = instruction[29:26];
-
-
+
assign direction = instruction[29];
-
assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
-
-
-assign break_opcode = op_raise & ~instruction[2];
+assign break_opcode = op_raise & ~instruction[2];
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
-
-
-assign bret = op_b & (instruction[25:21] == 5'd31);
+assign bret = op_b & (instruction[25:21] == 5'd31);
-
+
-
assign csr_write_enable = op_wcsr;
@@ -20104,11 +18025,11 @@ assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, inst
assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
-assign immediate = select_high_immediate == 1'b1
+assign immediate = select_high_immediate == 1'b1
? high_immediate
: extended_immediate;
-assign branch_offset = select_call_immediate == 1'b1
+assign branch_offset = select_call_immediate == 1'b1
? call_immediate
: branch_immediate;
@@ -20149,10 +18070,7 @@ endmodule
-
-
-
-
+
@@ -20182,9 +18100,9 @@ endmodule
-
+
@@ -20468,48 +18386,28 @@ endmodule
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
-
+
+
+
+
+
+
+
+
+
@@ -20527,10 +18425,9 @@ module lm32_icache_full_debug (
refill_ready,
refill_data,
iflush,
-
+
-
valid_d,
branch_predict_taken_d,
@@ -20559,7 +18456,7 @@ localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
localparam addr_set_lsb = (addr_offset_msb+1);
localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
localparam addr_tag_lsb = (addr_set_msb+1);
-localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_msb = clogb2(32'h7fffffff-32'h0)-1;
localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
@@ -20575,18 +18472,17 @@ input stall_f;
input valid_d;
input branch_predict_taken_d;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;
input read_enable_f;
input refill_ready;
-input [ (32-1):0] refill_data;
+input [(32-1):0] refill_data;
input iflush;
-
+
-
@@ -20598,12 +18494,12 @@ output restart_request;
reg restart_request;
output refill_request;
wire refill_request;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
output refilling;
reg refilling;
-output [ (32-1):0] inst;
-wire [ (32-1):0] inst;
+output [(32-1):0] inst;
+wire [(32-1):0] inst;
@@ -20611,27 +18507,27 @@ wire [ (32-1):0] inst;
wire enable;
wire [0:associativity-1] way_mem_we;
-wire [ (32-1):0] way_data[0:associativity-1];
-wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [(32-1):0] way_data[0:associativity-1];
+wire [((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
wire [0:associativity-1] way_valid;
wire [0:associativity-1] way_match;
wire miss;
-wire [ (addr_set_width-1):0] tmem_read_address;
-wire [ (addr_set_width-1):0] tmem_write_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
-wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+wire [(addr_set_width-1):0] tmem_read_address;
+wire [(addr_set_width-1):0] tmem_write_address;
+wire [((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [((addr_tag_width+1)-1):0] tmem_write_data;
-reg [ 3:0] state;
+reg [3:0] state;
wire flushing;
wire check;
wire refill;
reg [associativity-1:0] refill_way_select;
-reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+reg [addr_offset_msb:addr_offset_lsb] refill_offset;
wire last_refill;
-reg [ (addr_set_width-1):0] flush_set;
+reg [(addr_set_width-1):0] flush_set;
genvar i;
@@ -20639,9 +18535,7 @@ genvar i;
-
-
-
+
@@ -20696,7 +18590,6 @@ endfunction
-
generate
for (i = 0; i < associativity; i = i + 1)
begin : memories
@@ -20705,7 +18598,7 @@ endfunction
#(
.data_width (32),
- .address_width ( (addr_offset_width+addr_set_width))
+ .address_width ((addr_offset_width+addr_set_width))
)
way_0_data_ram
@@ -20717,7 +18610,7 @@ endfunction
.read_address (dmem_read_address),
.enable_read (enable),
.write_address (dmem_write_address),
- .enable_write ( 1'b1),
+ .enable_write (1'b1),
.write_enable (way_mem_we[i]),
.write_data (refill_data),
@@ -20727,8 +18620,8 @@ endfunction
lm32_ram
#(
- .data_width ( (addr_tag_width+1)),
- .address_width ( addr_set_width)
+ .data_width ((addr_tag_width+1)),
+ .address_width (addr_set_width)
)
way_0_tag_ram
@@ -20740,7 +18633,7 @@ endfunction
.read_address (tmem_read_address),
.enable_read (enable),
.write_address (tmem_write_address),
- .enable_write ( 1'b1),
+ .enable_write (1'b1),
.write_enable (way_mem_we[i] | flushing),
.write_data (tmem_write_data),
@@ -20758,7 +18651,7 @@ endgenerate
generate
for (i = 0; i < associativity; i = i + 1)
begin : match
-assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb], 1'b1});
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[addr_tag_msb:addr_tag_lsb], 1'b1});
end
endgenerate
@@ -20777,55 +18670,55 @@ endgenerate
generate
if (bytes_per_line > 4)
-assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+assign dmem_write_address = {refill_address[addr_set_msb:addr_set_lsb], refill_offset};
else
-assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+assign dmem_write_address = refill_address[addr_set_msb:addr_set_lsb];
endgenerate
-assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+assign dmem_read_address = address_a[addr_set_msb:addr_offset_lsb];
-assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_read_address = address_a[addr_set_msb:addr_set_lsb];
assign tmem_write_address = flushing
? flush_set
- : refill_address[ addr_set_msb:addr_set_lsb];
+ : refill_address[addr_set_msb:addr_set_lsb];
generate
if (bytes_per_line > 4)
assign last_refill = refill_offset == {addr_offset_width{1'b1}};
else
-assign last_refill = 1'b1;
+assign last_refill = 1'b1;
endgenerate
-assign enable = (stall_a == 1'b0);
+assign enable = (stall_a == 1'b0);
generate
if (associativity == 1)
begin : we_1
-assign way_mem_we[0] = (refill_ready == 1'b1);
+assign way_mem_we[0] = (refill_ready == 1'b1);
end
else
begin : we_2
-assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1);
-assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1);
+assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1);
+assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1);
end
endgenerate
-assign tmem_write_data[ 0] = last_refill & !flushing;
-assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+assign tmem_write_data[0] = last_refill & !flushing;
+assign tmem_write_data[((addr_tag_width+1)-1):1] = refill_address[addr_tag_msb:addr_tag_lsb];
assign flushing = |state[1:0];
assign check = state[2];
assign refill = state[3];
-assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d);
-assign stall_request = (check == 1'b0);
-assign refill_request = (refill == 1'b1);
+assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check == 1'b0);
+assign refill_request = (refill == 1'b1);
@@ -20835,13 +18728,13 @@ assign refill_request = (refill == 1'b1);
generate
if (associativity >= 2)
begin : way_select
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
else
begin
- if (miss == 1'b1)
+ if (miss == 1'b1)
refill_way_select <= {refill_way_select[0], refill_way_select[1]};
end
end
@@ -20849,77 +18742,76 @@ end
endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- refilling <= 1'b0;
+ if (rst_i == 1'b1)
+ refilling <= 1'b0;
else
refilling <= refill;
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- state <= 4'b0001;
- flush_set <= { addr_set_width{1'b1}};
- refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
- restart_request <= 1'b0;
+ state <= 4'b0001;
+ flush_set <= {addr_set_width{1'b1}};
+ refill_address <= {(clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+ restart_request <= 1'b0;
end
else
begin
case (state)
- 4'b0001:
+ 4'b0001:
begin
- if (flush_set == { addr_set_width{1'b0}})
- state <= 4'b0100;
+ if (flush_set == {addr_set_width{1'b0}})
+ state <= 4'b0100;
flush_set <= flush_set - 1'b1;
end
- 4'b0010:
+ 4'b0010:
begin
- if (flush_set == { addr_set_width{1'b0}})
-
+ if (flush_set == {addr_set_width{1'b0}})
+
-
- state <= 4'b0100;
+ state <= 4'b0100;
flush_set <= flush_set - 1'b1;
end
- 4'b0100:
+ 4'b0100:
begin
- if (stall_a == 1'b0)
- restart_request <= 1'b0;
- if (iflush == 1'b1)
+ if (stall_a == 1'b0)
+ restart_request <= 1'b0;
+ if (iflush == 1'b1)
begin
refill_address <= address_f;
- state <= 4'b0010;
+ state <= 4'b0010;
end
- else if (miss == 1'b1)
+ else if (miss == 1'b1)
begin
refill_address <= address_f;
- state <= 4'b1000;
+ state <= 4'b1000;
end
end
- 4'b1000:
+ 4'b1000:
begin
- if (refill_ready == 1'b1)
+ if (refill_ready == 1'b1)
begin
- if (last_refill == 1'b1)
+ if (last_refill == 1'b1)
begin
- restart_request <= 1'b1;
- state <= 4'b0100;
+ restart_request <= 1'b1;
+ state <= 4'b0100;
end
end
end
@@ -20932,27 +18824,27 @@ generate
if (bytes_per_line > 4)
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
else
begin
case (state)
- 4'b0100:
+ 4'b0100:
begin
- if (iflush == 1'b1)
+ if (iflush == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
- else if (miss == 1'b1)
+ else if (miss == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
end
- 4'b1000:
+ 4'b1000:
begin
- if (refill_ready == 1'b1)
+ if (refill_ready == 1'b1)
refill_offset <= refill_offset + 1'b1;
end
@@ -20964,7 +18856,6 @@ endgenerate
endmodule
-
@@ -20997,10 +18888,7 @@ endmodule
-
-
-
-
+
@@ -21030,9 +18918,9 @@ endmodule
-
+
@@ -21316,46 +19204,27 @@ endmodule
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
-
+
+
+
+
+
+
+
+
@@ -21403,7 +19272,7 @@ localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
localparam addr_set_lsb = (addr_offset_msb+1);
localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
localparam addr_tag_lsb = (addr_set_msb+1);
-localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_msb = clogb2(32'h7fffffff-32'h0)-1;
localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
@@ -21417,15 +19286,15 @@ input stall_a;
input stall_x;
input stall_m;
-input [ (32-1):0] address_x;
-input [ (32-1):0] address_m;
+input [(32-1):0] address_x;
+input [(32-1):0] address_m;
input load_q_m;
input store_q_m;
-input [ (32-1):0] store_data;
-input [ (4-1):0] store_byte_select;
+input [(32-1):0] store_data;
+input [(4-1):0] store_byte_select;
input refill_ready;
-input [ (32-1):0] refill_data;
+input [(32-1):0] refill_data;
input dflush;
@@ -21439,12 +19308,12 @@ output restart_request;
reg restart_request;
output refill_request;
reg refill_request;
-output [ (32-1):0] refill_address;
-reg [ (32-1):0] refill_address;
+output [(32-1):0] refill_address;
+reg [(32-1):0] refill_address;
output refilling;
reg refilling;
-output [ (32-1):0] load_data;
-wire [ (32-1):0] load_data;
+output [(32-1):0] load_data;
+wire [(32-1):0] load_data;
@@ -21454,29 +19323,29 @@ wire read_port_enable;
wire write_port_enable;
wire [0:associativity-1] way_tmem_we;
wire [0:associativity-1] way_dmem_we;
-wire [ (32-1):0] way_data[0:associativity-1];
-wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [(32-1):0] way_data[0:associativity-1];
+wire [((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
wire [0:associativity-1] way_valid;
wire [0:associativity-1] way_match;
wire miss;
-wire [ (addr_set_width-1):0] tmem_read_address;
-wire [ (addr_set_width-1):0] tmem_write_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
-wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
-reg [ (32-1):0] dmem_write_data;
+wire [(addr_set_width-1):0] tmem_read_address;
+wire [(addr_set_width-1):0] tmem_write_address;
+wire [((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [((addr_tag_width+1)-1):0] tmem_write_data;
+reg [(32-1):0] dmem_write_data;
-reg [ 2:0] state;
+reg [2:0] state;
wire flushing;
wire check;
wire refill;
wire valid_store;
reg [associativity-1:0] refill_way_select;
-reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+reg [addr_offset_msb:addr_offset_lsb] refill_offset;
wire last_refill;
-reg [ (addr_set_width-1):0] flush_set;
+reg [(addr_set_width-1):0] flush_set;
genvar i, j;
@@ -21484,9 +19353,7 @@ genvar i, j;
-
-
-
+
@@ -21541,18 +19408,17 @@ endfunction
-
generate
for (i = 0; i < associativity; i = i + 1)
begin : memories
- if ( (addr_offset_width+addr_set_width) < 11)
+ if ((addr_offset_width+addr_set_width) < 11)
begin : data_memories
lm32_ram
#(
.data_width (32),
- .address_width ( (addr_offset_width+addr_set_width))
+ .address_width ((addr_offset_width+addr_set_width))
) way_0_data_ram
(
@@ -21578,7 +19444,7 @@ endfunction
#(
.data_width (8),
- .address_width ( (addr_offset_width+addr_set_width))
+ .address_width ((addr_offset_width+addr_set_width))
) way_0_data_ram
(
@@ -21602,8 +19468,8 @@ endfunction
lm32_ram
#(
- .data_width ( (addr_tag_width+1)),
- .address_width ( addr_set_width)
+ .data_width ((addr_tag_width+1)),
+ .address_width (addr_set_width)
) way_0_tag_ram
(
@@ -21614,7 +19480,7 @@ endfunction
.read_address (tmem_read_address),
.enable_read (read_port_enable),
.write_address (tmem_write_address),
- .enable_write ( 1'b1),
+ .enable_write (1'b1),
.write_enable (way_tmem_we[i]),
.write_data (tmem_write_data),
@@ -21632,7 +19498,7 @@ endfunction
generate
for (i = 0; i < associativity; i = i + 1)
begin : match
-assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[ addr_tag_msb:addr_tag_lsb], 1'b1});
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[addr_tag_msb:addr_tag_lsb], 1'b1});
end
endgenerate
@@ -21649,19 +19515,19 @@ assign load_data = way_match[0] ? way_data[0] : way_data[1];
endgenerate
generate
- if ( (addr_offset_width+addr_set_width) < 11)
+ if ((addr_offset_width+addr_set_width) < 11)
begin
always @(*)
begin
- if (refill == 1'b1)
+ if (refill == 1'b1)
dmem_write_data = refill_data;
else
begin
- dmem_write_data[ 7:0] = store_byte_select[0] ? store_data[ 7:0] : load_data[ 7:0];
- dmem_write_data[ 15:8] = store_byte_select[1] ? store_data[ 15:8] : load_data[ 15:8];
- dmem_write_data[ 23:16] = store_byte_select[2] ? store_data[ 23:16] : load_data[ 23:16];
- dmem_write_data[ 31:24] = store_byte_select[3] ? store_data[ 31:24] : load_data[ 31:24];
+ dmem_write_data[7:0] = store_byte_select[0] ? store_data[7:0] : load_data[7:0];
+ dmem_write_data[15:8] = store_byte_select[1] ? store_data[15:8] : load_data[15:8];
+ dmem_write_data[23:16] = store_byte_select[2] ? store_data[23:16] : load_data[23:16];
+ dmem_write_data[31:24] = store_byte_select[3] ? store_data[31:24] : load_data[31:24];
end
end
end
@@ -21670,7 +19536,7 @@ end
always @(*)
begin
- if (refill == 1'b1)
+ if (refill == 1'b1)
dmem_write_data = refill_data;
else
dmem_write_data = store_data;
@@ -21681,63 +19547,63 @@ endgenerate
generate
if (bytes_per_line > 4)
-assign dmem_write_address = (refill == 1'b1)
- ? {refill_address[ addr_set_msb:addr_set_lsb], refill_offset}
- : address_m[ addr_set_msb:addr_offset_lsb];
+assign dmem_write_address = (refill == 1'b1)
+ ? {refill_address[addr_set_msb:addr_set_lsb], refill_offset}
+ : address_m[addr_set_msb:addr_offset_lsb];
else
-assign dmem_write_address = (refill == 1'b1)
- ? refill_address[ addr_set_msb:addr_set_lsb]
- : address_m[ addr_set_msb:addr_offset_lsb];
+assign dmem_write_address = (refill == 1'b1)
+ ? refill_address[addr_set_msb:addr_set_lsb]
+ : address_m[addr_set_msb:addr_offset_lsb];
endgenerate
-assign dmem_read_address = address_x[ addr_set_msb:addr_offset_lsb];
+assign dmem_read_address = address_x[addr_set_msb:addr_offset_lsb];
-assign tmem_write_address = (flushing == 1'b1)
+assign tmem_write_address = (flushing == 1'b1)
? flush_set
- : refill_address[ addr_set_msb:addr_set_lsb];
-assign tmem_read_address = address_x[ addr_set_msb:addr_set_lsb];
+ : refill_address[addr_set_msb:addr_set_lsb];
+assign tmem_read_address = address_x[addr_set_msb:addr_set_lsb];
generate
if (bytes_per_line > 4)
assign last_refill = refill_offset == {addr_offset_width{1'b1}};
else
-assign last_refill = 1'b1;
+assign last_refill = 1'b1;
endgenerate
-assign read_port_enable = (stall_x == 1'b0);
-assign write_port_enable = (refill_ready == 1'b1) || !stall_m;
+assign read_port_enable = (stall_x == 1'b0);
+assign write_port_enable = (refill_ready == 1'b1) || !stall_m;
-assign valid_store = (store_q_m == 1'b1) && (check == 1'b1);
+assign valid_store = (store_q_m == 1'b1) && (check == 1'b1);
generate
if (associativity == 1)
begin : we_1
-assign way_dmem_we[0] = (refill_ready == 1'b1) || ((valid_store == 1'b1) && (way_match[0] == 1'b1));
-assign way_tmem_we[0] = (refill_ready == 1'b1) || (flushing == 1'b1);
+assign way_dmem_we[0] = (refill_ready == 1'b1) || ((valid_store == 1'b1) && (way_match[0] == 1'b1));
+assign way_tmem_we[0] = (refill_ready == 1'b1) || (flushing == 1'b1);
end
else
begin : we_2
-assign way_dmem_we[0] = ((refill_ready == 1'b1) && (refill_way_select[0] == 1'b1)) || ((valid_store == 1'b1) && (way_match[0] == 1'b1));
-assign way_dmem_we[1] = ((refill_ready == 1'b1) && (refill_way_select[1] == 1'b1)) || ((valid_store == 1'b1) && (way_match[1] == 1'b1));
-assign way_tmem_we[0] = ((refill_ready == 1'b1) && (refill_way_select[0] == 1'b1)) || (flushing == 1'b1);
-assign way_tmem_we[1] = ((refill_ready == 1'b1) && (refill_way_select[1] == 1'b1)) || (flushing == 1'b1);
+assign way_dmem_we[0] = ((refill_ready == 1'b1) && (refill_way_select[0] == 1'b1)) || ((valid_store == 1'b1) && (way_match[0] == 1'b1));
+assign way_dmem_we[1] = ((refill_ready == 1'b1) && (refill_way_select[1] == 1'b1)) || ((valid_store == 1'b1) && (way_match[1] == 1'b1));
+assign way_tmem_we[0] = ((refill_ready == 1'b1) && (refill_way_select[0] == 1'b1)) || (flushing == 1'b1);
+assign way_tmem_we[1] = ((refill_ready == 1'b1) && (refill_way_select[1] == 1'b1)) || (flushing == 1'b1);
end
endgenerate
-assign tmem_write_data[ 0] = ((last_refill == 1'b1) || (valid_store == 1'b1)) && (flushing == 1'b0);
-assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+assign tmem_write_data[0] = ((last_refill == 1'b1) || (valid_store == 1'b1)) && (flushing == 1'b0);
+assign tmem_write_data[((addr_tag_width+1)-1):1] = refill_address[addr_tag_msb:addr_tag_lsb];
assign flushing = state[0];
assign check = state[1];
assign refill = state[2];
-assign miss = (~(|way_match)) && (load_q_m == 1'b1) && (stall_m == 1'b0);
-assign stall_request = (check == 1'b0);
+assign miss = (~(|way_match)) && (load_q_m == 1'b1) && (stall_m == 1'b0);
+assign stall_request = (check == 1'b0);
@@ -21747,13 +19613,13 @@ assign stall_request = (check == 1'b0);
generate
if (associativity >= 2)
begin : way_select
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
else
begin
- if (refill_request == 1'b1)
+ if (refill_request == 1'b1)
refill_way_select <= {refill_way_select[0], refill_way_select[1]};
end
end
@@ -21761,62 +19627,62 @@ end
endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- refilling <= 1'b0;
+ if (rst_i == 1'b1)
+ refilling <= 1'b0;
else
refilling <= refill;
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- state <= 3'b001;
- flush_set <= { addr_set_width{1'b1}};
- refill_request <= 1'b0;
- refill_address <= { 32{1'bx}};
- restart_request <= 1'b0;
+ state <= 3'b001;
+ flush_set <= {addr_set_width{1'b1}};
+ refill_request <= 1'b0;
+ refill_address <= {32{1'bx}};
+ restart_request <= 1'b0;
end
else
begin
case (state)
- 3'b001:
+ 3'b001:
begin
- if (flush_set == { addr_set_width{1'b0}})
- state <= 3'b010;
+ if (flush_set == {addr_set_width{1'b0}})
+ state <= 3'b010;
flush_set <= flush_set - 1'b1;
end
- 3'b010:
+ 3'b010:
begin
- if (stall_a == 1'b0)
- restart_request <= 1'b0;
- if (miss == 1'b1)
+ if (stall_a == 1'b0)
+ restart_request <= 1'b0;
+ if (miss == 1'b1)
begin
- refill_request <= 1'b1;
+ refill_request <= 1'b1;
refill_address <= address_m;
- state <= 3'b100;
+ state <= 3'b100;
end
- else if (dflush == 1'b1)
- state <= 3'b001;
+ else if (dflush == 1'b1)
+ state <= 3'b001;
end
- 3'b100:
+ 3'b100:
begin
- refill_request <= 1'b0;
- if (refill_ready == 1'b1)
+ refill_request <= 1'b0;
+ if (refill_ready == 1'b1)
begin
- if (last_refill == 1'b1)
+ if (last_refill == 1'b1)
begin
- restart_request <= 1'b1;
- state <= 3'b010;
+ restart_request <= 1'b1;
+ state <= 3'b010;
end
end
end
@@ -21829,25 +19695,25 @@ generate
if (bytes_per_line > 4)
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
else
begin
case (state)
- 3'b010:
+ 3'b010:
begin
- if (miss == 1'b1)
+ if (miss == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
end
- 3'b100:
+ 3'b100:
begin
- if (refill_ready == 1'b1)
+ if (refill_ready == 1'b1)
refill_offset <= refill_offset + 1'b1;
end
@@ -21859,9 +19725,6 @@ endgenerate
endmodule
-
-
-
@@ -21893,9 +19756,9 @@ endmodule
-
+
@@ -21926,9 +19789,8 @@ endmodule
-
-
+
@@ -22212,24 +20074,15 @@ endmodule
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
@@ -22246,32 +20099,24 @@ module lm32_debug_full_debug (
csr_write_enable_x,
csr_write_data,
csr_x,
-
-
+
jtag_csr_write_enable,
jtag_csr_write_data,
jtag_csr,
-
-
-
+
eret_q_x,
bret_q_x,
stall_x,
exception_x,
q_x,
-
-
- dcache_refill_request,
+ dcache_refill_request,
-
-
-
- dc_ss,
+ dc_ss,
dc_re,
bp_match,
@@ -22292,44 +20137,36 @@ parameter watchpoints = 0;
input clk_i;
input rst_i;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
input load_x;
input store_x;
-input [ (32-1):0] load_store_address_x;
+input [(32-1):0] load_store_address_x;
input csr_write_enable_x;
-input [ (32-1):0] csr_write_data;
-input [ (5-1):0] csr_x;
-
-
-input jtag_csr_write_enable;
-input [ (32-1):0] jtag_csr_write_data;
-input [ (5-1):0] jtag_csr;
+input [(32-1):0] csr_write_data;
+input [(5-1):0] csr_x;
+input jtag_csr_write_enable;
+input [(32-1):0] jtag_csr_write_data;
+input [(5-1):0] jtag_csr;
-
-
+
input eret_q_x;
input bret_q_x;
input stall_x;
input exception_x;
input q_x;
-
-
-input dcache_refill_request;
-
-
+input dcache_refill_request;
-
+
output dc_ss;
reg dc_ss;
-
output dc_re;
reg dc_re;
@@ -22346,33 +20183,29 @@ genvar i;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];
reg bp_e[0:breakpoints-1];
wire [0:breakpoints-1]bp_match_n;
-reg [ 1:0] wpc_c[0:watchpoints-1];
-reg [ (32-1):0] wp[0:watchpoints-1];
+reg [1:0] wpc_c[0:watchpoints-1];
+reg [(32-1):0] wp[0:watchpoints-1];
wire [0:watchpoints]wp_match_n;
wire debug_csr_write_enable;
-wire [ (32-1):0] debug_csr_write_data;
-wire [ (5-1):0] debug_csr;
-
-
-
-
-reg [ 2:0] state;
+wire [(32-1):0] debug_csr_write_data;
+wire [(5-1):0] debug_csr;
+reg [2:0] state;
-
+
@@ -22428,27 +20261,24 @@ endfunction
-
generate
for (i = 0; i < breakpoints; i = i + 1)
begin : bp_comb
-assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == 1'b1));
+assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == 1'b1));
end
endgenerate
generate
-
-
+
if (breakpoints > 0)
-assign bp_match = (|bp_match_n) || (state == 3'b011);
+assign bp_match = (|bp_match_n) || (state == 3'b011);
else
-assign bp_match = state == 3'b011;
-
+assign bp_match = state == 3'b011;
+
-
endgenerate
@@ -22462,16 +20292,15 @@ generate
if (watchpoints > 0)
assign wp_match = |wp_match_n;
else
-assign wp_match = 1'b0;
+assign wp_match = 1'b0;
endgenerate
-
-
+
+
+assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1);
+assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data;
+assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
-assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1);
-assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data;
-assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
-
@@ -22482,22 +20311,21 @@ assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
-
generate
for (i = 0; i < breakpoints; i = i + 1)
begin : bp_seq
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
- bp_e[i] <= 1'b0;
+ bp_a[i] <= {(clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+ bp_e[i] <= 1'b0;
end
else
begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i))
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i))
begin
- bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+ bp_a[i] <= debug_csr_write_data[((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
bp_e[i] <= debug_csr_write_data[0];
end
end
@@ -22509,20 +20337,20 @@ endgenerate
generate
for (i = 0; i < watchpoints; i = i + 1)
begin : wp_seq
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- wp[i] <= { 32{1'bx}};
- wpc_c[i] <= 2'b00;
+ wp[i] <= {32{1'bx}};
+ wpc_c[i] <= 2'b00;
end
else
begin
- if (debug_csr_write_enable == 1'b1)
+ if (debug_csr_write_enable == 1'b1)
begin
- if (debug_csr == 5'h8)
+ if (debug_csr == 5'h8)
wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
- if (debug_csr == 5'h18 + i)
+ if (debug_csr == 5'h18 + i)
wp[i] <= debug_csr_write_data;
end
end
@@ -22531,93 +20359,84 @@ end
endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- dc_re <= 1'b0;
+ if (rst_i == 1'b1)
+ dc_re <= 1'b0;
else
begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
dc_re <= debug_csr_write_data[1];
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- state <= 3'b000;
- dc_ss <= 1'b0;
+ state <= 3'b000;
+ dc_ss <= 1'b0;
end
else
begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
begin
dc_ss <= debug_csr_write_data[0];
- if (debug_csr_write_data[0] == 1'b0)
- state <= 3'b000;
+ if (debug_csr_write_data[0] == 1'b0)
+ state <= 3'b000;
else
- state <= 3'b001;
+ state <= 3'b001;
end
case (state)
- 3'b001:
+ 3'b001:
begin
- if ( ( (eret_q_x == 1'b1)
- || (bret_q_x == 1'b1)
+ if ( ( (eret_q_x == 1'b1)
+ || (bret_q_x == 1'b1)
)
- && (stall_x == 1'b0)
+ && (stall_x == 1'b0)
)
- state <= 3'b010;
+ state <= 3'b010;
end
- 3'b010:
+ 3'b010:
begin
- if ((q_x == 1'b1) && (stall_x == 1'b0))
- state <= 3'b011;
+ if ((q_x == 1'b1) && (stall_x == 1'b0))
+ state <= 3'b011;
end
- 3'b011:
+ 3'b011:
begin
-
-
- if (dcache_refill_request == 1'b1)
- state <= 3'b010;
- else
+ if (dcache_refill_request == 1'b1)
+ state <= 3'b010;
+ else
- if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
+ if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
begin
- dc_ss <= 1'b0;
- state <= 3'b100;
+ dc_ss <= 1'b0;
+ state <= 3'b100;
end
end
- 3'b100:
+ 3'b100:
begin
-
-
- if (dcache_refill_request == 1'b1)
- state <= 3'b010;
- else
+ if (dcache_refill_request == 1'b1)
+ state <= 3'b010;
+ else
- state <= 3'b000;
+ state <= 3'b000;
end
endcase
end
end
-
endmodule
-
-
-
@@ -22663,10 +20482,9 @@ endmodule
-
-
+
@@ -22696,9 +20514,9 @@ endmodule
-
+
@@ -22983,8 +20801,6 @@ endmodule
-
-
@@ -23003,50 +20819,39 @@ module lm32_instruction_unit_full_debug (
kill_f,
branch_predict_taken_d,
branch_predict_address_d,
-
-
+
branch_taken_x,
branch_target_x,
-
exception_m,
branch_taken_m,
branch_mispredict_taken_m,
branch_target_m,
-
-
- iflush,
+ iflush,
-
-
+
dcache_restart_request,
dcache_refill_request,
dcache_refilling,
-
-
+
-
-
-
+
i_dat_i,
i_ack_i,
i_err_i,
i_rty_i,
-
-
-
+
jtag_read_enable,
jtag_write_enable,
jtag_write_data,
jtag_address,
-
@@ -23055,20 +20860,16 @@ module lm32_instruction_unit_full_debug (
pc_x,
pc_m,
pc_w,
-
-
+
icache_stall_request,
icache_restart_request,
icache_refill_request,
icache_refilling,
-
-
+
-
-
-
+
i_dat_o,
i_adr_o,
@@ -23079,23 +20880,16 @@ module lm32_instruction_unit_full_debug (
i_cti_o,
i_lock_o,
i_bte_o,
-
-
-
+
jtag_read_data,
jtag_access_complete,
-
-
-
- bus_error_d,
+ bus_error_d,
-
-
- instruction_f,
+ instruction_f,
instruction_d
);
@@ -23132,74 +20926,62 @@ input valid_d;
input kill_f;
input branch_predict_taken_d;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
-
-
+
input branch_taken_x;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
-
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
input exception_m;
input branch_taken_m;
input branch_mispredict_taken_m;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
-
-
-input iflush;
+input iflush;
-
-
+
input dcache_restart_request;
input dcache_refill_request;
input dcache_refilling;
-
-
+
-
-
-
-input [ (32-1):0] i_dat_i;
+
+input [(32-1):0] i_dat_i;
input i_ack_i;
input i_err_i;
input i_rty_i;
-
-
-
+
input jtag_read_enable;
input jtag_write_enable;
-input [ 7:0] jtag_write_data;
-input [ (32-1):0] jtag_address;
-
+input [7:0] jtag_write_data;
+input [(32-1):0] jtag_address;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-
-
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
output icache_stall_request;
wire icache_stall_request;
output icache_restart_request;
@@ -23208,140 +20990,111 @@ output icache_refill_request;
wire icache_refill_request;
output icache_refilling;
wire icache_refilling;
-
-
+
-
-
-
-output [ (32-1):0] i_dat_o;
-
-
-reg [ (32-1):0] i_dat_o;
-
+output [(32-1):0] i_dat_o;
+
+reg [(32-1):0] i_dat_o;
+
-output [ (32-1):0] i_adr_o;
-reg [ (32-1):0] i_adr_o;
+output [(32-1):0] i_adr_o;
+reg [(32-1):0] i_adr_o;
output i_cyc_o;
reg i_cyc_o;
-output [ (4-1):0] i_sel_o;
-
-
-reg [ (4-1):0] i_sel_o;
+output [(4-1):0] i_sel_o;
-
+reg [(4-1):0] i_sel_o;
+
output i_stb_o;
reg i_stb_o;
output i_we_o;
-
-
-reg i_we_o;
-
+reg i_we_o;
+
-output [ (3-1):0] i_cti_o;
-reg [ (3-1):0] i_cti_o;
+output [(3-1):0] i_cti_o;
+reg [(3-1):0] i_cti_o;
output i_lock_o;
reg i_lock_o;
-output [ (2-1):0] i_bte_o;
-wire [ (2-1):0] i_bte_o;
-
-
+output [(2-1):0] i_bte_o;
+wire [(2-1):0] i_bte_o;
-
-output [ 7:0] jtag_read_data;
-reg [ 7:0] jtag_read_data;
+
+output [7:0] jtag_read_data;
+reg [7:0] jtag_read_data;
output jtag_access_complete;
wire jtag_access_complete;
-
-
-
+
output bus_error_d;
reg bus_error_d;
-
-
-
-output [ (32-1):0] instruction_f;
-wire [ (32-1):0] instruction_f;
+output [(32-1):0] instruction_f;
+wire [(32-1):0] instruction_f;
-output [ (32-1):0] instruction_d;
-reg [ (32-1):0] instruction_d;
+output [(32-1):0] instruction_d;
+reg [(32-1):0] instruction_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;
-
-
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;
-
-
+
wire icache_read_enable_f;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;
reg icache_refill_ready;
-reg [ (32-1):0] icache_refill_data;
-wire [ (32-1):0] icache_data_f;
-wire [ (3-1):0] first_cycle_type;
-wire [ (3-1):0] next_cycle_type;
+reg [(32-1):0] icache_refill_data;
+wire [(32-1):0] icache_data_f;
+wire [(3-1):0] first_cycle_type;
+wire [(3-1):0] next_cycle_type;
wire last_word;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;
-
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;
+
-
-
+
-
-
-
-
+
-
-
-reg bus_error_f;
+reg bus_error_f;
-
-
-reg jtag_access;
+reg jtag_access;
-
-
-
+
@@ -23397,8 +21150,7 @@ endfunction
-
-
+
@@ -23444,11 +21196,9 @@ endfunction
-
-
-
+
lm32_icache_full_debug #(
.associativity (associativity),
@@ -23478,84 +21228,68 @@ lm32_icache_full_debug #(
.refilling (icache_refilling),
.inst (icache_data_f)
);
-
-
-
-
-assign icache_read_enable_f = (valid_f == 1'b1)
- && (kill_f == 1'b0)
-
+
- && (dcache_restart_request == 1'b0)
+assign icache_read_enable_f = (valid_f == 1'b1)
+ && (kill_f == 1'b0)
+ && (dcache_restart_request == 1'b0)
-
+
-
;
-
always @(*)
begin
-
-
- if (dcache_restart_request == 1'b1)
+
+ if (dcache_restart_request == 1'b1)
pc_a = restart_address;
else
-
- if (branch_taken_m == 1'b1)
- if ((branch_mispredict_taken_m == 1'b1) && (exception_m == 1'b0))
+ if (branch_taken_m == 1'b1)
+ if ((branch_mispredict_taken_m == 1'b1) && (exception_m == 1'b0))
pc_a = pc_x;
else
pc_a = branch_target_m;
-
-
- else if (branch_taken_x == 1'b1)
+
+ else if (branch_taken_x == 1'b1)
pc_a = branch_target_x;
-
else
- if ( (valid_d == 1'b1) && (branch_predict_taken_d == 1'b1) )
+ if ( (valid_d == 1'b1) && (branch_predict_taken_d == 1'b1) )
pc_a = branch_predict_address_d;
else
-
-
- if (icache_restart_request == 1'b1)
+
+ if (icache_restart_request == 1'b1)
pc_a = restart_address;
else
-
pc_a = pc_f + 1'b1;
end
-
+
-
-
-
-
+
+
-
assign instruction_f = icache_data_f;
-
-
+
@@ -23568,50 +21302,43 @@ assign instruction_f = icache_data_f;
-
-
-
-
-
+
+
+assign i_bte_o = 2'b00;
-assign i_bte_o = 2'b00;
-
-
-
-
+
generate
case (bytes_per_line)
4:
begin
-assign first_cycle_type = 3'b111;
-assign next_cycle_type = 3'b111;
-assign last_word = 1'b1;
+assign first_cycle_type = 3'b111;
+assign next_cycle_type = 3'b111;
+assign last_word = 1'b1;
assign first_address = icache_refill_address;
end
8:
begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = 3'b111;
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = 3'b111;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
-assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+assign first_address = {icache_refill_address[(clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
end
16:
begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
-assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+assign first_address = {icache_refill_address[(clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
end
endcase
endgenerate
-
@@ -23619,67 +21346,61 @@ endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- pc_f <= ( 32'h00000000-4)/4;
- pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_f <= (32'h00000000-4)/4;
+ pc_d <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_x <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_m <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_w <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
end
else
begin
- if (stall_f == 1'b0)
+ if (stall_f == 1'b0)
pc_f <= pc_a;
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
pc_d <= pc_f;
- if (stall_x == 1'b0)
+ if (stall_x == 1'b0)
pc_x <= pc_d;
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
pc_m <= pc_x;
pc_w <= pc_m;
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ if (rst_i == 1'b1)
+ restart_address <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
else
begin
-
-
-
-
+
+
- if (dcache_refill_request == 1'b1)
+ if (dcache_refill_request == 1'b1)
restart_address <= pc_w;
- else if ((icache_refill_request == 1'b1) && (!dcache_refilling) && (!dcache_restart_request))
+ else if ((icache_refill_request == 1'b1) && (!dcache_refilling) && (!dcache_restart_request))
restart_address <= icache_refill_address;
-
+
-
-
end
end
-
-
+
@@ -23692,124 +21413,106 @@ end
-
-
-
-assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1);
+
+assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1);
always @(*)
begin
case (jtag_address[1:0])
- 2'b00: jtag_read_data = i_dat_i[ 31:24];
- 2'b01: jtag_read_data = i_dat_i[ 23:16];
- 2'b10: jtag_read_data = i_dat_i[ 15:8];
- 2'b11: jtag_read_data = i_dat_i[ 7:0];
+ 2'b00: jtag_read_data = i_dat_i[31:24];
+ 2'b01: jtag_read_data = i_dat_i[23:16];
+ 2'b10: jtag_read_data = i_dat_i[15:8];
+ 2'b11: jtag_read_data = i_dat_i[7:0];
endcase
end
-
-
-
+
-
-
-always @(posedge clk_i )
+
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_adr_o <= { 32{1'b0}};
- i_cti_o <= 3'b111;
- i_lock_o <= 1'b0;
- icache_refill_data <= { 32{1'b0}};
- icache_refill_ready <= 1'b0;
-
-
- bus_error_f <= 1'b0;
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_adr_o <= {32{1'b0}};
+ i_cti_o <= 3'b111;
+ i_lock_o <= 1'b0;
+ icache_refill_data <= {32{1'b0}};
+ icache_refill_ready <= 1'b0;
+ bus_error_f <= 1'b0;
-
-
- i_we_o <= 1'b0;
- i_sel_o <= 4'b1111;
- jtag_access <= 1'b0;
+ i_we_o <= 1'b0;
+ i_sel_o <= 4'b1111;
+ jtag_access <= 1'b0;
end
else
begin
- icache_refill_ready <= 1'b0;
+ icache_refill_ready <= 1'b0;
- if (i_cyc_o == 1'b1)
+ if (i_cyc_o == 1'b1)
begin
- if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
+ if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
begin
-
-
- if (jtag_access == 1'b1)
+
+ if (jtag_access == 1'b1)
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_we_o <= 1'b0;
- jtag_access <= 1'b0;
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_we_o <= 1'b0;
+ jtag_access <= 1'b0;
end
else
-
begin
- if (last_word == 1'b1)
+ if (last_word == 1'b1)
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_lock_o <= 1'b0;
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_lock_o <= 1'b0;
end
i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
i_cti_o <= next_cycle_type;
- icache_refill_ready <= 1'b1;
+ icache_refill_ready <= 1'b1;
icache_refill_data <= i_dat_i;
end
end
-
-
- if (i_err_i == 1'b1)
+
+ if (i_err_i == 1'b1)
begin
- bus_error_f <= 1'b1;
+ bus_error_f <= 1'b1;
$display ("Instruction bus error. Address: %x", i_adr_o);
end
-
end
else
begin
- if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
+ if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
begin
-
-
+
i_sel_o <= 4'b1111;
-
i_adr_o <= {first_address, 2'b00};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
i_cti_o <= first_cycle_type;
-
-
- bus_error_f <= 1'b0;
+ bus_error_f <= 1'b0;
end
-
-
+
else
begin
- if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1))
+ if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1))
begin
case (jtag_address[1:0])
2'b00: i_sel_o <= 4'b1000;
@@ -23819,33 +21522,28 @@ begin
endcase
i_adr_o <= jtag_address;
i_dat_o <= {4{jtag_write_data}};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
i_we_o <= jtag_write_enable;
- i_cti_o <= 3'b111;
- jtag_access <= 1'b1;
+ i_cti_o <= 3'b111;
+ jtag_access <= 1'b1;
end
end
-
-
-
+
-
-
- if (branch_taken_x == 1'b1)
- bus_error_f <= 1'b0;
-
+
+ if (branch_taken_x == 1'b1)
+ bus_error_f <= 1'b0;
- if (branch_taken_m == 1'b1)
- bus_error_f <= 1'b0;
-
+ if (branch_taken_m == 1'b1)
+ bus_error_f <= 1'b0;
end
end
end
-
+
@@ -23919,31 +21617,25 @@ end
-
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- instruction_d <= { 32{1'b0}};
-
-
- bus_error_d <= 1'b0;
+ instruction_d <= {32{1'b0}};
+ bus_error_d <= 1'b0;
end
else
begin
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
begin
instruction_d <= instruction_f;
-
-
- bus_error_d <= bus_error_f;
+ bus_error_d <= bus_error_f;
end
end
@@ -23978,10 +21670,7 @@ endmodule
-
-
-
-
+
@@ -24011,9 +21700,9 @@ endmodule
-
+
@@ -24297,57 +21986,33 @@ endmodule
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
-
+
+
+
+
+
+
+
+
+
+
@@ -24361,34 +22026,25 @@ module lm32_jtag_full_debug (
jtag_update,
jtag_reg_q,
jtag_reg_addr_q,
-
-
+
csr,
csr_write_enable,
csr_write_data,
stall_x,
-
-
-
+
jtag_read_data,
jtag_access_complete,
-
-
-
- exception_q_w,
+ exception_q_w,
-
-
+
jtx_csr_read_data,
jrx_csr_read_data,
-
-
-
+
jtag_csr_write_enable,
jtag_csr_write_data,
jtag_csr,
@@ -24396,13 +22052,10 @@ module lm32_jtag_full_debug (
jtag_write_enable,
jtag_write_data,
jtag_address,
-
-
-
+
jtag_break,
jtag_reset,
-
jtag_reg_d,
jtag_reg_addr_d
@@ -24417,69 +22070,57 @@ input rst_i;
input jtag_clk;
input jtag_update;
-input [ 7:0] jtag_reg_q;
+input [7:0] jtag_reg_q;
input [2:0] jtag_reg_addr_q;
-
-
-input [ (5-1):0] csr;
+
+input [(5-1):0] csr;
input csr_write_enable;
-input [ (32-1):0] csr_write_data;
+input [(32-1):0] csr_write_data;
input stall_x;
-
-
-
-input [ 7:0] jtag_read_data;
-input jtag_access_complete;
+input [7:0] jtag_read_data;
+input jtag_access_complete;
-
-
-input exception_q_w;
+input exception_q_w;
-
-
-output [ (32-1):0] jtx_csr_read_data;
-wire [ (32-1):0] jtx_csr_read_data;
-output [ (32-1):0] jrx_csr_read_data;
-wire [ (32-1):0] jrx_csr_read_data;
+output [(32-1):0] jtx_csr_read_data;
+wire [(32-1):0] jtx_csr_read_data;
+output [(32-1):0] jrx_csr_read_data;
+wire [(32-1):0] jrx_csr_read_data;
-
-
+
output jtag_csr_write_enable;
reg jtag_csr_write_enable;
-output [ (32-1):0] jtag_csr_write_data;
-wire [ (32-1):0] jtag_csr_write_data;
-output [ (5-1):0] jtag_csr;
-wire [ (5-1):0] jtag_csr;
+output [(32-1):0] jtag_csr_write_data;
+wire [(32-1):0] jtag_csr_write_data;
+output [(5-1):0] jtag_csr;
+wire [(5-1):0] jtag_csr;
output jtag_read_enable;
reg jtag_read_enable;
output jtag_write_enable;
reg jtag_write_enable;
-output [ 7:0] jtag_write_data;
-wire [ 7:0] jtag_write_data;
-output [ (32-1):0] jtag_address;
-wire [ (32-1):0] jtag_address;
-
-
-
+output [7:0] jtag_write_data;
+wire [7:0] jtag_write_data;
+output [(32-1):0] jtag_address;
+wire [(32-1):0] jtag_address;
+
output jtag_break;
reg jtag_break;
output jtag_reset;
reg jtag_reset;
-
-output [ 7:0] jtag_reg_d;
-reg [ 7:0] jtag_reg_d;
+output [7:0] jtag_reg_d;
+reg [7:0] jtag_reg_d;
output [2:0] jtag_reg_addr_d;
wire [2:0] jtag_reg_addr_d;
@@ -24494,66 +22135,54 @@ reg rx_update_r_r_r;
-wire [ 7:0] rx_byte;
+wire [7:0] rx_byte;
wire [2:0] rx_addr;
-
-
-reg [ 7:0] uart_tx_byte;
+
+reg [7:0] uart_tx_byte;
reg uart_tx_valid;
-reg [ 7:0] uart_rx_byte;
+reg [7:0] uart_rx_byte;
reg uart_rx_valid;
-
-reg [ 3:0] command;
-
-
-reg [ 7:0] jtag_byte_0;
-reg [ 7:0] jtag_byte_1;
-reg [ 7:0] jtag_byte_2;
-reg [ 7:0] jtag_byte_3;
-reg [ 7:0] jtag_byte_4;
-reg processing;
+reg [3:0] command;
+reg [7:0] jtag_byte_0;
+reg [7:0] jtag_byte_1;
+reg [7:0] jtag_byte_2;
+reg [7:0] jtag_byte_3;
+reg [7:0] jtag_byte_4;
+reg processing;
-reg [ 3:0] state;
-
+reg [3:0] state;
-
+
assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
-assign jtag_csr = jtag_byte_4[ (5-1):0];
+assign jtag_csr = jtag_byte_4[(5-1):0];
assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
assign jtag_write_data = jtag_byte_4;
-
-
-
+
assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
-
-
-
-
+
-assign jtag_reg_addr_d[2] = processing;
-
+assign jtag_reg_addr_d[2] = processing;
+
-
-
-assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
-assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
-
+
+assign jtx_csr_read_data = {{32-9{1'b0}}, uart_tx_valid, 8'h00};
+assign jrx_csr_read_data = {{32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
@@ -24565,9 +22194,9 @@ assign rx_addr = jtag_reg_addr_q;
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
rx_update <= 1'b0;
rx_update_r <= 1'b0;
@@ -24584,232 +22213,210 @@ begin
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- state <= 4'h0;
+ state <= 4'h0;
command <= 4'b0000;
jtag_reg_d <= 8'h00;
-
-
- processing <= 1'b0;
- jtag_csr_write_enable <= 1'b0;
- jtag_read_enable <= 1'b0;
- jtag_write_enable <= 1'b0;
+ processing <= 1'b0;
+ jtag_csr_write_enable <= 1'b0;
+ jtag_read_enable <= 1'b0;
+ jtag_write_enable <= 1'b0;
-
-
- jtag_break <= 1'b0;
- jtag_reset <= 1'b0;
+ jtag_break <= 1'b0;
+ jtag_reset <= 1'b0;
-
-
+
uart_tx_byte <= 8'h00;
- uart_tx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
uart_rx_byte <= 8'h00;
- uart_rx_valid <= 1'b0;
-
+ uart_rx_valid <= 1'b0;
end
else
begin
-
-
- if ((csr_write_enable == 1'b1) && (stall_x == 1'b0))
+
+ if ((csr_write_enable == 1'b1) && (stall_x == 1'b0))
begin
case (csr)
- 5'he:
+ 5'he:
begin
- uart_tx_byte <= csr_write_data[ 7:0];
- uart_tx_valid <= 1'b1;
+ uart_tx_byte <= csr_write_data[7:0];
+ uart_tx_valid <= 1'b1;
end
- 5'hf:
+ 5'hf:
begin
- uart_rx_valid <= 1'b0;
+ uart_rx_valid <= 1'b0;
end
endcase
end
-
-
-
+
- if (exception_q_w == 1'b1)
+ if (exception_q_w == 1'b1)
begin
- jtag_break <= 1'b0;
- jtag_reset <= 1'b0;
+ jtag_break <= 1'b0;
+ jtag_reset <= 1'b0;
end
-
case (state)
- 4'h0:
+ 4'h0:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
command <= rx_byte[7:4];
case (rx_addr)
-
-
- 3'b000:
+
+ 3'b000:
begin
case (rx_byte[7:4])
-
-
- 4'b0001:
- state <= 4'h1;
- 4'b0011:
+
+ 4'b0001:
+ state <= 4'h1;
+ 4'b0011:
begin
{jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
- state <= 4'h6;
+ state <= 4'h6;
end
- 4'b0010:
- state <= 4'h1;
- 4'b0100:
+ 4'b0010:
+ state <= 4'h1;
+ 4'b0100:
begin
{jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
state <= 5;
end
- 4'b0101:
- state <= 4'h1;
-
+ 4'b0101:
+ state <= 4'h1;
- 4'b0110:
+ 4'b0110:
begin
-
-
- uart_rx_valid <= 1'b0;
- uart_tx_valid <= 1'b0;
-
+
+ uart_rx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
- jtag_break <= 1'b1;
+ jtag_break <= 1'b1;
end
- 4'b0111:
+ 4'b0111:
begin
-
-
- uart_rx_valid <= 1'b0;
- uart_tx_valid <= 1'b0;
-
+
+ uart_rx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
- jtag_reset <= 1'b1;
+ jtag_reset <= 1'b1;
end
endcase
end
-
-
-
- 3'b001:
+
+ 3'b001:
begin
uart_rx_byte <= rx_byte;
- uart_rx_valid <= 1'b1;
+ uart_rx_valid <= 1'b1;
end
- 3'b010:
+ 3'b010:
begin
jtag_reg_d <= uart_tx_byte;
- uart_tx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
end
-
default:
;
endcase
end
end
-
-
- 4'h1:
+
+ 4'h1:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
jtag_byte_0 <= rx_byte;
- state <= 4'h2;
+ state <= 4'h2;
end
end
- 4'h2:
+ 4'h2:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
jtag_byte_1 <= rx_byte;
- state <= 4'h3;
+ state <= 4'h3;
end
end
- 4'h3:
+ 4'h3:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
jtag_byte_2 <= rx_byte;
- state <= 4'h4;
+ state <= 4'h4;
end
end
- 4'h4:
+ 4'h4:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
jtag_byte_3 <= rx_byte;
- if (command == 4'b0001)
- state <= 4'h6;
+ if (command == 4'b0001)
+ state <= 4'h6;
else
- state <= 4'h5;
+ state <= 4'h5;
end
end
- 4'h5:
+ 4'h5:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
jtag_byte_4 <= rx_byte;
- state <= 4'h6;
+ state <= 4'h6;
end
end
- 4'h6:
+ 4'h6:
begin
case (command)
- 4'b0001,
- 4'b0011:
+ 4'b0001,
+ 4'b0011:
begin
- jtag_read_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h7;
+ jtag_read_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h7;
end
- 4'b0010,
- 4'b0100:
+ 4'b0010,
+ 4'b0100:
begin
- jtag_write_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h7;
+ jtag_write_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h7;
end
- 4'b0101:
+ 4'b0101:
begin
- jtag_csr_write_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h8;
+ jtag_csr_write_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h8;
end
endcase
end
- 4'h7:
+ 4'h7:
begin
- if (jtag_access_complete == 1'b1)
+ if (jtag_access_complete == 1'b1)
begin
- jtag_read_enable <= 1'b0;
+ jtag_read_enable <= 1'b0;
jtag_reg_d <= jtag_read_data;
- jtag_write_enable <= 1'b0;
- processing <= 1'b0;
- state <= 4'h0;
+ jtag_write_enable <= 1'b0;
+ processing <= 1'b0;
+ state <= 4'h0;
end
end
- 4'h8:
+ 4'h8:
begin
- jtag_csr_write_enable <= 1'b0;
- processing <= 1'b0;
- state <= 4'h0;
+ jtag_csr_write_enable <= 1'b0;
+ processing <= 1'b0;
+ state <= 4'h0;
end
-
endcase
end
@@ -24817,8 +22424,6 @@ end
endmodule
-
-
@@ -24847,10 +22452,8 @@ endmodule
-
-
-
+
@@ -24880,9 +22483,9 @@ endmodule
-
+
@@ -25167,8 +22770,6 @@ endmodule
-
-
@@ -25180,19 +22781,15 @@ module lm32_interrupt_full_debug (
interrupt,
stall_x,
-
-
+
non_debug_exception,
debug_exception,
-
-
+
eret_q_x,
-
-
- bret_q_x,
+ bret_q_x,
csr,
csr_write_data,
@@ -25207,7 +22804,7 @@ module lm32_interrupt_full_debug (
-parameter interrupts = 32;
+parameter interrupts = 32;
@@ -25220,23 +22817,19 @@ input [interrupts-1:0] interrupt;
input stall_x;
-
-
+
input non_debug_exception;
input debug_exception;
-
-
+
input eret_q_x;
-
-
-input bret_q_x;
+input bret_q_x;
-input [ (5-1):0] csr;
-input [ (32-1):0] csr_write_data;
+input [(5-1):0] csr;
+input [(32-1):0] csr_write_data;
input csr_write_enable;
@@ -25246,8 +22839,8 @@ input csr_write_enable;
output interrupt_exception;
wire interrupt_exception;
-output [ (32-1):0] csr_read_data;
-reg [ (32-1):0] csr_read_data;
+output [(32-1):0] csr_read_data;
+reg [(32-1):0] csr_read_data;
@@ -25261,10 +22854,8 @@ wire [interrupts-1:0] interrupt_n_exception;
reg ie;
reg eie;
-
-
-reg bie;
+reg bie;
reg [interrupts-1:0] ip;
reg [interrupts-1:0] im;
@@ -25282,13 +22873,11 @@ assign interrupt_exception = (|interrupt_n_exception) & ie;
assign asserted = ip | interrupt;
-assign ie_csr_read_data = {{ 32-3{1'b0}},
-
-
- bie,
+assign ie_csr_read_data = {{32-3{1'b0}},
-
+ bie,
+
eie,
ie
@@ -25302,20 +22891,18 @@ generate
always @(*)
begin
case (csr)
- 5'h0: csr_read_data = {{ 32-3{1'b0}},
-
-
- bie,
+ 5'h0: csr_read_data = {{32-3{1'b0}},
-
+ bie,
+
eie,
ie
};
- 5'h2: csr_read_data = ip;
- 5'h1: csr_read_data = im;
- default: csr_read_data = { 32{1'bx}};
+ 5'h2: csr_read_data = ip;
+ 5'h1: csr_read_data = im;
+ default: csr_read_data = {32{1'bx}};
endcase
end
end
@@ -25325,19 +22912,17 @@ end
always @(*)
begin
case (csr)
- 5'h0: csr_read_data = {{ 32-3{1'b0}},
-
-
- bie,
+ 5'h0: csr_read_data = {{32-3{1'b0}},
-
+ bie,
+
eie,
ie
};
- 5'h2: csr_read_data = ip;
- default: csr_read_data = { 32{1'bx}};
+ 5'h2: csr_read_data = ip;
+ default: csr_read_data = {32{1'bx}};
endcase
end
end
@@ -25347,9 +22932,8 @@ endgenerate
-
-
- reg [ 10:0] eie_delay = 0;
+
+ reg [10:0] eie_delay = 0;
generate
@@ -25358,16 +22942,14 @@ generate
if (interrupts > 1)
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- ie <= 1'b0;
- eie <= 1'b0;
-
-
- bie <= 1'b0;
+ ie <= 1'b0;
+ eie <= 1'b0;
+ bie <= 1'b0;
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
@@ -25378,21 +22960,20 @@ always @(posedge clk_i )
begin
ip <= asserted;
-
-
- if (non_debug_exception == 1'b1)
+
+ if (non_debug_exception == 1'b1)
begin
eie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
- else if (debug_exception == 1'b1)
+ else if (debug_exception == 1'b1)
begin
bie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
-
+
@@ -25400,46 +22981,41 @@ always @(posedge clk_i )
-
- else if (stall_x == 1'b0)
+ else if (stall_x == 1'b0)
begin
if(eie_delay[0])
ie <= eie;
- eie_delay <= {1'b0, eie_delay[ 10:1]};
+ eie_delay <= {1'b0, eie_delay[10:1]};
- if (eret_q_x == 1'b1) begin
+ if (eret_q_x == 1'b1) begin
- eie_delay[ 10] <= 1'b1;
- eie_delay[ 10-1:0] <= 0;
+ eie_delay[10] <= 1'b1;
+ eie_delay[10-1:0] <= 0;
end
-
-
- else if (bret_q_x == 1'b1)
+
+ else if (bret_q_x == 1'b1)
ie <= bie;
-
- else if (csr_write_enable == 1'b1)
+ else if (csr_write_enable == 1'b1)
begin
- if (csr == 5'h0)
+ if (csr == 5'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
-
- bie <= csr_write_data[2];
+ bie <= csr_write_data[2];
end
- if (csr == 5'h1)
+ if (csr == 5'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 5'h2)
+ if (csr == 5'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -25449,16 +23025,14 @@ end
else
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- ie <= 1'b0;
- eie <= 1'b0;
-
-
- bie <= 1'b0;
+ ie <= 1'b0;
+ eie <= 1'b0;
+ bie <= 1'b0;
ip <= {interrupts{1'b0}};
eie_delay <= 0;
@@ -25467,21 +23041,20 @@ always @(posedge clk_i )
begin
ip <= asserted;
-
-
- if (non_debug_exception == 1'b1)
+
+ if (non_debug_exception == 1'b1)
begin
eie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
- else if (debug_exception == 1'b1)
+ else if (debug_exception == 1'b1)
begin
bie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
-
+
@@ -25489,42 +23062,37 @@ always @(posedge clk_i )
-
- else if (stall_x == 1'b0)
+ else if (stall_x == 1'b0)
begin
if(eie_delay[0])
ie <= eie;
- eie_delay <= {1'b0, eie_delay[ 10:1]};
+ eie_delay <= {1'b0, eie_delay[10:1]};
- if (eret_q_x == 1'b1) begin
+ if (eret_q_x == 1'b1) begin
- eie_delay[ 10] <= 1'b1;
- eie_delay[ 10-1:0] <= 0;
+ eie_delay[10] <= 1'b1;
+ eie_delay[10-1:0] <= 0;
end
-
-
- else if (bret_q_x == 1'b1)
+
+ else if (bret_q_x == 1'b1)
ie <= bie;
-
- else if (csr_write_enable == 1'b1)
+ else if (csr_write_enable == 1'b1)
begin
- if (csr == 5'h0)
+ if (csr == 5'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
-
- bie <= csr_write_data[2];
+ bie <= csr_write_data[2];
end
- if (csr == 5'h2)
+ if (csr == 5'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -25564,48 +23132,26 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -25614,26 +23160,8 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
@@ -25651,273 +23179,197 @@ endmodule
-
-
-
-
-
-
-
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
-
-
+
+
-
+
+
+
+
+
+
-
-
+
+
+
-
+
+
+
-
-
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
-
-
-
-
-
-
+
+
+
+
-
-
-
-
+
+
-
+
+
-
+
+
-
-
-
+
+
-
+
+
-
+
-
-
+
-
-
+
+
+
+
+
+
+
+
+
+
-
+
+
+
+
+
+
-
+
-
-
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
-
-
-
-
+
+
-
-
+
@@ -25926,156 +23378,100 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
-
-
+
+
+
+
-
-
-
+
+
+
-
-
+
+
+
+
-
-
+
+
+
+
-
-
+
+
+
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
@@ -26094,19 +23490,16 @@ module lm32_top_medium (
interrupt,
-
+
-
-
-
+
I_DAT_I,
I_ACK_I,
I_ERR_I,
I_RTY_I,
-
D_DAT_I,
@@ -26114,15 +23507,13 @@ module lm32_top_medium (
D_ERR_I,
D_RTY_I,
-
+
-
-
-
+
I_DAT_O,
I_ADR_O,
@@ -26133,7 +23524,6 @@ module lm32_top_medium (
I_CTI_O,
I_LOCK_O,
I_BTE_O,
-
D_DAT_O,
@@ -26155,25 +23545,22 @@ input clk_i;
input rst_i;
-input [ (32-1):0] interrupt;
+input [(32-1):0] interrupt;
-
+
-
-
-
-input [ (32-1):0] I_DAT_I;
+
+input [(32-1):0] I_DAT_I;
input I_ACK_I;
input I_ERR_I;
input I_RTY_I;
-
-input [ (32-1):0] D_DAT_I;
+input [(32-1):0] D_DAT_I;
input D_ACK_I;
input D_ERR_I;
input D_RTY_I;
@@ -26182,7 +23569,7 @@ input D_RTY_I;
-
+
@@ -26193,54 +23580,51 @@ input D_RTY_I;
-
-
-
-output [ (32-1):0] I_DAT_O;
-wire [ (32-1):0] I_DAT_O;
-output [ (32-1):0] I_ADR_O;
-wire [ (32-1):0] I_ADR_O;
+
+output [(32-1):0] I_DAT_O;
+wire [(32-1):0] I_DAT_O;
+output [(32-1):0] I_ADR_O;
+wire [(32-1):0] I_ADR_O;
output I_CYC_O;
wire I_CYC_O;
-output [ (4-1):0] I_SEL_O;
-wire [ (4-1):0] I_SEL_O;
+output [(4-1):0] I_SEL_O;
+wire [(4-1):0] I_SEL_O;
output I_STB_O;
wire I_STB_O;
output I_WE_O;
wire I_WE_O;
-output [ (3-1):0] I_CTI_O;
-wire [ (3-1):0] I_CTI_O;
+output [(3-1):0] I_CTI_O;
+wire [(3-1):0] I_CTI_O;
output I_LOCK_O;
wire I_LOCK_O;
-output [ (2-1):0] I_BTE_O;
-wire [ (2-1):0] I_BTE_O;
-
+output [(2-1):0] I_BTE_O;
+wire [(2-1):0] I_BTE_O;
-output [ (32-1):0] D_DAT_O;
-wire [ (32-1):0] D_DAT_O;
-output [ (32-1):0] D_ADR_O;
-wire [ (32-1):0] D_ADR_O;
+output [(32-1):0] D_DAT_O;
+wire [(32-1):0] D_DAT_O;
+output [(32-1):0] D_ADR_O;
+wire [(32-1):0] D_ADR_O;
output D_CYC_O;
wire D_CYC_O;
-output [ (4-1):0] D_SEL_O;
-wire [ (4-1):0] D_SEL_O;
+output [(4-1):0] D_SEL_O;
+wire [(4-1):0] D_SEL_O;
output D_STB_O;
wire D_STB_O;
output D_WE_O;
wire D_WE_O;
-output [ (3-1):0] D_CTI_O;
-wire [ (3-1):0] D_CTI_O;
+output [(3-1):0] D_CTI_O;
+wire [(3-1):0] D_CTI_O;
output D_LOCK_O;
wire D_LOCK_O;
-output [ (2-1):0] D_BTE_O;
-wire [ (2-1):0] D_BTE_O;
+output [(2-1):0] D_BTE_O;
+wire [(2-1):0] D_BTE_O;
-
+
@@ -26252,8 +23636,7 @@ wire [ (2-1):0] D_BTE_O;
-
-
+
@@ -26269,10 +23652,7 @@ wire [ (2-1):0] D_BTE_O;
-
-
-
-
+
@@ -26325,45 +23705,37 @@ endfunction
-
lm32_cpu_medium cpu (
.clk_i (clk_i),
-
+
-
.rst_i (rst_i),
-
-
- .interrupt (interrupt),
+ .interrupt (interrupt),
-
+
-
-
+
-
-
-
+
.I_DAT_I (I_DAT_I),
.I_ACK_I (I_ACK_I),
.I_ERR_I (I_ERR_I),
.I_RTY_I (I_RTY_I),
-
.D_DAT_I (D_DAT_I),
@@ -26371,7 +23743,7 @@ lm32_cpu_medium cpu (
.D_ERR_I (D_ERR_I),
.D_RTY_I (D_RTY_I),
-
+
@@ -26381,21 +23753,17 @@ lm32_cpu_medium cpu (
-
-
+
-
-
+
-
-
-
+
.I_DAT_O (I_DAT_O),
.I_ADR_O (I_ADR_O),
@@ -26406,8 +23774,7 @@ lm32_cpu_medium cpu (
.I_CTI_O (I_CTI_O),
.I_LOCK_O (I_LOCK_O),
.I_BTE_O (I_BTE_O),
-
-
+
.D_DAT_O (D_DAT_O),
.D_ADR_O (D_ADR_O),
@@ -26420,7 +23787,7 @@ lm32_cpu_medium cpu (
.D_BTE_O (D_BTE_O)
);
-
+
@@ -26433,7 +23800,6 @@ lm32_cpu_medium cpu (
-
endmodule
@@ -26465,9 +23831,7 @@ endmodule
-
-
-
+
@@ -26498,9 +23862,8 @@ endmodule
-
-
+
@@ -26782,24 +24145,15 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
@@ -26811,29 +24165,25 @@ module lm32_mc_arithmetic_medium (
rst_i,
stall_d,
kill_x,
-
+
-
-
+
-
-
+
-
operand_0_d,
operand_1_d,
result_x,
-
+
-
stall_request_x
);
@@ -26845,35 +24195,31 @@ input clk_i;
input rst_i;
input stall_d;
input kill_x;
-
+
-
-
+
-
-
+
-
-input [ (32-1):0] operand_0_d;
-input [ (32-1):0] operand_1_d;
+input [(32-1):0] operand_0_d;
+input [(32-1):0] operand_1_d;
-output [ (32-1):0] result_x;
-reg [ (32-1):0] result_x;
-
+output [(32-1):0] result_x;
+reg [(32-1):0] result_x;
+
-
output stall_request_x;
wire stall_request_x;
@@ -26881,18 +24227,17 @@ wire stall_request_x;
-reg [ (32-1):0] p;
-reg [ (32-1):0] a;
-reg [ (32-1):0] b;
-
+reg [(32-1):0] p;
+reg [(32-1):0] a;
+reg [(32-1):0] b;
+
-
-reg [ 2:0] state;
+reg [2:0] state;
reg [5:0] cycles;
-
+
@@ -26902,16 +24247,14 @@ reg [5:0] cycles;
+assign stall_request_x = state != 3'b000;
-assign stall_request_x = state != 3'b000;
-
-
+
-
-
+
@@ -26921,54 +24264,48 @@ assign stall_request_x = state != 3'b000;
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
cycles <= {6{1'b0}};
- p <= { 32{1'b0}};
- a <= { 32{1'b0}};
- b <= { 32{1'b0}};
-
+ p <= {32{1'b0}};
+ a <= {32{1'b0}};
+ b <= {32{1'b0}};
+
-
-
+
-
- result_x <= { 32{1'b0}};
- state <= 3'b000;
+ result_x <= {32{1'b0}};
+ state <= 3'b000;
end
else
begin
-
+
-
case (state)
- 3'b000:
+ 3'b000:
begin
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
begin
- cycles <= 32;
+ cycles <= 32;
p <= 32'b0;
a <= operand_0_d;
b <= operand_1_d;
-
+
-
-
+
-
-
+
@@ -26985,11 +24322,10 @@ begin
-
end
end
-
+
@@ -27032,9 +24368,8 @@ begin
-
-
+
@@ -27046,9 +24381,8 @@ begin
-
-
+
@@ -27065,7 +24399,6 @@ begin
-
endcase
end
@@ -27136,10 +24469,7 @@ endmodule
-
-
-
-
+
@@ -27169,9 +24499,9 @@ endmodule
-
+
@@ -27456,47 +24786,38 @@ endmodule
-
-
module lm32_cpu_medium (
clk_i,
-
+
-
rst_i,
-
-
- interrupt,
+ interrupt,
-
+
-
-
+
-
-
-
+
I_DAT_I,
I_ACK_I,
I_ERR_I,
I_RTY_I,
-
D_DAT_I,
@@ -27504,7 +24825,7 @@ module lm32_cpu_medium (
D_ERR_I,
D_RTY_I,
-
+
@@ -27514,21 +24835,17 @@ module lm32_cpu_medium (
-
-
+
-
-
+
-
-
-
+
I_DAT_O,
I_ADR_O,
@@ -27539,7 +24856,6 @@ module lm32_cpu_medium (
I_CTI_O,
I_LOCK_O,
I_BTE_O,
-
D_DAT_O,
@@ -27557,65 +24873,54 @@ module lm32_cpu_medium (
-parameter eba_reset = 32'h00000000;
-
+parameter eba_reset = 32'h00000000;
+
-
-
+
-
parameter icache_associativity = 1;
parameter icache_sets = 512;
parameter icache_bytes_per_line = 16;
parameter icache_base_address = 0;
parameter icache_limit = 0;
-
-
+
-
parameter dcache_associativity = 1;
parameter dcache_sets = 512;
parameter dcache_bytes_per_line = 16;
parameter dcache_base_address = 0;
parameter dcache_limit = 0;
-
-
+
-
parameter watchpoints = 0;
-
-
+
-
parameter breakpoints = 0;
-
-
-
-parameter interrupts = 32;
-
+parameter interrupts = 32;
+
@@ -27623,42 +24928,35 @@ parameter interrupts = 32;
input clk_i;
-
+
-
input rst_i;
-
-
-input [ (32-1):0] interrupt;
+input [(32-1):0] interrupt;
-
+
-
-
+
-
-
-
-input [ (32-1):0] I_DAT_I;
+
+input [(32-1):0] I_DAT_I;
input I_ACK_I;
input I_ERR_I;
input I_RTY_I;
-
-input [ (32-1):0] D_DAT_I;
+input [(32-1):0] D_DAT_I;
input D_ACK_I;
input D_ERR_I;
input D_RTY_I;
@@ -27667,7 +24965,7 @@ input D_RTY_I;
-
+
@@ -27684,16 +24982,14 @@ input D_RTY_I;
-
-
+
-
-
+
@@ -27704,48 +25000,45 @@ input D_RTY_I;
-
-
-
-output [ (32-1):0] I_DAT_O;
-wire [ (32-1):0] I_DAT_O;
-output [ (32-1):0] I_ADR_O;
-wire [ (32-1):0] I_ADR_O;
+
+output [(32-1):0] I_DAT_O;
+wire [(32-1):0] I_DAT_O;
+output [(32-1):0] I_ADR_O;
+wire [(32-1):0] I_ADR_O;
output I_CYC_O;
wire I_CYC_O;
-output [ (4-1):0] I_SEL_O;
-wire [ (4-1):0] I_SEL_O;
+output [(4-1):0] I_SEL_O;
+wire [(4-1):0] I_SEL_O;
output I_STB_O;
wire I_STB_O;
output I_WE_O;
wire I_WE_O;
-output [ (3-1):0] I_CTI_O;
-wire [ (3-1):0] I_CTI_O;
+output [(3-1):0] I_CTI_O;
+wire [(3-1):0] I_CTI_O;
output I_LOCK_O;
wire I_LOCK_O;
-output [ (2-1):0] I_BTE_O;
-wire [ (2-1):0] I_BTE_O;
-
+output [(2-1):0] I_BTE_O;
+wire [(2-1):0] I_BTE_O;
-output [ (32-1):0] D_DAT_O;
-wire [ (32-1):0] D_DAT_O;
-output [ (32-1):0] D_ADR_O;
-wire [ (32-1):0] D_ADR_O;
+output [(32-1):0] D_DAT_O;
+wire [(32-1):0] D_DAT_O;
+output [(32-1):0] D_ADR_O;
+wire [(32-1):0] D_ADR_O;
output D_CYC_O;
wire D_CYC_O;
-output [ (4-1):0] D_SEL_O;
-wire [ (4-1):0] D_SEL_O;
+output [(4-1):0] D_SEL_O;
+wire [(4-1):0] D_SEL_O;
output D_STB_O;
wire D_STB_O;
output D_WE_O;
wire D_WE_O;
-output [ (3-1):0] D_CTI_O;
-wire [ (3-1):0] D_CTI_O;
+output [(3-1):0] D_CTI_O;
+wire [(3-1):0] D_CTI_O;
output D_LOCK_O;
wire D_LOCK_O;
-output [ (2-1):0] D_BTE_O;
-wire [ (2-1):0] D_BTE_O;
+output [(2-1):0] D_BTE_O;
+wire [(2-1):0] D_BTE_O;
@@ -27753,10 +25046,9 @@ wire [ (2-1):0] D_BTE_O;
-
+
-
reg valid_f;
reg valid_d;
reg valid_x;
@@ -27764,7 +25056,7 @@ reg valid_m;
reg valid_w;
wire q_x;
-wire [ (32-1):0] immediate_d;
+wire [(32-1):0] immediate_d;
wire load_d;
reg load_x;
reg load_m;
@@ -27773,13 +25065,13 @@ wire store_q_x;
wire store_d;
reg store_x;
reg store_m;
-wire [ 1:0] size_d;
-reg [ 1:0] size_x;
+wire [1:0] size_d;
+reg [1:0] size_x;
wire branch_d;
wire branch_predict_d;
wire branch_predict_taken_d;
-wire [ ((32-2)+2-1):2] branch_predict_address_d;
-wire [ ((32-2)+2-1):2] branch_target_d;
+wire [((32-2)+2-1):2] branch_predict_address_d;
+wire [((32-2)+2-1):2] branch_target_d;
wire bi_unconditional;
wire bi_conditional;
reg branch_x;
@@ -27791,60 +25083,51 @@ reg branch_predict_taken_m;
wire branch_mispredict_taken_m;
wire branch_flushX_m;
wire branch_reg_d;
-wire [ ((32-2)+2-1):2] branch_offset_d;
-reg [ ((32-2)+2-1):2] branch_target_x;
-reg [ ((32-2)+2-1):2] branch_target_m;
-wire [ 0:0] d_result_sel_0_d;
-wire [ 1:0] d_result_sel_1_d;
+wire [((32-2)+2-1):2] branch_offset_d;
+reg [((32-2)+2-1):2] branch_target_x;
+reg [((32-2)+2-1):2] branch_target_m;
+wire [0:0] d_result_sel_0_d;
+wire [1:0] d_result_sel_1_d;
wire x_result_sel_csr_d;
reg x_result_sel_csr_x;
-
+
-
-
+
-
-
-
+
wire x_result_sel_sext_d;
reg x_result_sel_sext_x;
-
wire x_result_sel_logic_d;
reg x_result_sel_logic_x;
-
+
-
wire x_result_sel_add_d;
reg x_result_sel_add_x;
wire m_result_sel_compare_d;
reg m_result_sel_compare_x;
reg m_result_sel_compare_m;
-
-
+
wire m_result_sel_shift_d;
reg m_result_sel_shift_x;
reg m_result_sel_shift_m;
-
wire w_result_sel_load_d;
reg w_result_sel_load_x;
reg w_result_sel_load_m;
reg w_result_sel_load_w;
-
-
+
wire w_result_sel_mul_d;
reg w_result_sel_mul_x;
reg w_result_sel_mul_m;
reg w_result_sel_mul_w;
-
wire x_bypass_enable_d;
reg x_bypass_enable_x;
@@ -27861,33 +25144,31 @@ wire write_enable_q_m;
reg write_enable_w;
wire write_enable_q_w;
wire read_enable_0_d;
-wire [ (5-1):0] read_idx_0_d;
+wire [(5-1):0] read_idx_0_d;
wire read_enable_1_d;
-wire [ (5-1):0] read_idx_1_d;
-wire [ (5-1):0] write_idx_d;
-reg [ (5-1):0] write_idx_x;
-reg [ (5-1):0] write_idx_m;
-reg [ (5-1):0] write_idx_w;
-wire [ (3-1):0] csr_d;
-reg [ (3-1):0] csr_x;
-wire [ (3-1):0] condition_d;
-reg [ (3-1):0] condition_x;
-
+wire [(5-1):0] read_idx_1_d;
+wire [(5-1):0] write_idx_d;
+reg [(5-1):0] write_idx_x;
+reg [(5-1):0] write_idx_m;
+reg [(5-1):0] write_idx_w;
+wire [(3-1):0] csr_d;
+reg [(3-1):0] csr_x;
+wire [(3-1):0] condition_d;
+reg [(3-1):0] condition_x;
+
-
wire scall_d;
reg scall_x;
wire eret_d;
reg eret_x;
wire eret_q_x;
reg eret_m;
-
+
-
-
+
@@ -27896,55 +25177,48 @@ reg eret_m;
-
wire csr_write_enable_d;
reg csr_write_enable_x;
wire csr_write_enable_q_x;
-
+
-
-
+
+reg [(32-1):0] d_result_0;
+reg [(32-1):0] d_result_1;
+reg [(32-1):0] x_result;
+reg [(32-1):0] m_result;
+reg [(32-1):0] w_result;
-reg [ (32-1):0] d_result_0;
-reg [ (32-1):0] d_result_1;
-reg [ (32-1):0] x_result;
-reg [ (32-1):0] m_result;
-reg [ (32-1):0] w_result;
-
-reg [ (32-1):0] operand_0_x;
-reg [ (32-1):0] operand_1_x;
-reg [ (32-1):0] store_operand_x;
-reg [ (32-1):0] operand_m;
-reg [ (32-1):0] operand_w;
+reg [(32-1):0] operand_0_x;
+reg [(32-1):0] operand_1_x;
+reg [(32-1):0] store_operand_x;
+reg [(32-1):0] operand_m;
+reg [(32-1):0] operand_w;
-
-
-reg [ (32-1):0] reg_data_live_0;
-reg [ (32-1):0] reg_data_live_1;
-reg use_buf;
-reg [ (32-1):0] reg_data_buf_0;
-reg [ (32-1):0] reg_data_buf_1;
-
-
+reg [(32-1):0] reg_data_live_0;
+reg [(32-1):0] reg_data_live_1;
+reg use_buf;
+reg [(32-1):0] reg_data_buf_0;
+reg [(32-1):0] reg_data_buf_1;
-
+
-wire [ (32-1):0] reg_data_0;
-wire [ (32-1):0] reg_data_1;
-reg [ (32-1):0] bypass_data_0;
-reg [ (32-1):0] bypass_data_1;
+wire [(32-1):0] reg_data_0;
+wire [(32-1):0] reg_data_1;
+reg [(32-1):0] bypass_data_0;
+reg [(32-1):0] bypass_data_1;
wire reg_write_enable_q_w;
reg interlock;
@@ -27959,64 +25233,54 @@ wire stall_m;
wire adder_op_d;
reg adder_op_x;
reg adder_op_x_n;
-wire [ (32-1):0] adder_result_x;
+wire [(32-1):0] adder_result_x;
wire adder_overflow_x;
wire adder_carry_n_x;
-wire [ 3:0] logic_op_d;
-reg [ 3:0] logic_op_x;
-wire [ (32-1):0] logic_result_x;
+wire [3:0] logic_op_d;
+reg [3:0] logic_op_x;
+wire [(32-1):0] logic_result_x;
-
-
-
-wire [ (32-1):0] sextb_result_x;
-wire [ (32-1):0] sexth_result_x;
-wire [ (32-1):0] sext_result_x;
+wire [(32-1):0] sextb_result_x;
+wire [(32-1):0] sexth_result_x;
+wire [(32-1):0] sext_result_x;
-
-
+
+
-
wire direction_d;
reg direction_x;
reg direction_m;
-wire [ (32-1):0] shifter_result_m;
-
+wire [(32-1):0] shifter_result_m;
-
+
-
-
+
-
-
-
-wire [ (32-1):0] multiplier_result_w;
+wire [(32-1):0] multiplier_result_w;
-
+
-
-
+
@@ -28025,54 +25289,45 @@ wire [ (32-1):0] multiplier_result_w;
-
-
+
-
-
-
-wire [ (32-1):0] interrupt_csr_read_data_x;
+wire [(32-1):0] interrupt_csr_read_data_x;
-wire [ (32-1):0] cfg;
-wire [ (32-1):0] cfg2;
-
+wire [(32-1):0] cfg;
+wire [(32-1):0] cfg2;
+
-
-reg [ (32-1):0] csr_read_data_x;
+reg [(32-1):0] csr_read_data_x;
-wire [ ((32-2)+2-1):2] pc_f;
-wire [ ((32-2)+2-1):2] pc_d;
-wire [ ((32-2)+2-1):2] pc_x;
-wire [ ((32-2)+2-1):2] pc_m;
-wire [ ((32-2)+2-1):2] pc_w;
-
+wire [((32-2)+2-1):2] pc_f;
+wire [((32-2)+2-1):2] pc_d;
+wire [((32-2)+2-1):2] pc_x;
+wire [((32-2)+2-1):2] pc_m;
+wire [((32-2)+2-1):2] pc_w;
+
-
-
-
-wire [ (32-1):0] instruction_f;
+wire [(32-1):0] instruction_f;
-wire [ (32-1):0] instruction_d;
-
+wire [(32-1):0] instruction_d;
+
-
-
+
@@ -28081,8 +25336,7 @@ wire [ (32-1):0] instruction_d;
-
-
+
@@ -28090,12 +25344,11 @@ wire [ (32-1):0] instruction_d;
-
-wire [ (32-1):0] load_data_w;
+wire [(32-1):0] load_data_w;
wire stall_wb_load;
-
+
@@ -28115,7 +25368,6 @@ wire stall_wb_load;
-
wire raw_x_0;
@@ -28132,10 +25384,9 @@ wire cmp_overflow;
wire cmp_carry_n;
reg condition_met_x;
reg condition_met_m;
-
+
-
wire branch_taken_m;
wire kill_f;
@@ -28144,19 +25395,17 @@ wire kill_x;
wire kill_m;
wire kill_w;
-reg [ (32-2)+2-1:8] eba;
-
+reg [(32-2)+2-1:8] eba;
+
-
-reg [ (3-1):0] eid_x;
-
+reg [(3-1):0] eid_x;
+
-
-
+
@@ -28171,43 +25420,35 @@ reg [ (3-1):0] eid_x;
-
wire exception_x;
reg exception_m;
reg exception_w;
wire exception_q_w;
-
-
+
-
-
-
-wire interrupt_exception;
+wire interrupt_exception;
-
+
-
-
+
-
-
+
-
wire system_call_exception;
-
+
@@ -28215,10 +25456,7 @@ wire system_call_exception;
-
-
-
-
+
@@ -28274,7 +25512,6 @@ endfunction
-
lm32_instruction_unit_medium #(
.associativity (icache_associativity),
.sets (icache_sets),
@@ -28296,47 +25533,40 @@ lm32_instruction_unit_medium #(
.kill_f (kill_f),
.branch_predict_taken_d (branch_predict_taken_d),
.branch_predict_address_d (branch_predict_address_d),
-
+
-
.exception_m (exception_m),
.branch_taken_m (branch_taken_m),
.branch_mispredict_taken_m (branch_mispredict_taken_m),
.branch_target_m (branch_target_m),
-
+
-
-
+
-
-
+
-
-
-
+
.i_dat_i (I_DAT_I),
.i_ack_i (I_ACK_I),
.i_err_i (I_ERR_I),
.i_rty_i (I_RTY_I),
-
-
+
-
.pc_f (pc_f),
@@ -28344,19 +25574,16 @@ lm32_instruction_unit_medium #(
.pc_x (pc_x),
.pc_m (pc_m),
.pc_w (pc_w),
-
+
-
-
+
-
-
-
+
.i_dat_o (I_DAT_O),
.i_adr_o (I_ADR_O),
@@ -28367,21 +25594,16 @@ lm32_instruction_unit_medium #(
.i_cti_o (I_CTI_O),
.i_lock_o (I_LOCK_O),
.i_bte_o (I_BTE_O),
-
-
+
-
-
+
-
-
-
- .instruction_f (instruction_f),
+ .instruction_f (instruction_f),
.instruction_d (instruction_d)
);
@@ -28394,36 +25616,27 @@ lm32_decoder_medium decoder (
.d_result_sel_0 (d_result_sel_0_d),
.d_result_sel_1 (d_result_sel_1_d),
.x_result_sel_csr (x_result_sel_csr_d),
-
+
-
-
+
-
-
-
- .x_result_sel_sext (x_result_sel_sext_d),
+ .x_result_sel_sext (x_result_sel_sext_d),
.x_result_sel_logic (x_result_sel_logic_d),
-
+
-
.x_result_sel_add (x_result_sel_add_d),
.m_result_sel_compare (m_result_sel_compare_d),
-
-
- .m_result_sel_shift (m_result_sel_shift_d),
+ .m_result_sel_shift (m_result_sel_shift_d),
.w_result_sel_load (w_result_sel_load_d),
-
-
- .w_result_sel_mul (w_result_sel_mul_d),
+ .w_result_sel_mul (w_result_sel_mul_d),
.x_bypass_enable (x_bypass_enable_d),
.m_bypass_enable (m_bypass_enable_d),
@@ -28441,44 +25654,36 @@ lm32_decoder_medium decoder (
.sign_extend (sign_extend_d),
.adder_op (adder_op_d),
.logic_op (logic_op_d),
-
-
- .direction (direction_d),
+ .direction (direction_d),
-
+
-
-
+
-
-
+
-
.branch (branch_d),
.bi_unconditional (bi_unconditional),
.bi_conditional (bi_conditional),
.branch_reg (branch_reg_d),
.condition (condition_d),
-
+
-
.scall (scall_d),
.eret (eret_d),
-
+
-
-
+
-
.csr_write_enable (csr_write_enable_d)
);
@@ -28512,14 +25717,12 @@ lm32_load_store_unit_medium #(
.store_q_m (store_q_m),
.sign_extend_x (sign_extend_x),
.size_x (size_x),
-
+
-
-
+
-
.d_dat_i (D_DAT_I),
.d_ack_i (D_ACK_I),
@@ -28527,20 +25730,18 @@ lm32_load_store_unit_medium #(
.d_rty_i (D_RTY_I),
-
+
-
-
+
-
.load_data_w (load_data_w),
.stall_wb_load (stall_wb_load),
@@ -28579,8 +25780,7 @@ lm32_logic_op logic_op (
.logic_result_x (logic_result_x)
);
-
-
+
lm32_shifter shifter (
@@ -28594,11 +25794,9 @@ lm32_shifter shifter (
.shifter_result_m (shifter_result_m)
);
-
-
-
+
lm32_multiplier multiplier (
@@ -28611,10 +25809,9 @@ lm32_multiplier multiplier (
.result (multiplier_result_w)
);
-
-
+
@@ -28643,11 +25840,9 @@ lm32_multiplier multiplier (
-
-
-
+
lm32_interrupt_medium interrupt_unit (
@@ -28657,19 +25852,16 @@ lm32_interrupt_medium interrupt_unit (
.interrupt (interrupt),
.stall_x (stall_x),
-
+
-
.exception (exception_q_w),
-
.eret_q_x (eret_q_x),
-
+
-
.csr (csr_x),
.csr_write_data (operand_1_x),
.csr_write_enable (csr_write_enable_q_x),
@@ -28678,10 +25870,9 @@ lm32_interrupt_medium interrupt_unit (
.csr_read_data (interrupt_csr_read_data_x)
);
-
-
+
@@ -28731,8 +25922,7 @@ lm32_interrupt_medium interrupt_unit (
-
-
+
@@ -28775,9 +25965,7 @@ lm32_interrupt_medium interrupt_unit (
-
-
-
+
@@ -28838,8 +26026,8 @@ lm32_interrupt_medium interrupt_unit (
- always @(posedge clk_i )
- if (rst_i == 1'b1)
+ always @(posedge clk_i )
+ if (rst_i == 1'b1)
begin
regfile_raw_0 <= 1'b0;
regfile_raw_1 <= 1'b0;
@@ -28894,10 +26082,9 @@ lm32_interrupt_medium interrupt_unit (
.rdata_o (regfile_data_1)
);
-
-
+
@@ -28970,58 +26157,53 @@ lm32_interrupt_medium interrupt_unit (
-
-
-
+
assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
-
-
-
+
-
-assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == 1'b1);
-assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == 1'b1);
-assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == 1'b1);
-assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == 1'b1);
-assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == 1'b1);
-assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == 1'b1);
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == 1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == 1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == 1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == 1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == 1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == 1'b1);
always @(*)
begin
- if ( ( (x_bypass_enable_x == 1'b0)
- && ( ((read_enable_0_d == 1'b1) && (raw_x_0 == 1'b1))
- || ((read_enable_1_d == 1'b1) && (raw_x_1 == 1'b1))
+ if ( ( (x_bypass_enable_x == 1'b0)
+ && ( ((read_enable_0_d == 1'b1) && (raw_x_0 == 1'b1))
+ || ((read_enable_1_d == 1'b1) && (raw_x_1 == 1'b1))
)
)
- || ( (m_bypass_enable_m == 1'b0)
- && ( ((read_enable_0_d == 1'b1) && (raw_m_0 == 1'b1))
- || ((read_enable_1_d == 1'b1) && (raw_m_1 == 1'b1))
+ || ( (m_bypass_enable_m == 1'b0)
+ && ( ((read_enable_0_d == 1'b1) && (raw_m_0 == 1'b1))
+ || ((read_enable_1_d == 1'b1) && (raw_m_1 == 1'b1))
)
)
)
- interlock = 1'b1;
+ interlock = 1'b1;
else
- interlock = 1'b0;
+ interlock = 1'b0;
end
always @(*)
begin
- if (raw_x_0 == 1'b1)
+ if (raw_x_0 == 1'b1)
bypass_data_0 = x_result;
- else if (raw_m_0 == 1'b1)
+ else if (raw_m_0 == 1'b1)
bypass_data_0 = m_result;
- else if (raw_w_0 == 1'b1)
+ else if (raw_w_0 == 1'b1)
bypass_data_0 = w_result;
else
bypass_data_0 = reg_data_0;
@@ -29030,11 +26212,11 @@ end
always @(*)
begin
- if (raw_x_1 == 1'b1)
+ if (raw_x_1 == 1'b1)
bypass_data_1 = x_result;
- else if (raw_m_1 == 1'b1)
+ else if (raw_m_1 == 1'b1)
bypass_data_1 = m_result;
- else if (raw_w_1 == 1'b1)
+ else if (raw_w_1 == 1'b1)
bypass_data_1 = w_result;
else
bypass_data_1 = reg_data_1;
@@ -29062,51 +26244,47 @@ always @(*)
begin
d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
case (d_result_sel_1_d)
- 2'b00: d_result_1 = { 32{1'b0}};
- 2'b01: d_result_1 = bypass_data_1;
- 2'b10: d_result_1 = immediate_d;
- default: d_result_1 = { 32{1'bx}};
+ 2'b00: d_result_1 = {32{1'b0}};
+ 2'b01: d_result_1 = bypass_data_1;
+ 2'b10: d_result_1 = immediate_d;
+ default: d_result_1 = {32{1'bx}};
endcase
end
-
+
-
-
-
+
assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
-assign sext_result_x = size_x == 2'b00 ? sextb_result_x : sexth_result_x;
-
+assign sext_result_x = size_x == 2'b00 ? sextb_result_x : sexth_result_x;
-
+
-
assign cmp_zero = operand_0_x == operand_1_x;
-assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_negative = adder_result_x[32-1];
assign cmp_overflow = adder_overflow_x;
assign cmp_carry_n = adder_carry_n_x;
always @(*)
begin
case (condition_x)
- 3'b000: condition_met_x = 1'b1;
- 3'b110: condition_met_x = 1'b1;
- 3'b001: condition_met_x = cmp_zero;
- 3'b111: condition_met_x = !cmp_zero;
- 3'b010: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
- 3'b101: condition_met_x = cmp_carry_n && !cmp_zero;
- 3'b011: condition_met_x = cmp_negative == cmp_overflow;
- 3'b100: condition_met_x = cmp_carry_n;
+ 3'b000: condition_met_x = 1'b1;
+ 3'b110: condition_met_x = 1'b1;
+ 3'b001: condition_met_x = cmp_zero;
+ 3'b111: condition_met_x = !cmp_zero;
+ 3'b010: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+ 3'b101: condition_met_x = cmp_carry_n && !cmp_zero;
+ 3'b011: condition_met_x = cmp_negative == cmp_overflow;
+ 3'b100: condition_met_x = cmp_carry_n;
default: condition_met_x = 1'bx;
endcase
end
@@ -29116,34 +26294,27 @@ always @(*)
begin
x_result = x_result_sel_add_x ? adder_result_x
: x_result_sel_csr_x ? csr_read_data_x
-
-
- : x_result_sel_sext_x ? sext_result_x
+ : x_result_sel_sext_x ? sext_result_x
-
+
-
-
+
-
-
+
-
: logic_result_x;
end
always @(*)
begin
- m_result = m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
-
-
- : m_result_sel_shift_m ? shifter_result_m
+ m_result = m_result_sel_compare_m ? {{32-1{1'b0}}, condition_met_m}
+ : m_result_sel_shift_m ? shifter_result_m
: operand_m;
end
@@ -29152,15 +26323,13 @@ end
always @(*)
begin
w_result = w_result_sel_load_w ? load_data_w
-
-
- : w_result_sel_mul_w ? multiplier_result_w
+ : w_result_sel_mul_w ? multiplier_result_w
: operand_w;
end
-
+
@@ -29171,95 +26340,85 @@ end
-
-assign branch_taken_m = (stall_m == 1'b0)
- && ( ( (branch_m == 1'b1)
- && (valid_m == 1'b1)
- && ( ( (condition_met_m == 1'b1)
- && (branch_predict_taken_m == 1'b0)
+assign branch_taken_m = (stall_m == 1'b0)
+ && ( ( (branch_m == 1'b1)
+ && (valid_m == 1'b1)
+ && ( ( (condition_met_m == 1'b1)
+ && (branch_predict_taken_m == 1'b0)
)
- || ( (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1)
+ || ( (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1)
)
)
)
- || (exception_m == 1'b1)
+ || (exception_m == 1'b1)
);
-assign branch_mispredict_taken_m = (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1);
+assign branch_mispredict_taken_m = (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1);
-assign branch_flushX_m = (stall_m == 1'b0)
- && ( ( (branch_m == 1'b1)
- && (valid_m == 1'b1)
- && ( (condition_met_m == 1'b1)
- || ( (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1)
+assign branch_flushX_m = (stall_m == 1'b0)
+ && ( ( (branch_m == 1'b1)
+ && (valid_m == 1'b1)
+ && ( (condition_met_m == 1'b1)
+ || ( (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1)
)
)
)
- || (exception_m == 1'b1)
+ || (exception_m == 1'b1)
);
-assign kill_f = ( (valid_d == 1'b1)
- && (branch_predict_taken_d == 1'b1)
+assign kill_f = ( (valid_d == 1'b1)
+ && (branch_predict_taken_d == 1'b1)
)
- || (branch_taken_m == 1'b1)
-
+ || (branch_taken_m == 1'b1)
+
-
-
+
-
-
+
-
;
-assign kill_d = (branch_taken_m == 1'b1)
-
+assign kill_d = (branch_taken_m == 1'b1)
+
-
-
+
-
-
+
-
;
-assign kill_x = (branch_flushX_m == 1'b1)
-
+assign kill_x = (branch_flushX_m == 1'b1)
+
-
;
-assign kill_m = 1'b0
-
+assign kill_m = 1'b0
+
-
;
-assign kill_w = 1'b0
-
+assign kill_w = 1'b0
+
-
;
-
+
@@ -29271,33 +26430,28 @@ assign kill_w = 1'b0
-
-
+
-
-
+
-
-
+
-
-assign system_call_exception = ( (scall_x == 1'b1)
-
+assign system_call_exception = ( (scall_x == 1'b1)
+
-
);
-
+
@@ -29328,40 +26482,32 @@ assign system_call_exception = ( (scall_x == 1'b1)
-
-assign exception_x = (system_call_exception == 1'b1)
-
+assign exception_x = (system_call_exception == 1'b1)
+
-
-
+
-
-
-
- || ( (interrupt_exception == 1'b1)
-
+
+ || ( (interrupt_exception == 1'b1)
+
-
-
+
-
)
-
;
-
always @(*)
begin
-
+
@@ -29376,8 +26522,7 @@ begin
-
-
+
@@ -29385,60 +26530,53 @@ begin
-
-
+
-
-
+
-
-
-
- if ( (interrupt_exception == 1'b1)
-
+
+ if ( (interrupt_exception == 1'b1)
+
-
)
- eid_x = 3'h6;
+ eid_x = 3'h6;
else
-
- eid_x = 3'h7;
+ eid_x = 3'h7;
end
-assign stall_a = (stall_f == 1'b1);
+assign stall_a = (stall_f == 1'b1);
-assign stall_f = (stall_d == 1'b1);
+assign stall_f = (stall_d == 1'b1);
-assign stall_d = (stall_x == 1'b1)
- || ( (interlock == 1'b1)
- && (kill_d == 1'b0)
+assign stall_d = (stall_x == 1'b1)
+ || ( (interlock == 1'b1)
+ && (kill_d == 1'b0)
)
- || ( ( (eret_d == 1'b1)
- || (scall_d == 1'b1)
-
+ || ( ( (eret_d == 1'b1)
+ || (scall_d == 1'b1)
+
-
)
- && ( (load_q_x == 1'b1)
- || (load_q_m == 1'b1)
- || (store_q_x == 1'b1)
- || (store_q_m == 1'b1)
- || (D_CYC_O == 1'b1)
+ && ( (load_q_x == 1'b1)
+ || (load_q_m == 1'b1)
+ || (store_q_x == 1'b1)
+ || (store_q_m == 1'b1)
+ || (D_CYC_O == 1'b1)
)
- && (kill_d == 1'b0)
+ && (kill_d == 1'b0)
)
-
+
@@ -29450,21 +26588,19 @@ assign stall_d = (stall_x == 1'b1)
-
- || ( (csr_write_enable_d == 1'b1)
- && (load_q_x == 1'b1)
+ || ( (csr_write_enable_d == 1'b1)
+ && (load_q_x == 1'b1)
)
;
-assign stall_x = (stall_m == 1'b1)
-
+assign stall_x = (stall_m == 1'b1)
+
-
-
+
@@ -29473,16 +26609,14 @@ assign stall_x = (stall_m == 1'b1)
-
;
-assign stall_m = (stall_wb_load == 1'b1)
-
+assign stall_m = (stall_wb_load == 1'b1)
+
-
- || ( (D_CYC_O == 1'b1)
- && ( (store_m == 1'b1)
+ || ( (D_CYC_O == 1'b1)
+ && ( (store_m == 1'b1)
@@ -29496,215 +26630,168 @@ assign stall_m = (stall_wb_load == 1'b1)
-
-
- || ((store_x == 1'b1) && (interrupt_exception == 1'b1))
+ || ((store_x == 1'b1) && (interrupt_exception == 1'b1))
- || (load_m == 1'b1)
- || (load_x == 1'b1)
+ || (load_m == 1'b1)
+ || (load_x == 1'b1)
)
)
-
-
+
-
-
+
-
-
-
- || (I_CYC_O == 1'b1)
+ || (I_CYC_O == 1'b1)
-
-
+
-
;
-
+
-
-
+
-
-
+
-
-
+
-
-assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
-assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
-assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
-
+assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
+assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
+
-
-assign load_q_x = (load_x == 1'b1)
- && (q_x == 1'b1)
-
+assign load_q_x = (load_x == 1'b1)
+ && (q_x == 1'b1)
+
-
;
-assign store_q_x = (store_x == 1'b1)
- && (q_x == 1'b1)
-
+assign store_q_x = (store_x == 1'b1)
+ && (q_x == 1'b1)
+
-
;
-
+
-
-assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
-assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
-assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
+assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
+assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
+assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
+
-
-assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1));
-
+assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1));
-assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
-assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
-assign write_enable_q_w = (write_enable_w == 1'b1) && (valid_w == 1'b1);
+assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
+assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
+assign write_enable_q_w = (write_enable_w == 1'b1) && (valid_w == 1'b1);
-assign reg_write_enable_q_w = (write_enable_w == 1'b1) && (kill_w == 1'b0) && (valid_w == 1'b1);
+assign reg_write_enable_q_w = (write_enable_w == 1'b1) && (kill_w == 1'b0) && (valid_w == 1'b1);
assign cfg = {
- 6'h02,
+ 6'h02,
watchpoints[3:0],
breakpoints[3:0],
interrupts[5:0],
-
+
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
+ 1'b1,
-
-
- 1'b1,
-
+
+ 1'b1,
-
+
- 1'b1,
+ 1'b0,
-
-
-
- 1'b0,
-
+ 1'b1
-
-
- 1'b1
-
-
};
assign cfg2 = {
30'b0,
-
+
+ 1'b0,
- 1'b0,
-
-
-
- 1'b0
-
+ 1'b0
};
-
+
@@ -29717,9 +26804,8 @@ assign cfg2 = {
-
-
+
@@ -29729,41 +26815,35 @@ assign cfg2 = {
-
-assign csr_d = read_idx_0_d[ (3-1):0];
+assign csr_d = read_idx_0_d[(3-1):0];
always @(*)
begin
case (csr_x)
-
-
- 3'h0,
- 3'h1,
- 3'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 3'h0,
+ 3'h1,
+ 3'h2: csr_read_data_x = interrupt_csr_read_data_x;
-
+
-
- 3'h6: csr_read_data_x = cfg;
- 3'h7: csr_read_data_x = {eba, 8'h00};
-
+ 3'h6: csr_read_data_x = cfg;
+ 3'h7: csr_read_data_x = {eba, 8'h00};
+
-
-
+
-
- 3'ha: csr_read_data_x = cfg2;
+ 3'ha: csr_read_data_x = cfg2;
- default: csr_read_data_x = { 32{1'bx}};
+ default: csr_read_data_x = {32{1'bx}};
endcase
end
@@ -29772,23 +26852,22 @@ end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- eba <= eba_reset[ (32-2)+2-1:8];
+ if (rst_i == 1'b1)
+ eba <= eba_reset[(32-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 3'h7) && (stall_x == 1'b0))
- eba <= operand_1_x[ (32-2)+2-1:8];
-
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 3'h7) && (stall_x == 1'b0))
+ eba <= operand_1_x[(32-2)+2-1:8];
+
-
end
end
-
+
@@ -29807,8 +26886,7 @@ end
-
-
+
@@ -29818,8 +26896,7 @@ end
-
-
+
@@ -29836,11 +26913,10 @@ end
-
-
+
@@ -29867,8 +26943,7 @@ end
-
-
+
@@ -29879,253 +26954,210 @@ end
-
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- valid_f <= 1'b0;
- valid_d <= 1'b0;
- valid_x <= 1'b0;
- valid_m <= 1'b0;
- valid_w <= 1'b0;
+ valid_f <= 1'b0;
+ valid_d <= 1'b0;
+ valid_x <= 1'b0;
+ valid_m <= 1'b0;
+ valid_w <= 1'b0;
end
else
begin
- if ((kill_f == 1'b1) || (stall_a == 1'b0))
-
+ if ((kill_f == 1'b1) || (stall_a == 1'b0))
+
-
- valid_f <= 1'b1;
-
+ valid_f <= 1'b1;
- else if (stall_f == 1'b0)
- valid_f <= 1'b0;
+ else if (stall_f == 1'b0)
+ valid_f <= 1'b0;
- if (kill_d == 1'b1)
- valid_d <= 1'b0;
- else if (stall_f == 1'b0)
+ if (kill_d == 1'b1)
+ valid_d <= 1'b0;
+ else if (stall_f == 1'b0)
valid_d <= valid_f & !kill_f;
- else if (stall_d == 1'b0)
- valid_d <= 1'b0;
+ else if (stall_d == 1'b0)
+ valid_d <= 1'b0;
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
valid_x <= valid_d & !kill_d;
- else if (kill_x == 1'b1)
- valid_x <= 1'b0;
- else if (stall_x == 1'b0)
- valid_x <= 1'b0;
-
- if (kill_m == 1'b1)
- valid_m <= 1'b0;
- else if (stall_x == 1'b0)
+ else if (kill_x == 1'b1)
+ valid_x <= 1'b0;
+ else if (stall_x == 1'b0)
+ valid_x <= 1'b0;
+
+ if (kill_m == 1'b1)
+ valid_m <= 1'b0;
+ else if (stall_x == 1'b0)
valid_m <= valid_x & !kill_x;
- else if (stall_m == 1'b0)
- valid_m <= 1'b0;
+ else if (stall_m == 1'b0)
+ valid_m <= 1'b0;
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
valid_w <= valid_m & !kill_m;
else
- valid_w <= 1'b0;
+ valid_w <= 1'b0;
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
-
+
-
- operand_0_x <= { 32{1'b0}};
- operand_1_x <= { 32{1'b0}};
- store_operand_x <= { 32{1'b0}};
- branch_target_x <= { (32-2){1'b0}};
- x_result_sel_csr_x <= 1'b0;
-
+ operand_0_x <= {32{1'b0}};
+ operand_1_x <= {32{1'b0}};
+ store_operand_x <= {32{1'b0}};
+ branch_target_x <= {(32-2){1'b0}};
+ x_result_sel_csr_x <= 1'b0;
+
-
-
+
-
-
-
- x_result_sel_sext_x <= 1'b0;
+ x_result_sel_sext_x <= 1'b0;
- x_result_sel_logic_x <= 1'b0;
-
+ x_result_sel_logic_x <= 1'b0;
+
-
- x_result_sel_add_x <= 1'b0;
- m_result_sel_compare_x <= 1'b0;
-
-
- m_result_sel_shift_x <= 1'b0;
+ x_result_sel_add_x <= 1'b0;
+ m_result_sel_compare_x <= 1'b0;
+ m_result_sel_shift_x <= 1'b0;
- w_result_sel_load_x <= 1'b0;
-
-
- w_result_sel_mul_x <= 1'b0;
+ w_result_sel_load_x <= 1'b0;
+ w_result_sel_mul_x <= 1'b0;
- x_bypass_enable_x <= 1'b0;
- m_bypass_enable_x <= 1'b0;
- write_enable_x <= 1'b0;
- write_idx_x <= { 5{1'b0}};
- csr_x <= { 3{1'b0}};
- load_x <= 1'b0;
- store_x <= 1'b0;
- size_x <= { 2{1'b0}};
- sign_extend_x <= 1'b0;
- adder_op_x <= 1'b0;
- adder_op_x_n <= 1'b0;
+ x_bypass_enable_x <= 1'b0;
+ m_bypass_enable_x <= 1'b0;
+ write_enable_x <= 1'b0;
+ write_idx_x <= {5{1'b0}};
+ csr_x <= {3{1'b0}};
+ load_x <= 1'b0;
+ store_x <= 1'b0;
+ size_x <= {2{1'b0}};
+ sign_extend_x <= 1'b0;
+ adder_op_x <= 1'b0;
+ adder_op_x_n <= 1'b0;
logic_op_x <= 4'h0;
-
-
- direction_x <= 1'b0;
+ direction_x <= 1'b0;
-
+
-
- branch_x <= 1'b0;
- branch_predict_x <= 1'b0;
- branch_predict_taken_x <= 1'b0;
- condition_x <= 3'b000;
-
+ branch_x <= 1'b0;
+ branch_predict_x <= 1'b0;
+ branch_predict_taken_x <= 1'b0;
+ condition_x <= 3'b000;
+
-
- scall_x <= 1'b0;
- eret_x <= 1'b0;
-
+ scall_x <= 1'b0;
+ eret_x <= 1'b0;
+
-
-
+
-
- csr_write_enable_x <= 1'b0;
- operand_m <= { 32{1'b0}};
- branch_target_m <= { (32-2){1'b0}};
- m_result_sel_compare_m <= 1'b0;
-
-
- m_result_sel_shift_m <= 1'b0;
+ csr_write_enable_x <= 1'b0;
+ operand_m <= {32{1'b0}};
+ branch_target_m <= {(32-2){1'b0}};
+ m_result_sel_compare_m <= 1'b0;
+ m_result_sel_shift_m <= 1'b0;
- w_result_sel_load_m <= 1'b0;
-
-
- w_result_sel_mul_m <= 1'b0;
+ w_result_sel_load_m <= 1'b0;
+ w_result_sel_mul_m <= 1'b0;
- m_bypass_enable_m <= 1'b0;
- branch_m <= 1'b0;
- branch_predict_m <= 1'b0;
- branch_predict_taken_m <= 1'b0;
- exception_m <= 1'b0;
- load_m <= 1'b0;
- store_m <= 1'b0;
-
-
- direction_m <= 1'b0;
+ m_bypass_enable_m <= 1'b0;
+ branch_m <= 1'b0;
+ branch_predict_m <= 1'b0;
+ branch_predict_taken_m <= 1'b0;
+ exception_m <= 1'b0;
+ load_m <= 1'b0;
+ store_m <= 1'b0;
+ direction_m <= 1'b0;
- write_enable_m <= 1'b0;
- write_idx_m <= { 5{1'b0}};
- condition_met_m <= 1'b0;
-
+ write_enable_m <= 1'b0;
+ write_idx_m <= {5{1'b0}};
+ condition_met_m <= 1'b0;
+
-
-
+
-
- operand_w <= { 32{1'b0}};
- w_result_sel_load_w <= 1'b0;
-
-
- w_result_sel_mul_w <= 1'b0;
+ operand_w <= {32{1'b0}};
+ w_result_sel_load_w <= 1'b0;
+ w_result_sel_mul_w <= 1'b0;
- write_idx_w <= { 5{1'b0}};
- write_enable_w <= 1'b0;
-
+ write_idx_w <= {5{1'b0}};
+ write_enable_w <= 1'b0;
+
+ exception_w <= 1'b0;
- exception_w <= 1'b0;
-
-
-
end
else
begin
- if (stall_x == 1'b0)
+ if (stall_x == 1'b0)
begin
-
+
-
operand_0_x <= d_result_0;
operand_1_x <= d_result_1;
store_operand_x <= bypass_data_1;
- branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((32-2)+2-1):2] : branch_target_d;
+ branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[((32-2)+2-1):2] : branch_target_d;
x_result_sel_csr_x <= x_result_sel_csr_d;
-
+
-
-
+
-
-
-
- x_result_sel_sext_x <= x_result_sel_sext_d;
+ x_result_sel_sext_x <= x_result_sel_sext_d;
x_result_sel_logic_x <= x_result_sel_logic_d;
-
+
-
x_result_sel_add_x <= x_result_sel_add_d;
m_result_sel_compare_x <= m_result_sel_compare_d;
-
-
- m_result_sel_shift_x <= m_result_sel_shift_d;
+ m_result_sel_shift_x <= m_result_sel_shift_d;
w_result_sel_load_x <= w_result_sel_load_d;
-
-
- w_result_sel_mul_x <= w_result_sel_mul_d;
+ w_result_sel_mul_x <= w_result_sel_mul_d;
x_bypass_enable_x <= x_bypass_enable_d;
m_bypass_enable_x <= m_bypass_enable_d;
@@ -30141,81 +27173,65 @@ begin
adder_op_x <= adder_op_d;
adder_op_x_n <= ~adder_op_d;
logic_op_x <= logic_op_d;
-
-
- direction_x <= direction_d;
+ direction_x <= direction_d;
-
+
-
condition_x <= condition_d;
csr_write_enable_x <= csr_write_enable_d;
-
+
-
scall_x <= scall_d;
-
+
-
eret_x <= eret_d;
-
+
-
write_enable_x <= write_enable_d;
end
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
operand_m <= x_result;
m_result_sel_compare_m <= m_result_sel_compare_x;
-
-
- m_result_sel_shift_m <= m_result_sel_shift_x;
+ m_result_sel_shift_m <= m_result_sel_shift_x;
- if (exception_x == 1'b1)
+ if (exception_x == 1'b1)
begin
- w_result_sel_load_m <= 1'b0;
-
-
- w_result_sel_mul_m <= 1'b0;
+ w_result_sel_load_m <= 1'b0;
+ w_result_sel_mul_m <= 1'b0;
end
else
begin
w_result_sel_load_m <= w_result_sel_load_x;
-
-
- w_result_sel_mul_m <= w_result_sel_mul_x;
+ w_result_sel_mul_m <= w_result_sel_mul_x;
end
m_bypass_enable_m <= m_bypass_enable_x;
-
-
- direction_m <= direction_x;
+ direction_m <= direction_x;
load_m <= load_x;
store_m <= store_x;
-
+
-
branch_m <= branch_x;
branch_predict_m <= branch_predict_x;
branch_predict_taken_m <= branch_predict_taken_x;
-
-
+
@@ -30228,15 +27244,13 @@ begin
-
- if (exception_x == 1'b1)
- write_idx_m <= 5'd30;
+ if (exception_x == 1'b1)
+ write_idx_m <= 5'd30;
else
write_idx_m <= write_idx_x;
-
condition_met_m <= condition_met_x;
-
+
@@ -30247,81 +27261,67 @@ begin
+ branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
- branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
-
-
-
-
+
-
eret_m <= eret_q_x;
-
+
-
- write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
-
+ write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
+
-
end
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
- if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
- exception_m <= 1'b1;
+ if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
+ exception_m <= 1'b1;
else
- exception_m <= 1'b0;
-
+ exception_m <= 1'b0;
+
-
end
-
+
-
- operand_w <= exception_m == 1'b1 ? {pc_m, 2'b00} : m_result;
-
+ operand_w <= exception_m == 1'b1 ? {pc_m, 2'b00} : m_result;
w_result_sel_load_w <= w_result_sel_load_m;
-
-
- w_result_sel_mul_w <= w_result_sel_mul_m;
+ w_result_sel_mul_w <= w_result_sel_mul_m;
write_idx_w <= write_idx_m;
-
+
-
write_enable_w <= write_enable_m;
-
+
-
exception_w <= exception_m;
-
-
+
@@ -30329,33 +27329,31 @@ begin
-
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- use_buf <= 1'b0;
- reg_data_buf_0 <= { 32{1'b0}};
- reg_data_buf_1 <= { 32{1'b0}};
+ use_buf <= 1'b0;
+ reg_data_buf_0 <= {32{1'b0}};
+ reg_data_buf_1 <= {32{1'b0}};
end
else
begin
- if (stall_d == 1'b0)
- use_buf <= 1'b0;
- else if (use_buf == 1'b0)
+ if (stall_d == 1'b0)
+ use_buf <= 1'b0;
+ else if (use_buf == 1'b0)
begin
reg_data_buf_0 <= reg_data_live_0;
reg_data_buf_1 <= reg_data_live_1;
- use_buf <= 1'b1;
+ use_buf <= 1'b1;
end
- if (reg_write_enable_q_w == 1'b1)
+ if (reg_write_enable_q_w == 1'b1)
begin
if (write_idx_w == read_idx_0_d)
reg_data_buf_0 <= w_result;
@@ -30364,13 +27362,11 @@ begin
end
end
end
-
-
-
+
@@ -30414,8 +27410,7 @@ end
-
-
+
@@ -30474,7 +27469,6 @@ end
-
@@ -30487,13 +27481,9 @@ end
initial
begin
-
-
- reg_0.ram[0] = { 32{1'b0}};
- reg_1.ram[0] = { 32{1'b0}};
-
+
end
@@ -30541,10 +27531,7 @@ endmodule
-
-
-
-
+
@@ -30574,9 +27561,9 @@ endmodule
-
+
@@ -30861,8 +27848,6 @@ endmodule
-
-
@@ -30889,14 +27874,12 @@ module lm32_load_store_unit_medium (
store_q_m,
sign_extend_x,
size_x,
-
+
-
-
+
-
d_dat_i,
d_ack_i,
@@ -30904,19 +27887,17 @@ module lm32_load_store_unit_medium (
d_rty_i,
-
+
-
-
+
-
load_data_w,
stall_wb_load,
@@ -30961,9 +27942,9 @@ input kill_x;
input kill_m;
input exception_m;
-input [ (32-1):0] store_operand_x;
-input [ (32-1):0] load_store_address_x;
-input [ (32-1):0] load_store_address_m;
+input [(32-1):0] store_operand_x;
+input [(32-1):0] load_store_address_x;
+input [(32-1):0] load_store_address_m;
input [1:0] load_store_address_w;
input load_x;
input store_x;
@@ -30972,19 +27953,17 @@ input store_q_x;
input load_q_m;
input store_q_m;
input sign_extend_x;
-input [ 1:0] size_x;
+input [1:0] size_x;
-
+
-
-
+
-
-input [ (32-1):0] d_dat_i;
+input [(32-1):0] d_dat_i;
input d_ack_i;
input d_err_i;
input d_rty_i;
@@ -30993,7 +27972,7 @@ input d_rty_i;
-
+
@@ -31004,8 +27983,7 @@ input d_rty_i;
-
-
+
@@ -31014,50 +27992,49 @@ input d_rty_i;
-
-output [ (32-1):0] load_data_w;
-reg [ (32-1):0] load_data_w;
+output [(32-1):0] load_data_w;
+reg [(32-1):0] load_data_w;
output stall_wb_load;
reg stall_wb_load;
-output [ (32-1):0] d_dat_o;
-reg [ (32-1):0] d_dat_o;
-output [ (32-1):0] d_adr_o;
-reg [ (32-1):0] d_adr_o;
+output [(32-1):0] d_dat_o;
+reg [(32-1):0] d_dat_o;
+output [(32-1):0] d_adr_o;
+reg [(32-1):0] d_adr_o;
output d_cyc_o;
reg d_cyc_o;
-output [ (4-1):0] d_sel_o;
-reg [ (4-1):0] d_sel_o;
+output [(4-1):0] d_sel_o;
+reg [(4-1):0] d_sel_o;
output d_stb_o;
reg d_stb_o;
output d_we_o;
reg d_we_o;
-output [ (3-1):0] d_cti_o;
-reg [ (3-1):0] d_cti_o;
+output [(3-1):0] d_cti_o;
+reg [(3-1):0] d_cti_o;
output d_lock_o;
reg d_lock_o;
-output [ (2-1):0] d_bte_o;
-wire [ (2-1):0] d_bte_o;
+output [(2-1):0] d_bte_o;
+wire [(2-1):0] d_bte_o;
-reg [ 1:0] size_m;
-reg [ 1:0] size_w;
+reg [1:0] size_m;
+reg [1:0] size_w;
reg sign_extend_m;
reg sign_extend_w;
-reg [ (32-1):0] store_data_x;
-reg [ (32-1):0] store_data_m;
-reg [ (4-1):0] byte_enable_x;
-reg [ (4-1):0] byte_enable_m;
-wire [ (32-1):0] data_m;
-reg [ (32-1):0] data_w;
+reg [(32-1):0] store_data_x;
+reg [(32-1):0] store_data_m;
+reg [(4-1):0] byte_enable_x;
+reg [(4-1):0] byte_enable_m;
+wire [(32-1):0] data_m;
+reg [(32-1):0] data_w;
-
+
@@ -31068,8 +28045,7 @@ reg [ (32-1):0] data_w;
-
-
+
@@ -31077,25 +28053,21 @@ reg [ (32-1):0] data_w;
-
wire wb_select_x;
-
+
-
reg wb_select_m;
-reg [ (32-1):0] wb_data_m;
+reg [(32-1):0] wb_data_m;
reg wb_load_complete;
-
-
-
+
@@ -31150,8 +28122,7 @@ endfunction
-
-
+
@@ -31235,8 +28206,7 @@ endfunction
-
-
+
@@ -31275,20 +28245,17 @@ endfunction
-
-
+
-
-
+
-
-
+
@@ -31298,32 +28265,28 @@ endfunction
-
- assign wb_select_x = 1'b1
-
+ assign wb_select_x = 1'b1
+
-
-
+
-
-
+
-
;
always @(*)
begin
case (size_x)
- 2'b00: store_data_x = {4{store_operand_x[7:0]}};
- 2'b11: store_data_x = {2{store_operand_x[15:0]}};
- 2'b10: store_data_x = store_operand_x;
- default: store_data_x = { 32{1'bx}};
+ 2'b00: store_data_x = {4{store_operand_x[7:0]}};
+ 2'b11: store_data_x = {2{store_operand_x[15:0]}};
+ 2'b10: store_data_x = store_operand_x;
+ default: store_data_x = {32{1'bx}};
endcase
end
@@ -31331,18 +28294,18 @@ end
always @(*)
begin
casez ({size_x, load_store_address_x[1:0]})
- { 2'b00, 2'b11}: byte_enable_x = 4'b0001;
- { 2'b00, 2'b10}: byte_enable_x = 4'b0010;
- { 2'b00, 2'b01}: byte_enable_x = 4'b0100;
- { 2'b00, 2'b00}: byte_enable_x = 4'b1000;
- { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
- { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
- { 2'b10, 2'b??}: byte_enable_x = 4'b1111;
+ {2'b00, 2'b11}: byte_enable_x = 4'b0001;
+ {2'b00, 2'b10}: byte_enable_x = 4'b0010;
+ {2'b00, 2'b01}: byte_enable_x = 4'b0100;
+ {2'b00, 2'b00}: byte_enable_x = 4'b1000;
+ {2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+ {2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+ {2'b10, 2'b??}: byte_enable_x = 4'b1111;
default: byte_enable_x = 4'bxxxx;
endcase
end
-
+
@@ -31350,8 +28313,7 @@ end
-
-
+
@@ -31359,8 +28321,7 @@ end
-
-
+
@@ -31380,9 +28341,8 @@ end
-
-
+
@@ -31417,8 +28377,7 @@ end
-
-
+
@@ -31433,20 +28392,15 @@ end
-
-
+
-
assign data_m = wb_data_m;
-
-
-
@@ -31454,21 +28408,21 @@ end
always @(*)
begin
casez ({size_w, load_store_address_w[1:0]})
- { 2'b00, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
- { 2'b00, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
- { 2'b00, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
- { 2'b00, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
- { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
- { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
- { 2'b10, 2'b??}: load_data_w = data_w;
- default: load_data_w = { 32{1'bx}};
+ {2'b00, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+ {2'b00, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+ {2'b00, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+ {2'b00, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+ {2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+ {2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+ {2'b10, 2'b??}: load_data_w = data_w;
+ default: load_data_w = {32{1'bx}};
endcase
end
-assign d_bte_o = 2'b00;
+assign d_bte_o = 2'b00;
-
+
@@ -31502,74 +28456,69 @@ assign d_bte_o = 2'b00;
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- d_cyc_o <= 1'b0;
- d_stb_o <= 1'b0;
- d_dat_o <= { 32{1'b0}};
- d_adr_o <= { 32{1'b0}};
- d_sel_o <= { 4{ 1'b0}};
- d_we_o <= 1'b0;
- d_cti_o <= 3'b111;
- d_lock_o <= 1'b0;
- wb_data_m <= { 32{1'b0}};
- wb_load_complete <= 1'b0;
- stall_wb_load <= 1'b0;
-
+ d_cyc_o <= 1'b0;
+ d_stb_o <= 1'b0;
+ d_dat_o <= {32{1'b0}};
+ d_adr_o <= {32{1'b0}};
+ d_sel_o <= {4{1'b0}};
+ d_we_o <= 1'b0;
+ d_cti_o <= 3'b111;
+ d_lock_o <= 1'b0;
+ wb_data_m <= {32{1'b0}};
+ wb_load_complete <= 1'b0;
+ stall_wb_load <= 1'b0;
+
-
end
else
begin
-
+
-
- if (d_cyc_o == 1'b1)
+ if (d_cyc_o == 1'b1)
begin
- if ((d_ack_i == 1'b1) || (d_err_i == 1'b1))
+ if ((d_ack_i == 1'b1) || (d_err_i == 1'b1))
begin
-
+
-
begin
- d_cyc_o <= 1'b0;
- d_stb_o <= 1'b0;
- d_lock_o <= 1'b0;
+ d_cyc_o <= 1'b0;
+ d_stb_o <= 1'b0;
+ d_lock_o <= 1'b0;
end
-
+
-
wb_data_m <= d_dat_i;
wb_load_complete <= !d_we_o;
end
- if (d_err_i == 1'b1)
+ if (d_err_i == 1'b1)
$display ("Data bus error. Address: %x", d_adr_o);
end
else
begin
-
+
@@ -31582,115 +28531,106 @@ begin
-
- if ( (store_q_m == 1'b1)
- && (stall_m == 1'b0)
-
+ if ( (store_q_m == 1'b1)
+ && (stall_m == 1'b0)
+
-
-
+
-
)
begin
d_dat_o <= store_data_m;
d_adr_o <= load_store_address_m;
- d_cyc_o <= 1'b1;
+ d_cyc_o <= 1'b1;
d_sel_o <= byte_enable_m;
- d_stb_o <= 1'b1;
- d_we_o <= 1'b1;
- d_cti_o <= 3'b111;
+ d_stb_o <= 1'b1;
+ d_we_o <= 1'b1;
+ d_cti_o <= 3'b111;
end
- else if ( (load_q_m == 1'b1)
- && (wb_select_m == 1'b1)
- && (wb_load_complete == 1'b0)
+ else if ( (load_q_m == 1'b1)
+ && (wb_select_m == 1'b1)
+ && (wb_load_complete == 1'b0)
)
begin
- stall_wb_load <= 1'b0;
+ stall_wb_load <= 1'b0;
d_adr_o <= load_store_address_m;
- d_cyc_o <= 1'b1;
+ d_cyc_o <= 1'b1;
d_sel_o <= byte_enable_m;
- d_stb_o <= 1'b1;
- d_we_o <= 1'b0;
- d_cti_o <= 3'b111;
+ d_stb_o <= 1'b1;
+ d_we_o <= 1'b0;
+ d_cti_o <= 3'b111;
end
end
- if (stall_m == 1'b0)
- wb_load_complete <= 1'b0;
+ if (stall_m == 1'b0)
+ wb_load_complete <= 1'b0;
- if ((load_q_x == 1'b1) && (wb_select_x == 1'b1) && (stall_x == 1'b0))
- stall_wb_load <= 1'b1;
+ if ((load_q_x == 1'b1) && (wb_select_x == 1'b1) && (stall_x == 1'b0))
+ stall_wb_load <= 1'b1;
- if ((kill_m == 1'b1) || (exception_m == 1'b1))
- stall_wb_load <= 1'b0;
+ if ((kill_m == 1'b1) || (exception_m == 1'b1))
+ stall_wb_load <= 1'b0;
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- sign_extend_m <= 1'b0;
+ sign_extend_m <= 1'b0;
size_m <= 2'b00;
- byte_enable_m <= 1'b0;
- store_data_m <= { 32{1'b0}};
-
+ byte_enable_m <= 1'b0;
+ store_data_m <= {32{1'b0}};
+
-
-
+
-
-
+
-
- wb_select_m <= 1'b0;
+ wb_select_m <= 1'b0;
end
else
begin
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
sign_extend_m <= sign_extend_x;
size_m <= size_x;
byte_enable_m <= byte_enable_x;
store_data_m <= store_data_x;
-
+
-
-
+
-
-
+
-
wb_select_m <= wb_select_x;
end
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
size_w <= 2'b00;
- data_w <= { 32{1'b0}};
- sign_extend_w <= 1'b0;
+ data_w <= {32{1'b0}};
+ sign_extend_w <= 1'b0;
end
else
begin
@@ -31709,11 +28649,11 @@ end
always @(posedge clk_i)
begin
- if (((load_q_m == 1'b1) || (store_q_m == 1'b1)) && (stall_m == 1'b0))
+ if (((load_q_m == 1'b1) || (store_q_m == 1'b1)) && (stall_m == 1'b0))
begin
- if ((size_m === 2'b11) && (load_store_address_m[0] !== 1'b0))
+ if ((size_m === 2'b11) && (load_store_address_m[0] !== 1'b0))
$display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
- if ((size_m === 2'b10) && (load_store_address_m[1:0] !== 2'b00))
+ if ((size_m === 2'b10) && (load_store_address_m[1:0] !== 2'b00))
$display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
end
end
@@ -31755,10 +28695,7 @@ endmodule
-
-
-
-
+
@@ -31788,9 +28725,9 @@ endmodule
-
+
@@ -32075,104 +29012,55 @@ endmodule
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -32185,36 +29073,27 @@ module lm32_decoder_medium (
d_result_sel_0,
d_result_sel_1,
x_result_sel_csr,
-
+
-
-
+
-
-
-
- x_result_sel_sext,
+ x_result_sel_sext,
x_result_sel_logic,
-
+
-
x_result_sel_add,
m_result_sel_compare,
-
-
- m_result_sel_shift,
+ m_result_sel_shift,
w_result_sel_load,
-
-
- w_result_sel_mul,
+ w_result_sel_mul,
x_bypass_enable,
m_bypass_enable,
@@ -32232,44 +29111,36 @@ module lm32_decoder_medium (
sign_extend,
adder_op,
logic_op,
-
-
- direction,
+ direction,
-
+
-
-
+
-
-
+
-
branch,
branch_reg,
condition,
bi_conditional,
bi_unconditional,
-
+
-
scall,
eret,
-
+
-
-
+
-
csr_write_enable
);
@@ -32277,58 +29148,49 @@ module lm32_decoder_medium (
-input [ (32-1):0] instruction;
+input [(32-1):0] instruction;
-output [ 0:0] d_result_sel_0;
-reg [ 0:0] d_result_sel_0;
-output [ 1:0] d_result_sel_1;
-reg [ 1:0] d_result_sel_1;
+output [0:0] d_result_sel_0;
+reg [0:0] d_result_sel_0;
+output [1:0] d_result_sel_1;
+reg [1:0] d_result_sel_1;
output x_result_sel_csr;
reg x_result_sel_csr;
-
+
-
-
+
-
-
-
+
output x_result_sel_sext;
reg x_result_sel_sext;
-
output x_result_sel_logic;
reg x_result_sel_logic;
-
+
-
output x_result_sel_add;
reg x_result_sel_add;
output m_result_sel_compare;
reg m_result_sel_compare;
-
-
+
output m_result_sel_shift;
reg m_result_sel_shift;
-
output w_result_sel_load;
reg w_result_sel_load;
-
-
+
output w_result_sel_mul;
reg w_result_sel_mul;
-
output x_bypass_enable;
wire x_bypass_enable;
@@ -32336,86 +29198,78 @@ output m_bypass_enable;
wire m_bypass_enable;
output read_enable_0;
wire read_enable_0;
-output [ (5-1):0] read_idx_0;
-wire [ (5-1):0] read_idx_0;
+output [(5-1):0] read_idx_0;
+wire [(5-1):0] read_idx_0;
output read_enable_1;
wire read_enable_1;
-output [ (5-1):0] read_idx_1;
-wire [ (5-1):0] read_idx_1;
+output [(5-1):0] read_idx_1;
+wire [(5-1):0] read_idx_1;
output write_enable;
wire write_enable;
-output [ (5-1):0] write_idx;
-wire [ (5-1):0] write_idx;
-output [ (32-1):0] immediate;
-wire [ (32-1):0] immediate;
-output [ ((32-2)+2-1):2] branch_offset;
-wire [ ((32-2)+2-1):2] branch_offset;
+output [(5-1):0] write_idx;
+wire [(5-1):0] write_idx;
+output [(32-1):0] immediate;
+wire [(32-1):0] immediate;
+output [((32-2)+2-1):2] branch_offset;
+wire [((32-2)+2-1):2] branch_offset;
output load;
wire load;
output store;
wire store;
-output [ 1:0] size;
-wire [ 1:0] size;
+output [1:0] size;
+wire [1:0] size;
output sign_extend;
wire sign_extend;
output adder_op;
wire adder_op;
-output [ 3:0] logic_op;
-wire [ 3:0] logic_op;
-
-
+output [3:0] logic_op;
+wire [3:0] logic_op;
+
output direction;
wire direction;
-
-
+
-
-
+
-
-
+
-
output branch;
wire branch;
output branch_reg;
wire branch_reg;
-output [ (3-1):0] condition;
-wire [ (3-1):0] condition;
+output [(3-1):0] condition;
+wire [(3-1):0] condition;
output bi_conditional;
wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
-
+
-
output scall;
wire scall;
output eret;
wire eret;
-
+
-
-
+
-
output csr_write_enable;
wire csr_write_enable;
@@ -32423,10 +29277,10 @@ wire csr_write_enable;
-wire [ (32-1):0] extended_immediate;
-wire [ (32-1):0] high_immediate;
-wire [ (32-1):0] call_immediate;
-wire [ (32-1):0] branch_immediate;
+wire [(32-1):0] extended_immediate;
+wire [(32-1):0] high_immediate;
+wire [(32-1):0] call_immediate;
+wire [(32-1):0] branch_immediate;
wire sign_extend_immediate;
wire select_high_immediate;
wire select_call_immediate;
@@ -32435,9 +29289,7 @@ wire select_call_immediate;
-
-
-
+
@@ -32493,70 +29345,61 @@ endfunction
-
-assign op_add = instruction[ 30:26] == 5'b01101;
-assign op_and = instruction[ 30:26] == 5'b01000;
-assign op_andhi = instruction[ 31:26] == 6'b011000;
-assign op_b = instruction[ 31:26] == 6'b110000;
-assign op_bi = instruction[ 31:26] == 6'b111000;
-assign op_be = instruction[ 31:26] == 6'b010001;
-assign op_bg = instruction[ 31:26] == 6'b010010;
-assign op_bge = instruction[ 31:26] == 6'b010011;
-assign op_bgeu = instruction[ 31:26] == 6'b010100;
-assign op_bgu = instruction[ 31:26] == 6'b010101;
-assign op_bne = instruction[ 31:26] == 6'b010111;
-assign op_call = instruction[ 31:26] == 6'b110110;
-assign op_calli = instruction[ 31:26] == 6'b111110;
-assign op_cmpe = instruction[ 30:26] == 5'b11001;
-assign op_cmpg = instruction[ 30:26] == 5'b11010;
-assign op_cmpge = instruction[ 30:26] == 5'b11011;
-assign op_cmpgeu = instruction[ 30:26] == 5'b11100;
-assign op_cmpgu = instruction[ 30:26] == 5'b11101;
-assign op_cmpne = instruction[ 30:26] == 5'b11111;
-
+assign op_add = instruction[30:26] == 5'b01101;
+assign op_and = instruction[30:26] == 5'b01000;
+assign op_andhi = instruction[31:26] == 6'b011000;
+assign op_b = instruction[31:26] == 6'b110000;
+assign op_bi = instruction[31:26] == 6'b111000;
+assign op_be = instruction[31:26] == 6'b010001;
+assign op_bg = instruction[31:26] == 6'b010010;
+assign op_bge = instruction[31:26] == 6'b010011;
+assign op_bgeu = instruction[31:26] == 6'b010100;
+assign op_bgu = instruction[31:26] == 6'b010101;
+assign op_bne = instruction[31:26] == 6'b010111;
+assign op_call = instruction[31:26] == 6'b110110;
+assign op_calli = instruction[31:26] == 6'b111110;
+assign op_cmpe = instruction[30:26] == 5'b11001;
+assign op_cmpg = instruction[30:26] == 5'b11010;
+assign op_cmpge = instruction[30:26] == 5'b11011;
+assign op_cmpgeu = instruction[30:26] == 5'b11100;
+assign op_cmpgu = instruction[30:26] == 5'b11101;
+assign op_cmpne = instruction[30:26] == 5'b11111;
+
-
-assign op_lb = instruction[ 31:26] == 6'b000100;
-assign op_lbu = instruction[ 31:26] == 6'b010000;
-assign op_lh = instruction[ 31:26] == 6'b000111;
-assign op_lhu = instruction[ 31:26] == 6'b001011;
-assign op_lw = instruction[ 31:26] == 6'b001010;
-
+assign op_lb = instruction[31:26] == 6'b000100;
+assign op_lbu = instruction[31:26] == 6'b010000;
+assign op_lh = instruction[31:26] == 6'b000111;
+assign op_lhu = instruction[31:26] == 6'b001011;
+assign op_lw = instruction[31:26] == 6'b001010;
+
-
-
-
-assign op_mul = instruction[ 30:26] == 5'b00010;
+assign op_mul = instruction[30:26] == 5'b00010;
-assign op_nor = instruction[ 30:26] == 5'b00001;
-assign op_or = instruction[ 30:26] == 5'b01110;
-assign op_orhi = instruction[ 31:26] == 6'b011110;
-assign op_raise = instruction[ 31:26] == 6'b101011;
-assign op_rcsr = instruction[ 31:26] == 6'b100100;
-assign op_sb = instruction[ 31:26] == 6'b001100;
-
-
-assign op_sextb = instruction[ 31:26] == 6'b101100;
-assign op_sexth = instruction[ 31:26] == 6'b110111;
+assign op_nor = instruction[30:26] == 5'b00001;
+assign op_or = instruction[30:26] == 5'b01110;
+assign op_orhi = instruction[31:26] == 6'b011110;
+assign op_raise = instruction[31:26] == 6'b101011;
+assign op_rcsr = instruction[31:26] == 6'b100100;
+assign op_sb = instruction[31:26] == 6'b001100;
+assign op_sextb = instruction[31:26] == 6'b101100;
+assign op_sexth = instruction[31:26] == 6'b110111;
-assign op_sh = instruction[ 31:26] == 6'b000011;
-
-
-assign op_sl = instruction[ 30:26] == 5'b01111;
+assign op_sh = instruction[31:26] == 6'b000011;
+assign op_sl = instruction[30:26] == 5'b01111;
-assign op_sr = instruction[ 30:26] == 5'b00101;
-assign op_sru = instruction[ 30:26] == 5'b00000;
-assign op_sub = instruction[ 31:26] == 6'b110010;
-assign op_sw = instruction[ 31:26] == 6'b010110;
-assign op_user = instruction[ 31:26] == 6'b110011;
-assign op_wcsr = instruction[ 31:26] == 6'b110100;
-assign op_xnor = instruction[ 30:26] == 5'b01001;
-assign op_xor = instruction[ 30:26] == 5'b00110;
+assign op_sr = instruction[30:26] == 5'b00101;
+assign op_sru = instruction[30:26] == 5'b00000;
+assign op_sub = instruction[31:26] == 6'b110010;
+assign op_sw = instruction[31:26] == 6'b010110;
+assign op_user = instruction[31:26] == 6'b110011;
+assign op_wcsr = instruction[31:26] == 6'b110100;
+assign op_xnor = instruction[30:26] == 5'b01001;
+assign op_xor = instruction[30:26] == 5'b00110;
assign arith = op_add | op_sub;
@@ -32566,35 +29409,26 @@ assign bi_conditional = op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne;
assign bi_unconditional = op_bi;
assign bra = op_b | bi_unconditional | bi_conditional;
assign call = op_call | op_calli;
-
-
-assign shift = op_sl | op_sr | op_sru;
+assign shift = op_sl | op_sr | op_sru;
-
+
-
-
+
-
-
-
-assign sext = op_sextb | op_sexth;
+assign sext = op_sextb | op_sexth;
-
-
-assign multiply = op_mul;
+assign multiply = op_mul;
-
+
-
assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
assign store = op_sb | op_sh | op_sw;
@@ -32603,39 +29437,34 @@ always @(*)
begin
if (call)
- d_result_sel_0 = 1'b1;
+ d_result_sel_0 = 1'b1;
else
- d_result_sel_0 = 1'b0;
+ d_result_sel_0 = 1'b0;
if (call)
- d_result_sel_1 = 2'b00;
+ d_result_sel_1 = 2'b00;
else if ((instruction[31] == 1'b0) && !bra)
- d_result_sel_1 = 2'b10;
+ d_result_sel_1 = 2'b10;
else
- d_result_sel_1 = 2'b01;
+ d_result_sel_1 = 2'b01;
- x_result_sel_csr = 1'b0;
-
+ x_result_sel_csr = 1'b0;
+
-
-
+
-
-
-
- x_result_sel_sext = 1'b0;
+ x_result_sel_sext = 1'b0;
- x_result_sel_logic = 1'b0;
-
+ x_result_sel_logic = 1'b0;
+
-
- x_result_sel_add = 1'b0;
+ x_result_sel_add = 1'b0;
if (op_rcsr)
- x_result_sel_csr = 1'b1;
-
+ x_result_sel_csr = 1'b1;
+
@@ -32649,84 +29478,66 @@ begin
-
-
+
-
-
-
- else if (sext)
- x_result_sel_sext = 1'b1;
+ else if (sext)
+ x_result_sel_sext = 1'b1;
else if (logical)
- x_result_sel_logic = 1'b1;
-
+ x_result_sel_logic = 1'b1;
+
-
else
- x_result_sel_add = 1'b1;
+ x_result_sel_add = 1'b1;
m_result_sel_compare = cmp;
-
-
- m_result_sel_shift = shift;
+ m_result_sel_shift = shift;
w_result_sel_load = load;
-
-
- w_result_sel_mul = op_mul;
+ w_result_sel_mul = op_mul;
end
assign x_bypass_enable = arith
| logical
-
+
-
-
+
-
-
+
-
-
+
-
-
-
- | sext
+ | sext
-
+
-
| op_rcsr
;
assign m_bypass_enable = x_bypass_enable
-
-
- | shift
+ | shift
| cmp
;
@@ -32752,32 +29563,27 @@ assign sign_extend = instruction[28];
assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
assign logic_op = instruction[29:26];
-
-
+
assign direction = instruction[29];
-
assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
-
+
-
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
-
+
-
-
+
-
assign csr_write_enable = op_wcsr;
@@ -32791,11 +29597,11 @@ assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, inst
assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
-assign immediate = select_high_immediate == 1'b1
+assign immediate = select_high_immediate == 1'b1
? high_immediate
: extended_immediate;
-assign branch_offset = select_call_immediate == 1'b1
+assign branch_offset = select_call_immediate == 1'b1
? call_immediate
: branch_immediate;
@@ -32836,10 +29642,7 @@ endmodule
-
-
-
-
+
@@ -32869,9 +29672,9 @@ endmodule
-
+
@@ -33155,9 +29958,7 @@ endmodule
-
-
-
+
@@ -33609,12 +30410,8 @@ endmodule
-
-
-
-
-
+
@@ -33644,9 +30441,9 @@ endmodule
-
+
@@ -33930,9 +30727,7 @@ endmodule
-
-
-
+
@@ -34437,10 +31232,7 @@ endmodule
-
-
-
-
+
@@ -34471,9 +31263,8 @@ endmodule
-
-
+
@@ -34757,9 +31548,7 @@ endmodule
-
-
-
+
@@ -35120,11 +31909,7 @@ endmodule
-
-
-
-
-
+
@@ -35154,9 +31939,9 @@ endmodule
-
+
@@ -35441,8 +32226,6 @@ endmodule
-
-
@@ -35461,47 +32244,40 @@ module lm32_instruction_unit_medium (
kill_f,
branch_predict_taken_d,
branch_predict_address_d,
-
+
-
exception_m,
branch_taken_m,
branch_mispredict_taken_m,
branch_target_m,
-
+
-
-
+
-
-
+
-
-
-
+
i_dat_i,
i_ack_i,
i_err_i,
i_rty_i,
-
-
+
-
pc_f,
@@ -35509,19 +32285,16 @@ module lm32_instruction_unit_medium (
pc_x,
pc_m,
pc_w,
-
+
-
-
+
-
-
-
+
i_dat_o,
i_adr_o,
@@ -35532,21 +32305,16 @@ module lm32_instruction_unit_medium (
i_cti_o,
i_lock_o,
i_bte_o,
-
-
+
-
-
+
-
-
-
- instruction_f,
+ instruction_f,
instruction_d
);
@@ -35583,46 +32351,40 @@ input valid_d;
input kill_f;
input branch_predict_taken_d;
-input [ ((32-2)+2-1):2] branch_predict_address_d;
+input [((32-2)+2-1):2] branch_predict_address_d;
-
+
-
input exception_m;
input branch_taken_m;
input branch_mispredict_taken_m;
-input [ ((32-2)+2-1):2] branch_target_m;
+input [((32-2)+2-1):2] branch_target_m;
-
+
-
-
+
-
-
+
-
-
-
-input [ (32-1):0] i_dat_i;
+
+input [(32-1):0] i_dat_i;
input i_ack_i;
input i_err_i;
input i_rty_i;
-
-
+
@@ -35632,20 +32394,19 @@ input i_rty_i;
-
-output [ ((32-2)+2-1):2] pc_f;
-reg [ ((32-2)+2-1):2] pc_f;
-output [ ((32-2)+2-1):2] pc_d;
-reg [ ((32-2)+2-1):2] pc_d;
-output [ ((32-2)+2-1):2] pc_x;
-reg [ ((32-2)+2-1):2] pc_x;
-output [ ((32-2)+2-1):2] pc_m;
-reg [ ((32-2)+2-1):2] pc_m;
-output [ ((32-2)+2-1):2] pc_w;
-reg [ ((32-2)+2-1):2] pc_w;
+output [((32-2)+2-1):2] pc_f;
+reg [((32-2)+2-1):2] pc_f;
+output [((32-2)+2-1):2] pc_d;
+reg [((32-2)+2-1):2] pc_d;
+output [((32-2)+2-1):2] pc_x;
+reg [((32-2)+2-1):2] pc_x;
+output [((32-2)+2-1):2] pc_m;
+reg [((32-2)+2-1):2] pc_m;
+output [((32-2)+2-1):2] pc_w;
+reg [((32-2)+2-1):2] pc_w;
-
+
@@ -35656,88 +32417,73 @@ reg [ ((32-2)+2-1):2] pc_w;
-
-
+
-
-
-
-output [ (32-1):0] i_dat_o;
-
+
+output [(32-1):0] i_dat_o;
+
+wire [(32-1):0] i_dat_o;
-wire [ (32-1):0] i_dat_o;
-
-
-output [ (32-1):0] i_adr_o;
-reg [ (32-1):0] i_adr_o;
+output [(32-1):0] i_adr_o;
+reg [(32-1):0] i_adr_o;
output i_cyc_o;
reg i_cyc_o;
-output [ (4-1):0] i_sel_o;
-
+output [(4-1):0] i_sel_o;
+
-
-wire [ (4-1):0] i_sel_o;
-
+wire [(4-1):0] i_sel_o;
output i_stb_o;
reg i_stb_o;
output i_we_o;
-
+
-
wire i_we_o;
-
-output [ (3-1):0] i_cti_o;
-reg [ (3-1):0] i_cti_o;
+output [(3-1):0] i_cti_o;
+reg [(3-1):0] i_cti_o;
output i_lock_o;
reg i_lock_o;
-output [ (2-1):0] i_bte_o;
-wire [ (2-1):0] i_bte_o;
-
+output [(2-1):0] i_bte_o;
+wire [(2-1):0] i_bte_o;
-
+
-
-
+
-
-
-
-output [ (32-1):0] instruction_f;
-wire [ (32-1):0] instruction_f;
+output [(32-1):0] instruction_f;
+wire [(32-1):0] instruction_f;
-output [ (32-1):0] instruction_d;
-reg [ (32-1):0] instruction_d;
+output [(32-1):0] instruction_d;
+reg [(32-1):0] instruction_d;
-reg [ ((32-2)+2-1):2] pc_a;
+reg [((32-2)+2-1):2] pc_a;
-
+
-
-
+
@@ -35748,43 +32494,32 @@ reg [ ((32-2)+2-1):2] pc_a;
-
-
-
-reg [ (32-1):0] wb_data_f;
+reg [(32-1):0] wb_data_f;
-
-
+
+
-
+
-
+
-
+
-
-
-
-
-
-
-
-
-
+
@@ -35840,8 +32575,7 @@ endfunction
-
-
+
@@ -35887,10 +32621,9 @@ endfunction
-
-
+
@@ -35926,8 +32659,7 @@ endfunction
-
-
+
@@ -35939,86 +32671,73 @@ endfunction
-
always @(*)
begin
-
+
-
- if (branch_taken_m == 1'b1)
- if ((branch_mispredict_taken_m == 1'b1) && (exception_m == 1'b0))
+ if (branch_taken_m == 1'b1)
+ if ((branch_mispredict_taken_m == 1'b1) && (exception_m == 1'b0))
pc_a = pc_x;
else
pc_a = branch_target_m;
-
+
-
else
- if ( (valid_d == 1'b1) && (branch_predict_taken_d == 1'b1) )
+ if ( (valid_d == 1'b1) && (branch_predict_taken_d == 1'b1) )
pc_a = branch_predict_address_d;
else
-
+
-
pc_a = pc_f + 1'b1;
end
-
+
-
-
+
-
-
+
-
assign instruction_f = wb_data_f;
-
-
-
-
-
-
+
+
assign i_dat_o = 32'd0;
-assign i_we_o = 1'b0;
+assign i_we_o = 1'b0;
assign i_sel_o = 4'b1111;
-
-assign i_bte_o = 2'b00;
-
+assign i_bte_o = 2'b00;
-
+
@@ -36044,7 +32763,6 @@ assign i_bte_o = 2'b00;
-
@@ -36053,31 +32771,31 @@ assign i_bte_o = 2'b00;
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- pc_f <= ( 32'h00000000-4)/4;
- pc_d <= { (32-2){1'b0}};
- pc_x <= { (32-2){1'b0}};
- pc_m <= { (32-2){1'b0}};
- pc_w <= { (32-2){1'b0}};
+ pc_f <= (32'h00000000-4)/4;
+ pc_d <= {(32-2){1'b0}};
+ pc_x <= {(32-2){1'b0}};
+ pc_m <= {(32-2){1'b0}};
+ pc_w <= {(32-2){1'b0}};
end
else
begin
- if (stall_f == 1'b0)
+ if (stall_f == 1'b0)
pc_f <= pc_a;
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
pc_d <= pc_f;
- if (stall_x == 1'b0)
+ if (stall_x == 1'b0)
pc_x <= pc_d;
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
pc_m <= pc_x;
pc_w <= pc_m;
end
end
-
+
@@ -36107,8 +32825,7 @@ end
-
-
+
@@ -36121,8 +32838,7 @@ end
-
-
+
@@ -36135,11 +32851,9 @@ end
+
-
-
-
-
+
@@ -36255,111 +32969,99 @@ end
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_adr_o <= { 32{1'b0}};
- i_cti_o <= 3'b111;
- i_lock_o <= 1'b0;
- wb_data_f <= { 32{1'b0}};
-
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_adr_o <= {32{1'b0}};
+ i_cti_o <= 3'b111;
+ i_lock_o <= 1'b0;
+ wb_data_f <= {32{1'b0}};
+
-
end
else
begin
- if (i_cyc_o == 1'b1)
+ if (i_cyc_o == 1'b1)
begin
- if((i_ack_i == 1'b1) || (i_err_i == 1'b1))
+ if((i_ack_i == 1'b1) || (i_err_i == 1'b1))
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
wb_data_f <= i_dat_i;
end
-
+
-
end
else
begin
- if ( (stall_a == 1'b0)
-
+ if ( (stall_a == 1'b0)
+
-
)
begin
-
+
-
i_adr_o <= {pc_a, 2'b00};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
-
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
+
-
end
else
begin
- if ( (stall_a == 1'b0)
-
+ if ( (stall_a == 1'b0)
+
-
)
begin
-
+
-
end
end
end
end
end
-
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- instruction_d <= { 32{1'b0}};
-
+ instruction_d <= {32{1'b0}};
+
-
end
else
begin
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
begin
instruction_d <= instruction_f;
-
+
-
end
end
end
@@ -36393,10 +33095,7 @@ endmodule
-
-
-
-
+
@@ -36426,9 +33125,9 @@ endmodule
-
+
@@ -36712,9 +33411,7 @@ endmodule
-
-
-
+
@@ -37181,11 +33878,7 @@ endmodule
-
-
-
-
-
+
@@ -37215,9 +33908,9 @@ endmodule
-
+
@@ -37502,8 +34195,6 @@ endmodule
-
-
@@ -37515,19 +34206,16 @@ module lm32_interrupt_medium (
interrupt,
stall_x,
-
+
-
exception,
-
eret_q_x,
-
+
-
csr,
csr_write_data,
csr_write_enable,
@@ -37541,7 +34229,7 @@ module lm32_interrupt_medium (
-parameter interrupts = 32;
+parameter interrupts = 32;
@@ -37554,22 +34242,19 @@ input [interrupts-1:0] interrupt;
input stall_x;
-
+
-
input exception;
-
input eret_q_x;
-
+
-
-input [ (3-1):0] csr;
-input [ (32-1):0] csr_write_data;
+input [(3-1):0] csr;
+input [(32-1):0] csr_write_data;
input csr_write_enable;
@@ -37579,8 +34264,8 @@ input csr_write_enable;
output interrupt_exception;
wire interrupt_exception;
-output [ (32-1):0] csr_read_data;
-reg [ (32-1):0] csr_read_data;
+output [(32-1):0] csr_read_data;
+reg [(32-1):0] csr_read_data;
@@ -37594,10 +34279,9 @@ wire [interrupts-1:0] interrupt_n_exception;
reg ie;
reg eie;
-
+
-
reg [interrupts-1:0] ip;
reg [interrupts-1:0] im;
@@ -37614,13 +34298,11 @@ assign interrupt_exception = (|interrupt_n_exception) & ie;
assign asserted = ip | interrupt;
-assign ie_csr_read_data = {{ 32-3{1'b0}},
-
+assign ie_csr_read_data = {{32-3{1'b0}},
+
-
1'b0,
-
eie,
ie
@@ -37634,20 +34316,18 @@ generate
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
-
+ 3'h0: csr_read_data = {{32-3{1'b0}},
+
-
1'b0,
-
eie,
ie
};
- 3'h2: csr_read_data = ip;
- 3'h1: csr_read_data = im;
- default: csr_read_data = { 32{1'bx}};
+ 3'h2: csr_read_data = ip;
+ 3'h1: csr_read_data = im;
+ default: csr_read_data = {32{1'bx}};
endcase
end
end
@@ -37657,19 +34337,17 @@ end
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
-
+ 3'h0: csr_read_data = {{32-3{1'b0}},
+
-
1'b0,
-
eie,
ie
};
- 3'h2: csr_read_data = ip;
- default: csr_read_data = { 32{1'bx}};
+ 3'h2: csr_read_data = ip;
+ default: csr_read_data = {32{1'bx}};
endcase
end
end
@@ -37679,9 +34357,8 @@ endgenerate
-
-
- reg [ 10:0] eie_delay = 0;
+
+ reg [10:0] eie_delay = 0;
generate
@@ -37690,16 +34367,15 @@ generate
if (interrupts > 1)
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- ie <= 1'b0;
- eie <= 1'b0;
-
+ ie <= 1'b0;
+ eie <= 1'b0;
+
-
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
eie_delay <= 0;
@@ -37709,7 +34385,7 @@ always @(posedge clk_i )
begin
ip <= asserted;
-
+
@@ -37723,52 +34399,48 @@ always @(posedge clk_i )
-
- if (exception == 1'b1)
+ if (exception == 1'b1)
begin
eie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
-
- else if (stall_x == 1'b0)
+ else if (stall_x == 1'b0)
begin
if(eie_delay[0])
ie <= eie;
- eie_delay <= {1'b0, eie_delay[ 10:1]};
+ eie_delay <= {1'b0, eie_delay[10:1]};
- if (eret_q_x == 1'b1) begin
+ if (eret_q_x == 1'b1) begin
- eie_delay[ 10] <= 1'b1;
- eie_delay[ 10-1:0] <= 0;
+ eie_delay[10] <= 1'b1;
+ eie_delay[10-1:0] <= 0;
end
-
+
-
- else if (csr_write_enable == 1'b1)
+ else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 3'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
+
-
end
- if (csr == 3'h1)
+ if (csr == 3'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 3'h2)
+ if (csr == 3'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -37778,16 +34450,15 @@ end
else
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- ie <= 1'b0;
- eie <= 1'b0;
-
+ ie <= 1'b0;
+ eie <= 1'b0;
+
-
ip <= {interrupts{1'b0}};
eie_delay <= 0;
end
@@ -37795,7 +34466,7 @@ always @(posedge clk_i )
begin
ip <= asserted;
-
+
@@ -37809,48 +34480,44 @@ always @(posedge clk_i )
-
- if (exception == 1'b1)
+ if (exception == 1'b1)
begin
eie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
-
- else if (stall_x == 1'b0)
+ else if (stall_x == 1'b0)
begin
if(eie_delay[0])
ie <= eie;
- eie_delay <= {1'b0, eie_delay[ 10:1]};
+ eie_delay <= {1'b0, eie_delay[10:1]};
- if (eret_q_x == 1'b1) begin
+ if (eret_q_x == 1'b1) begin
- eie_delay[ 10] <= 1'b1;
- eie_delay[ 10-1:0] <= 0;
+ eie_delay[10] <= 1'b1;
+ eie_delay[10-1:0] <= 0;
end
-
+
-
- else if (csr_write_enable == 1'b1)
+ else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 3'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
+
-
end
- if (csr == 3'h2)
+ if (csr == 3'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -37890,72 +34557,41 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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@@ -37983,236 +34619,157 @@ endmodule
-
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@@ -38222,209 +34779,126 @@ endmodule
-
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@@ -38443,19 +34917,16 @@ module lm32_top_medium_debug (
interrupt,
-
+
-
-
-
+
I_DAT_I,
I_ACK_I,
I_ERR_I,
I_RTY_I,
-
D_DAT_I,
@@ -38463,15 +34934,13 @@ module lm32_top_medium_debug (
D_ERR_I,
D_RTY_I,
-
+
-
-
-
+
I_DAT_O,
I_ADR_O,
@@ -38482,7 +34951,6 @@ module lm32_top_medium_debug (
I_CTI_O,
I_LOCK_O,
I_BTE_O,
-
D_DAT_O,
@@ -38504,25 +34972,22 @@ input clk_i;
input rst_i;
-input [ (32-1):0] interrupt;
+input [(32-1):0] interrupt;
-
+
-
-
-
-input [ (32-1):0] I_DAT_I;
+
+input [(32-1):0] I_DAT_I;
input I_ACK_I;
input I_ERR_I;
input I_RTY_I;
-
-input [ (32-1):0] D_DAT_I;
+input [(32-1):0] D_DAT_I;
input D_ACK_I;
input D_ERR_I;
input D_RTY_I;
@@ -38531,7 +34996,7 @@ input D_RTY_I;
-
+
@@ -38542,68 +35007,63 @@ input D_RTY_I;
-
-
-
-output [ (32-1):0] I_DAT_O;
-wire [ (32-1):0] I_DAT_O;
-output [ (32-1):0] I_ADR_O;
-wire [ (32-1):0] I_ADR_O;
+
+output [(32-1):0] I_DAT_O;
+wire [(32-1):0] I_DAT_O;
+output [(32-1):0] I_ADR_O;
+wire [(32-1):0] I_ADR_O;
output I_CYC_O;
wire I_CYC_O;
-output [ (4-1):0] I_SEL_O;
-wire [ (4-1):0] I_SEL_O;
+output [(4-1):0] I_SEL_O;
+wire [(4-1):0] I_SEL_O;
output I_STB_O;
wire I_STB_O;
output I_WE_O;
wire I_WE_O;
-output [ (3-1):0] I_CTI_O;
-wire [ (3-1):0] I_CTI_O;
+output [(3-1):0] I_CTI_O;
+wire [(3-1):0] I_CTI_O;
output I_LOCK_O;
wire I_LOCK_O;
-output [ (2-1):0] I_BTE_O;
-wire [ (2-1):0] I_BTE_O;
-
+output [(2-1):0] I_BTE_O;
+wire [(2-1):0] I_BTE_O;
-output [ (32-1):0] D_DAT_O;
-wire [ (32-1):0] D_DAT_O;
-output [ (32-1):0] D_ADR_O;
-wire [ (32-1):0] D_ADR_O;
+output [(32-1):0] D_DAT_O;
+wire [(32-1):0] D_DAT_O;
+output [(32-1):0] D_ADR_O;
+wire [(32-1):0] D_ADR_O;
output D_CYC_O;
wire D_CYC_O;
-output [ (4-1):0] D_SEL_O;
-wire [ (4-1):0] D_SEL_O;
+output [(4-1):0] D_SEL_O;
+wire [(4-1):0] D_SEL_O;
output D_STB_O;
wire D_STB_O;
output D_WE_O;
wire D_WE_O;
-output [ (3-1):0] D_CTI_O;
-wire [ (3-1):0] D_CTI_O;
+output [(3-1):0] D_CTI_O;
+wire [(3-1):0] D_CTI_O;
output D_LOCK_O;
wire D_LOCK_O;
-output [ (2-1):0] D_BTE_O;
-wire [ (2-1):0] D_BTE_O;
+output [(2-1):0] D_BTE_O;
+wire [(2-1):0] D_BTE_O;
-
-
+
-wire [ 7:0] jtag_reg_d;
-wire [ 7:0] jtag_reg_q;
+wire [7:0] jtag_reg_d;
+wire [7:0] jtag_reg_q;
wire jtag_update;
wire [2:0] jtag_reg_addr_d;
wire [2:0] jtag_reg_addr_q;
wire jtck;
wire jrstn;
-
-
+
@@ -38619,10 +35079,7 @@ wire jrstn;
-
-
-
-
+
@@ -38675,46 +35132,37 @@ endfunction
-
lm32_cpu_medium_debug cpu (
.clk_i (clk_i),
-
+
-
.rst_i (rst_i),
-
-
- .interrupt (interrupt),
+ .interrupt (interrupt),
-
+
-
-
-
+
.jtag_clk (jtck),
.jtag_update (jtag_update),
.jtag_reg_q (jtag_reg_q),
.jtag_reg_addr_q (jtag_reg_addr_q),
-
-
-
+
.I_DAT_I (I_DAT_I),
.I_ACK_I (I_ACK_I),
.I_ERR_I (I_ERR_I),
.I_RTY_I (I_RTY_I),
-
.D_DAT_I (D_DAT_I),
@@ -38722,7 +35170,7 @@ lm32_cpu_medium_debug cpu (
.D_ERR_I (D_ERR_I),
.D_RTY_I (D_RTY_I),
-
+
@@ -38732,22 +35180,17 @@ lm32_cpu_medium_debug cpu (
-
-
-
+
.jtag_reg_d (jtag_reg_d),
.jtag_reg_addr_d (jtag_reg_addr_d),
-
-
+
-
-
-
+
.I_DAT_O (I_DAT_O),
.I_ADR_O (I_ADR_O),
@@ -38758,8 +35201,7 @@ lm32_cpu_medium_debug cpu (
.I_CTI_O (I_CTI_O),
.I_LOCK_O (I_LOCK_O),
.I_BTE_O (I_BTE_O),
-
-
+
.D_DAT_O (D_DAT_O),
.D_ADR_O (D_ADR_O),
@@ -38772,8 +35214,7 @@ lm32_cpu_medium_debug cpu (
.D_BTE_O (D_BTE_O)
);
-
-
+
jtag_cores jtag_cores (
@@ -38786,7 +35227,6 @@ jtag_cores jtag_cores (
.jtck (jtck),
.jrstn (jrstn)
);
-
endmodule
@@ -38818,10 +35258,7 @@ endmodule
-
-
-
-
+
@@ -38851,9 +35288,9 @@ endmodule
-
+
@@ -39135,24 +35572,15 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
@@ -39164,29 +35592,25 @@ module lm32_mc_arithmetic_medium_debug (
rst_i,
stall_d,
kill_x,
-
+
-
-
+
-
-
+
-
operand_0_d,
operand_1_d,
result_x,
-
+
-
stall_request_x
);
@@ -39198,35 +35622,31 @@ input clk_i;
input rst_i;
input stall_d;
input kill_x;
-
+
-
-
+
-
-
+
-
-input [ (32-1):0] operand_0_d;
-input [ (32-1):0] operand_1_d;
+input [(32-1):0] operand_0_d;
+input [(32-1):0] operand_1_d;
-output [ (32-1):0] result_x;
-reg [ (32-1):0] result_x;
-
+output [(32-1):0] result_x;
+reg [(32-1):0] result_x;
+
-
output stall_request_x;
wire stall_request_x;
@@ -39234,18 +35654,17 @@ wire stall_request_x;
-reg [ (32-1):0] p;
-reg [ (32-1):0] a;
-reg [ (32-1):0] b;
-
+reg [(32-1):0] p;
+reg [(32-1):0] a;
+reg [(32-1):0] b;
+
-
-reg [ 2:0] state;
+reg [2:0] state;
reg [5:0] cycles;
-
+
@@ -39255,16 +35674,14 @@ reg [5:0] cycles;
+assign stall_request_x = state != 3'b000;
-assign stall_request_x = state != 3'b000;
-
-
+
-
-
+
@@ -39274,54 +35691,48 @@ assign stall_request_x = state != 3'b000;
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
cycles <= {6{1'b0}};
- p <= { 32{1'b0}};
- a <= { 32{1'b0}};
- b <= { 32{1'b0}};
-
+ p <= {32{1'b0}};
+ a <= {32{1'b0}};
+ b <= {32{1'b0}};
+
-
-
+
-
- result_x <= { 32{1'b0}};
- state <= 3'b000;
+ result_x <= {32{1'b0}};
+ state <= 3'b000;
end
else
begin
-
+
-
case (state)
- 3'b000:
+ 3'b000:
begin
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
begin
- cycles <= 32;
+ cycles <= 32;
p <= 32'b0;
a <= operand_0_d;
b <= operand_1_d;
-
+
-
-
+
-
-
+
@@ -39338,11 +35749,10 @@ begin
-
end
end
-
+
@@ -39385,9 +35795,8 @@ begin
-
-
+
@@ -39399,9 +35808,8 @@ begin
-
-
+
@@ -39418,7 +35826,6 @@ begin
-
endcase
end
@@ -39489,10 +35896,7 @@ endmodule
-
-
-
-
+
@@ -39522,9 +35926,9 @@ endmodule
-
+
@@ -39809,48 +36213,38 @@ endmodule
-
-
module lm32_cpu_medium_debug (
clk_i,
-
+
-
rst_i,
-
-
- interrupt,
+ interrupt,
-
+
-
-
-
+
jtag_clk,
jtag_update,
jtag_reg_q,
jtag_reg_addr_q,
-
-
-
+
I_DAT_I,
I_ACK_I,
I_ERR_I,
I_RTY_I,
-
D_DAT_I,
@@ -39858,7 +36252,7 @@ module lm32_cpu_medium_debug (
D_ERR_I,
D_RTY_I,
-
+
@@ -39868,22 +36262,17 @@ module lm32_cpu_medium_debug (
-
-
-
+
jtag_reg_d,
jtag_reg_addr_d,
-
-
+
-
-
-
+
I_DAT_O,
I_ADR_O,
@@ -39894,7 +36283,6 @@ module lm32_cpu_medium_debug (
I_CTI_O,
I_LOCK_O,
I_BTE_O,
-
D_DAT_O,
@@ -39912,21 +36300,18 @@ module lm32_cpu_medium_debug (
-parameter eba_reset = 32'h00000000;
-
-
-parameter deba_reset = 32'h10000000;
+parameter eba_reset = 32'h00000000;
+parameter deba_reset = 32'h10000000;
-
-
-parameter icache_associativity = 1;
-parameter icache_sets = 256;
-parameter icache_bytes_per_line = 16;
-parameter icache_base_address = 32'h0;
-parameter icache_limit = 32'h7fffffff;
+parameter icache_associativity = 1;
+parameter icache_sets = 256;
+parameter icache_bytes_per_line = 16;
+parameter icache_base_address = 32'h0;
+parameter icache_limit = 32'h7fffffff;
+
@@ -39934,44 +36319,35 @@ parameter icache_limit = 32'h7fffffff;
-
-
+
-
parameter dcache_associativity = 1;
parameter dcache_sets = 512;
parameter dcache_bytes_per_line = 16;
parameter dcache_base_address = 0;
parameter dcache_limit = 0;
-
-
-
-parameter watchpoints = 32'h4;
-
+parameter watchpoints = 32'h4;
+
-
+
-
parameter breakpoints = 0;
-
-
-
-parameter interrupts = 32;
-
+parameter interrupts = 32;
+
@@ -39979,43 +36355,35 @@ parameter interrupts = 32;
input clk_i;
-
+
-
input rst_i;
-
-
-input [ (32-1):0] interrupt;
+input [(32-1):0] interrupt;
-
+
-
-
-
+
input jtag_clk;
input jtag_update;
-input [ 7:0] jtag_reg_q;
+input [7:0] jtag_reg_q;
input [2:0] jtag_reg_addr_q;
-
-
-
-input [ (32-1):0] I_DAT_I;
+
+input [(32-1):0] I_DAT_I;
input I_ACK_I;
input I_ERR_I;
input I_RTY_I;
-
-input [ (32-1):0] D_DAT_I;
+input [(32-1):0] D_DAT_I;
input D_ACK_I;
input D_ERR_I;
input D_RTY_I;
@@ -40024,7 +36392,7 @@ input D_RTY_I;
-
+
@@ -40041,17 +36409,14 @@ input D_RTY_I;
-
-
-
-output [ 7:0] jtag_reg_d;
-wire [ 7:0] jtag_reg_d;
+
+output [7:0] jtag_reg_d;
+wire [7:0] jtag_reg_d;
output [2:0] jtag_reg_addr_d;
wire [2:0] jtag_reg_addr_d;
-
-
+
@@ -40062,59 +36427,54 @@ wire [2:0] jtag_reg_addr_d;
-
-
-
-output [ (32-1):0] I_DAT_O;
-wire [ (32-1):0] I_DAT_O;
-output [ (32-1):0] I_ADR_O;
-wire [ (32-1):0] I_ADR_O;
+
+output [(32-1):0] I_DAT_O;
+wire [(32-1):0] I_DAT_O;
+output [(32-1):0] I_ADR_O;
+wire [(32-1):0] I_ADR_O;
output I_CYC_O;
wire I_CYC_O;
-output [ (4-1):0] I_SEL_O;
-wire [ (4-1):0] I_SEL_O;
+output [(4-1):0] I_SEL_O;
+wire [(4-1):0] I_SEL_O;
output I_STB_O;
wire I_STB_O;
output I_WE_O;
wire I_WE_O;
-output [ (3-1):0] I_CTI_O;
-wire [ (3-1):0] I_CTI_O;
+output [(3-1):0] I_CTI_O;
+wire [(3-1):0] I_CTI_O;
output I_LOCK_O;
wire I_LOCK_O;
-output [ (2-1):0] I_BTE_O;
-wire [ (2-1):0] I_BTE_O;
-
+output [(2-1):0] I_BTE_O;
+wire [(2-1):0] I_BTE_O;
-output [ (32-1):0] D_DAT_O;
-wire [ (32-1):0] D_DAT_O;
-output [ (32-1):0] D_ADR_O;
-wire [ (32-1):0] D_ADR_O;
+output [(32-1):0] D_DAT_O;
+wire [(32-1):0] D_DAT_O;
+output [(32-1):0] D_ADR_O;
+wire [(32-1):0] D_ADR_O;
output D_CYC_O;
wire D_CYC_O;
-output [ (4-1):0] D_SEL_O;
-wire [ (4-1):0] D_SEL_O;
+output [(4-1):0] D_SEL_O;
+wire [(4-1):0] D_SEL_O;
output D_STB_O;
wire D_STB_O;
output D_WE_O;
wire D_WE_O;
-output [ (3-1):0] D_CTI_O;
-wire [ (3-1):0] D_CTI_O;
+output [(3-1):0] D_CTI_O;
+wire [(3-1):0] D_CTI_O;
output D_LOCK_O;
wire D_LOCK_O;
-output [ (2-1):0] D_BTE_O;
-wire [ (2-1):0] D_BTE_O;
-
+output [(2-1):0] D_BTE_O;
+wire [(2-1):0] D_BTE_O;
-
-reg valid_a;
+reg valid_a;
reg valid_f;
reg valid_d;
@@ -40123,7 +36483,7 @@ reg valid_m;
reg valid_w;
wire q_x;
-wire [ (32-1):0] immediate_d;
+wire [(32-1):0] immediate_d;
wire load_d;
reg load_x;
reg load_m;
@@ -40132,13 +36492,13 @@ wire store_q_x;
wire store_d;
reg store_x;
reg store_m;
-wire [ 1:0] size_d;
-reg [ 1:0] size_x;
+wire [1:0] size_d;
+reg [1:0] size_x;
wire branch_d;
wire branch_predict_d;
wire branch_predict_taken_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
wire bi_unconditional;
wire bi_conditional;
reg branch_x;
@@ -40150,60 +36510,51 @@ reg branch_predict_taken_m;
wire branch_mispredict_taken_m;
wire branch_flushX_m;
wire branch_reg_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
-wire [ 0:0] d_result_sel_0_d;
-wire [ 1:0] d_result_sel_1_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [0:0] d_result_sel_0_d;
+wire [1:0] d_result_sel_1_d;
wire x_result_sel_csr_d;
reg x_result_sel_csr_x;
-
+
-
-
+
-
-
-
+
wire x_result_sel_sext_d;
reg x_result_sel_sext_x;
-
wire x_result_sel_logic_d;
reg x_result_sel_logic_x;
-
+
-
wire x_result_sel_add_d;
reg x_result_sel_add_x;
wire m_result_sel_compare_d;
reg m_result_sel_compare_x;
reg m_result_sel_compare_m;
-
-
+
wire m_result_sel_shift_d;
reg m_result_sel_shift_x;
reg m_result_sel_shift_m;
-
wire w_result_sel_load_d;
reg w_result_sel_load_x;
reg w_result_sel_load_m;
reg w_result_sel_load_w;
-
-
+
wire w_result_sel_mul_d;
reg w_result_sel_mul_x;
reg w_result_sel_mul_m;
reg w_result_sel_mul_w;
-
wire x_bypass_enable_d;
reg x_bypass_enable_x;
@@ -40220,22 +36571,20 @@ wire write_enable_q_m;
reg write_enable_w;
wire write_enable_q_w;
wire read_enable_0_d;
-wire [ (5-1):0] read_idx_0_d;
+wire [(5-1):0] read_idx_0_d;
wire read_enable_1_d;
-wire [ (5-1):0] read_idx_1_d;
-wire [ (5-1):0] write_idx_d;
-reg [ (5-1):0] write_idx_x;
-reg [ (5-1):0] write_idx_m;
-reg [ (5-1):0] write_idx_w;
-wire [ (5-1):0] csr_d;
-reg [ (5-1):0] csr_x;
-wire [ (3-1):0] condition_d;
-reg [ (3-1):0] condition_x;
-
-
+wire [(5-1):0] read_idx_1_d;
+wire [(5-1):0] write_idx_d;
+reg [(5-1):0] write_idx_x;
+reg [(5-1):0] write_idx_m;
+reg [(5-1):0] write_idx_w;
+wire [(5-1):0] csr_d;
+reg [(5-1):0] csr_x;
+wire [(3-1):0] condition_d;
+reg [(3-1):0] condition_x;
+
wire break_d;
reg break_x;
-
wire scall_d;
reg scall_x;
@@ -40243,70 +36592,60 @@ wire eret_d;
reg eret_x;
wire eret_q_x;
reg eret_m;
-
+
-
-
-
+
wire bret_d;
reg bret_x;
wire bret_q_x;
reg bret_m;
-
-
-
+
wire csr_write_enable_d;
reg csr_write_enable_x;
wire csr_write_enable_q_x;
-
+
-
-
+
+reg [(32-1):0] d_result_0;
+reg [(32-1):0] d_result_1;
+reg [(32-1):0] x_result;
+reg [(32-1):0] m_result;
+reg [(32-1):0] w_result;
-reg [ (32-1):0] d_result_0;
-reg [ (32-1):0] d_result_1;
-reg [ (32-1):0] x_result;
-reg [ (32-1):0] m_result;
-reg [ (32-1):0] w_result;
-
-reg [ (32-1):0] operand_0_x;
-reg [ (32-1):0] operand_1_x;
-reg [ (32-1):0] store_operand_x;
-reg [ (32-1):0] operand_m;
-reg [ (32-1):0] operand_w;
-
+reg [(32-1):0] operand_0_x;
+reg [(32-1):0] operand_1_x;
+reg [(32-1):0] store_operand_x;
+reg [(32-1):0] operand_m;
+reg [(32-1):0] operand_w;
-
-reg [ (32-1):0] reg_data_live_0;
-reg [ (32-1):0] reg_data_live_1;
-reg use_buf;
-reg [ (32-1):0] reg_data_buf_0;
-reg [ (32-1):0] reg_data_buf_1;
-
-
+reg [(32-1):0] reg_data_live_0;
+reg [(32-1):0] reg_data_live_1;
+reg use_buf;
+reg [(32-1):0] reg_data_buf_0;
+reg [(32-1):0] reg_data_buf_1;
-
+
-wire [ (32-1):0] reg_data_0;
-wire [ (32-1):0] reg_data_1;
-reg [ (32-1):0] bypass_data_0;
-reg [ (32-1):0] bypass_data_1;
+wire [(32-1):0] reg_data_0;
+wire [(32-1):0] reg_data_1;
+reg [(32-1):0] bypass_data_0;
+reg [(32-1):0] bypass_data_1;
wire reg_write_enable_q_w;
reg interlock;
@@ -40321,64 +36660,54 @@ wire stall_m;
wire adder_op_d;
reg adder_op_x;
reg adder_op_x_n;
-wire [ (32-1):0] adder_result_x;
+wire [(32-1):0] adder_result_x;
wire adder_overflow_x;
wire adder_carry_n_x;
-wire [ 3:0] logic_op_d;
-reg [ 3:0] logic_op_x;
-wire [ (32-1):0] logic_result_x;
-
-
-
+wire [3:0] logic_op_d;
+reg [3:0] logic_op_x;
+wire [(32-1):0] logic_result_x;
-wire [ (32-1):0] sextb_result_x;
-wire [ (32-1):0] sexth_result_x;
-wire [ (32-1):0] sext_result_x;
+wire [(32-1):0] sextb_result_x;
+wire [(32-1):0] sexth_result_x;
+wire [(32-1):0] sext_result_x;
-
-
+
+
-
wire direction_d;
reg direction_x;
reg direction_m;
-wire [ (32-1):0] shifter_result_m;
-
+wire [(32-1):0] shifter_result_m;
-
+
-
-
+
-
-
-
-wire [ (32-1):0] multiplier_result_w;
+wire [(32-1):0] multiplier_result_w;
-
+
-
-
+
@@ -40387,55 +36716,45 @@ wire [ (32-1):0] multiplier_result_w;
-
-
+
-
-
-
-wire [ (32-1):0] interrupt_csr_read_data_x;
+wire [(32-1):0] interrupt_csr_read_data_x;
-wire [ (32-1):0] cfg;
-wire [ (32-1):0] cfg2;
-
+wire [(32-1):0] cfg;
+wire [(32-1):0] cfg2;
+
+reg [(32-1):0] csr_read_data_x;
-reg [ (32-1):0] csr_read_data_x;
-
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
-
-
-
-wire [ (32-1):0] instruction_f;
+wire [(32-1):0] instruction_f;
-wire [ (32-1):0] instruction_d;
-
-
+wire [(32-1):0] instruction_d;
+
wire iflush;
wire icache_stall_request;
wire icache_restart_request;
wire icache_refill_request;
wire icache_refilling;
-
-
+
@@ -40444,8 +36763,7 @@ wire icache_refilling;
-
-
+
@@ -40453,38 +36771,29 @@ wire icache_refilling;
-
-wire [ (32-1):0] load_data_w;
+wire [(32-1):0] load_data_w;
wire stall_wb_load;
-
-
-
-
-wire [ (32-1):0] jtx_csr_read_data;
-wire [ (32-1):0] jrx_csr_read_data;
+
+wire [(32-1):0] jtx_csr_read_data;
+wire [(32-1):0] jrx_csr_read_data;
-
-
+
wire jtag_csr_write_enable;
-wire [ (32-1):0] jtag_csr_write_data;
-wire [ (5-1):0] jtag_csr;
+wire [(32-1):0] jtag_csr_write_data;
+wire [(5-1):0] jtag_csr;
wire jtag_read_enable;
-wire [ 7:0] jtag_read_data;
+wire [7:0] jtag_read_data;
wire jtag_write_enable;
-wire [ 7:0] jtag_write_data;
-wire [ (32-1):0] jtag_address;
+wire [7:0] jtag_write_data;
+wire [(32-1):0] jtag_address;
wire jtag_access_complete;
-
-
-
-wire jtag_break;
+wire jtag_break;
-
@@ -40502,10 +36811,9 @@ wire cmp_overflow;
wire cmp_carry_n;
reg condition_met_x;
reg condition_met_m;
-
+
-
wire branch_taken_m;
wire kill_f;
@@ -40514,25 +36822,19 @@ wire kill_x;
wire kill_m;
wire kill_w;
-reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
-
-
-reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;
+reg [(clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
+reg [(clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;
-reg [ (3-1):0] eid_x;
-
+reg [(3-1):0] eid_x;
+
-
-
-
-
-
-wire dc_ss;
+
+wire dc_ss;
wire dc_re;
wire exception_x;
@@ -40545,46 +36847,35 @@ wire non_debug_exception_x;
reg non_debug_exception_m;
reg non_debug_exception_w;
wire non_debug_exception_q_w;
-
+
-
-
-
-
-
-wire reset_exception;
-
+wire reset_exception;
-
-wire interrupt_exception;
+wire interrupt_exception;
-
-
+
wire breakpoint_exception;
wire watchpoint_exception;
-
-
+
-
-
+
-
wire system_call_exception;
-
+
@@ -40592,10 +36883,7 @@ wire system_call_exception;
-
-
-
-
+
@@ -40651,7 +36939,6 @@ endfunction
-
lm32_instruction_unit_medium_debug #(
.associativity (icache_associativity),
.sets (icache_sets),
@@ -40673,48 +36960,39 @@ lm32_instruction_unit_medium_debug #(
.kill_f (kill_f),
.branch_predict_taken_d (branch_predict_taken_d),
.branch_predict_address_d (branch_predict_address_d),
-
+
-
.exception_m (exception_m),
.branch_taken_m (branch_taken_m),
.branch_mispredict_taken_m (branch_mispredict_taken_m),
.branch_target_m (branch_target_m),
-
-
- .iflush (iflush),
+ .iflush (iflush),
-
+
-
-
+
-
-
-
+
.i_dat_i (I_DAT_I),
.i_ack_i (I_ACK_I),
.i_err_i (I_ERR_I),
.i_rty_i (I_RTY_I),
-
-
-
+
.jtag_read_enable (jtag_read_enable),
.jtag_write_enable (jtag_write_enable),
.jtag_write_data (jtag_write_data),
.jtag_address (jtag_address),
-
@@ -40723,20 +37001,16 @@ lm32_instruction_unit_medium_debug #(
.pc_x (pc_x),
.pc_m (pc_m),
.pc_w (pc_w),
-
-
+
.icache_stall_request (icache_stall_request),
.icache_restart_request (icache_restart_request),
.icache_refill_request (icache_refill_request),
.icache_refilling (icache_refilling),
-
-
+
-
-
-
+
.i_dat_o (I_DAT_O),
.i_adr_o (I_ADR_O),
@@ -40747,22 +37021,16 @@ lm32_instruction_unit_medium_debug #(
.i_cti_o (I_CTI_O),
.i_lock_o (I_LOCK_O),
.i_bte_o (I_BTE_O),
-
-
-
+
.jtag_read_data (jtag_read_data),
.jtag_access_complete (jtag_access_complete),
-
-
+
-
-
-
- .instruction_f (instruction_f),
+ .instruction_f (instruction_f),
.instruction_d (instruction_d)
);
@@ -40775,36 +37043,27 @@ lm32_decoder_medium_debug decoder (
.d_result_sel_0 (d_result_sel_0_d),
.d_result_sel_1 (d_result_sel_1_d),
.x_result_sel_csr (x_result_sel_csr_d),
-
+
-
-
+
-
-
-
- .x_result_sel_sext (x_result_sel_sext_d),
+ .x_result_sel_sext (x_result_sel_sext_d),
.x_result_sel_logic (x_result_sel_logic_d),
-
+
-
.x_result_sel_add (x_result_sel_add_d),
.m_result_sel_compare (m_result_sel_compare_d),
-
-
- .m_result_sel_shift (m_result_sel_shift_d),
+ .m_result_sel_shift (m_result_sel_shift_d),
.w_result_sel_load (w_result_sel_load_d),
-
-
- .w_result_sel_mul (w_result_sel_mul_d),
+ .w_result_sel_mul (w_result_sel_mul_d),
.x_bypass_enable (x_bypass_enable_d),
.m_bypass_enable (m_bypass_enable_d),
@@ -40822,46 +37081,36 @@ lm32_decoder_medium_debug decoder (
.sign_extend (sign_extend_d),
.adder_op (adder_op_d),
.logic_op (logic_op_d),
-
-
- .direction (direction_d),
+ .direction (direction_d),
-
+
-
-
+
-
-
+
-
.branch (branch_d),
.bi_unconditional (bi_unconditional),
.bi_conditional (bi_conditional),
.branch_reg (branch_reg_d),
.condition (condition_d),
-
-
- .break_opcode (break_d),
+ .break_opcode (break_d),
.scall (scall_d),
.eret (eret_d),
-
-
- .bret (bret_d),
+ .bret (bret_d),
-
+
-
.csr_write_enable (csr_write_enable_d)
);
@@ -40895,14 +37144,12 @@ lm32_load_store_unit_medium_debug #(
.store_q_m (store_q_m),
.sign_extend_x (sign_extend_x),
.size_x (size_x),
-
+
-
-
+
-
.d_dat_i (D_DAT_I),
.d_ack_i (D_ACK_I),
@@ -40910,20 +37157,18 @@ lm32_load_store_unit_medium_debug #(
.d_rty_i (D_RTY_I),
-
+
-
-
+
-
.load_data_w (load_data_w),
.stall_wb_load (stall_wb_load),
@@ -40962,8 +37207,7 @@ lm32_logic_op logic_op (
.logic_result_x (logic_result_x)
);
-
-
+
lm32_shifter shifter (
@@ -40977,11 +37221,9 @@ lm32_shifter shifter (
.shifter_result_m (shifter_result_m)
);
-
-
-
+
lm32_multiplier multiplier (
@@ -40994,10 +37236,9 @@ lm32_multiplier multiplier (
.result (multiplier_result_w)
);
-
-
+
@@ -41026,11 +37267,9 @@ lm32_multiplier multiplier (
-
-
-
+
lm32_interrupt_medium_debug interrupt_unit (
@@ -41040,19 +37279,15 @@ lm32_interrupt_medium_debug interrupt_unit (
.interrupt (interrupt),
.stall_x (stall_x),
-
-
+
.non_debug_exception (non_debug_exception_q_w),
.debug_exception (debug_exception_q_w),
-
-
+
.eret_q_x (eret_q_x),
-
-
- .bret_q_x (bret_q_x),
+ .bret_q_x (bret_q_x),
.csr (csr_x),
.csr_write_data (operand_1_x),
@@ -41062,11 +37297,9 @@ lm32_interrupt_medium_debug interrupt_unit (
.csr_read_data (interrupt_csr_read_data_x)
);
-
-
-
+
lm32_jtag_medium_debug jtag (
@@ -41078,35 +37311,26 @@ lm32_jtag_medium_debug jtag (
.jtag_reg_q (jtag_reg_q),
.jtag_reg_addr_q (jtag_reg_addr_q),
-
-
+
.csr (csr_x),
.csr_write_data (operand_1_x),
.csr_write_enable (csr_write_enable_q_x),
.stall_x (stall_x),
-
-
-
+
.jtag_read_data (jtag_read_data),
.jtag_access_complete (jtag_access_complete),
-
-
-
- .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
+ .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
-
-
+
.jtx_csr_read_data (jtx_csr_read_data),
.jrx_csr_read_data (jrx_csr_read_data),
-
-
-
+
.jtag_csr_write_enable (jtag_csr_write_enable),
.jtag_csr_write_data (jtag_csr_write_data),
.jtag_csr (jtag_csr),
@@ -41114,23 +37338,18 @@ lm32_jtag_medium_debug jtag (
.jtag_write_enable (jtag_write_enable),
.jtag_write_data (jtag_write_data),
.jtag_address (jtag_address),
-
-
-
+
.jtag_break (jtag_break),
.jtag_reset (reset_exception),
-
.jtag_reg_d (jtag_reg_d),
.jtag_reg_addr_d (jtag_reg_addr_d)
);
-
-
-
+
lm32_debug_medium_debug #(
.breakpoints (breakpoints),
@@ -41146,43 +37365,34 @@ lm32_debug_medium_debug #(
.csr_write_enable_x (csr_write_enable_q_x),
.csr_write_data (operand_1_x),
.csr_x (csr_x),
-
-
+
.jtag_csr_write_enable (jtag_csr_write_enable),
.jtag_csr_write_data (jtag_csr_write_data),
.jtag_csr (jtag_csr),
-
-
-
+
.eret_q_x (eret_q_x),
.bret_q_x (bret_q_x),
.stall_x (stall_x),
.exception_x (exception_x),
.q_x (q_x),
-
+
-
-
-
-
- .dc_ss (dc_ss),
+ .dc_ss (dc_ss),
.dc_re (dc_re),
.bp_match (bp_match),
.wp_match (wp_match)
);
-
-
-
+
@@ -41243,8 +37453,8 @@ lm32_debug_medium_debug #(
- always @(posedge clk_i )
- if (rst_i == 1'b1)
+ always @(posedge clk_i )
+ if (rst_i == 1'b1)
begin
regfile_raw_0 <= 1'b0;
regfile_raw_1 <= 1'b0;
@@ -41299,10 +37509,9 @@ lm32_debug_medium_debug #(
.rdata_o (regfile_data_1)
);
-
-
+
@@ -41375,58 +37584,53 @@ lm32_debug_medium_debug #(
-
-
-
+
assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
-
-
-
+
-
-assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == 1'b1);
-assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == 1'b1);
-assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == 1'b1);
-assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == 1'b1);
-assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == 1'b1);
-assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == 1'b1);
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == 1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == 1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == 1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == 1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == 1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == 1'b1);
always @(*)
begin
- if ( ( (x_bypass_enable_x == 1'b0)
- && ( ((read_enable_0_d == 1'b1) && (raw_x_0 == 1'b1))
- || ((read_enable_1_d == 1'b1) && (raw_x_1 == 1'b1))
+ if ( ( (x_bypass_enable_x == 1'b0)
+ && ( ((read_enable_0_d == 1'b1) && (raw_x_0 == 1'b1))
+ || ((read_enable_1_d == 1'b1) && (raw_x_1 == 1'b1))
)
)
- || ( (m_bypass_enable_m == 1'b0)
- && ( ((read_enable_0_d == 1'b1) && (raw_m_0 == 1'b1))
- || ((read_enable_1_d == 1'b1) && (raw_m_1 == 1'b1))
+ || ( (m_bypass_enable_m == 1'b0)
+ && ( ((read_enable_0_d == 1'b1) && (raw_m_0 == 1'b1))
+ || ((read_enable_1_d == 1'b1) && (raw_m_1 == 1'b1))
)
)
)
- interlock = 1'b1;
+ interlock = 1'b1;
else
- interlock = 1'b0;
+ interlock = 1'b0;
end
always @(*)
begin
- if (raw_x_0 == 1'b1)
+ if (raw_x_0 == 1'b1)
bypass_data_0 = x_result;
- else if (raw_m_0 == 1'b1)
+ else if (raw_m_0 == 1'b1)
bypass_data_0 = m_result;
- else if (raw_w_0 == 1'b1)
+ else if (raw_w_0 == 1'b1)
bypass_data_0 = w_result;
else
bypass_data_0 = reg_data_0;
@@ -41435,11 +37639,11 @@ end
always @(*)
begin
- if (raw_x_1 == 1'b1)
+ if (raw_x_1 == 1'b1)
bypass_data_1 = x_result;
- else if (raw_m_1 == 1'b1)
+ else if (raw_m_1 == 1'b1)
bypass_data_1 = m_result;
- else if (raw_w_1 == 1'b1)
+ else if (raw_w_1 == 1'b1)
bypass_data_1 = w_result;
else
bypass_data_1 = reg_data_1;
@@ -41467,51 +37671,47 @@ always @(*)
begin
d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
case (d_result_sel_1_d)
- 2'b00: d_result_1 = { 32{1'b0}};
- 2'b01: d_result_1 = bypass_data_1;
- 2'b10: d_result_1 = immediate_d;
- default: d_result_1 = { 32{1'bx}};
+ 2'b00: d_result_1 = {32{1'b0}};
+ 2'b01: d_result_1 = bypass_data_1;
+ 2'b10: d_result_1 = immediate_d;
+ default: d_result_1 = {32{1'bx}};
endcase
end
-
+
-
-
-
+
assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
-assign sext_result_x = size_x == 2'b00 ? sextb_result_x : sexth_result_x;
-
+assign sext_result_x = size_x == 2'b00 ? sextb_result_x : sexth_result_x;
-
+
-
assign cmp_zero = operand_0_x == operand_1_x;
-assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_negative = adder_result_x[32-1];
assign cmp_overflow = adder_overflow_x;
assign cmp_carry_n = adder_carry_n_x;
always @(*)
begin
case (condition_x)
- 3'b000: condition_met_x = 1'b1;
- 3'b110: condition_met_x = 1'b1;
- 3'b001: condition_met_x = cmp_zero;
- 3'b111: condition_met_x = !cmp_zero;
- 3'b010: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
- 3'b101: condition_met_x = cmp_carry_n && !cmp_zero;
- 3'b011: condition_met_x = cmp_negative == cmp_overflow;
- 3'b100: condition_met_x = cmp_carry_n;
+ 3'b000: condition_met_x = 1'b1;
+ 3'b110: condition_met_x = 1'b1;
+ 3'b001: condition_met_x = cmp_zero;
+ 3'b111: condition_met_x = !cmp_zero;
+ 3'b010: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+ 3'b101: condition_met_x = cmp_carry_n && !cmp_zero;
+ 3'b011: condition_met_x = cmp_negative == cmp_overflow;
+ 3'b100: condition_met_x = cmp_carry_n;
default: condition_met_x = 1'bx;
endcase
end
@@ -41521,34 +37721,27 @@ always @(*)
begin
x_result = x_result_sel_add_x ? adder_result_x
: x_result_sel_csr_x ? csr_read_data_x
-
-
- : x_result_sel_sext_x ? sext_result_x
+ : x_result_sel_sext_x ? sext_result_x
-
+
-
-
+
-
-
+
-
: logic_result_x;
end
always @(*)
begin
- m_result = m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
-
-
- : m_result_sel_shift_m ? shifter_result_m
+ m_result = m_result_sel_compare_m ? {{32-1{1'b0}}, condition_met_m}
+ : m_result_sel_shift_m ? shifter_result_m
: operand_m;
end
@@ -41557,15 +37750,13 @@ end
always @(*)
begin
w_result = w_result_sel_load_w ? load_data_w
-
-
- : w_result_sel_mul_w ? multiplier_result_w
+ : w_result_sel_mul_w ? multiplier_result_w
: operand_w;
end
-
+
@@ -41576,179 +37767,148 @@ end
-
-assign branch_taken_m = (stall_m == 1'b0)
- && ( ( (branch_m == 1'b1)
- && (valid_m == 1'b1)
- && ( ( (condition_met_m == 1'b1)
- && (branch_predict_taken_m == 1'b0)
+assign branch_taken_m = (stall_m == 1'b0)
+ && ( ( (branch_m == 1'b1)
+ && (valid_m == 1'b1)
+ && ( ( (condition_met_m == 1'b1)
+ && (branch_predict_taken_m == 1'b0)
)
- || ( (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1)
+ || ( (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1)
)
)
)
- || (exception_m == 1'b1)
+ || (exception_m == 1'b1)
);
-assign branch_mispredict_taken_m = (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1);
+assign branch_mispredict_taken_m = (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1);
-assign branch_flushX_m = (stall_m == 1'b0)
- && ( ( (branch_m == 1'b1)
- && (valid_m == 1'b1)
- && ( (condition_met_m == 1'b1)
- || ( (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1)
+assign branch_flushX_m = (stall_m == 1'b0)
+ && ( ( (branch_m == 1'b1)
+ && (valid_m == 1'b1)
+ && ( (condition_met_m == 1'b1)
+ || ( (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1)
)
)
)
- || (exception_m == 1'b1)
+ || (exception_m == 1'b1)
);
-assign kill_f = ( (valid_d == 1'b1)
- && (branch_predict_taken_d == 1'b1)
+assign kill_f = ( (valid_d == 1'b1)
+ && (branch_predict_taken_d == 1'b1)
)
- || (branch_taken_m == 1'b1)
-
+ || (branch_taken_m == 1'b1)
+
-
-
-
- || (icache_refill_request == 1'b1)
+ || (icache_refill_request == 1'b1)
-
+
-
;
-assign kill_d = (branch_taken_m == 1'b1)
-
+assign kill_d = (branch_taken_m == 1'b1)
+
-
-
-
- || (icache_refill_request == 1'b1)
+ || (icache_refill_request == 1'b1)
-
+
-
;
-assign kill_x = (branch_flushX_m == 1'b1)
-
+assign kill_x = (branch_flushX_m == 1'b1)
+
-
;
-assign kill_m = 1'b0
-
+assign kill_m = 1'b0
+
-
;
-assign kill_w = 1'b0
-
+assign kill_w = 1'b0
+
-
;
-
-
-assign breakpoint_exception = ( ( (break_x == 1'b1)
- || (bp_match == 1'b1)
+
+assign breakpoint_exception = ( ( (break_x == 1'b1)
+ || (bp_match == 1'b1)
)
- && (valid_x == 1'b1)
+ && (valid_x == 1'b1)
)
-
-
- || (jtag_break == 1'b1)
+ || (jtag_break == 1'b1)
;
-
-
-
-assign watchpoint_exception = wp_match == 1'b1;
+assign watchpoint_exception = wp_match == 1'b1;
-
+
-
-
+
-
-assign system_call_exception = ( (scall_x == 1'b1)
-
+assign system_call_exception = ( (scall_x == 1'b1)
+
-
);
-
-
-assign debug_exception_x = (breakpoint_exception == 1'b1)
- || (watchpoint_exception == 1'b1)
+
+assign debug_exception_x = (breakpoint_exception == 1'b1)
+ || (watchpoint_exception == 1'b1)
;
-assign non_debug_exception_x = (system_call_exception == 1'b1)
-
-
- || (reset_exception == 1'b1)
+assign non_debug_exception_x = (system_call_exception == 1'b1)
+ || (reset_exception == 1'b1)
-
+
-
-
+
-
-
-
- || ( (interrupt_exception == 1'b1)
-
-
- && (dc_ss == 1'b0)
+ || ( (interrupt_exception == 1'b1)
+
+ && (dc_ss == 1'b0)
-
+
-
)
-
;
-assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1);
-
+assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1);
+
@@ -41770,32 +37930,26 @@ assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x ==
-
always @(*)
begin
-
-
-
-
- if (reset_exception == 1'b1)
- eid_x = 3'h0;
- else
+
+ if (reset_exception == 1'b1)
+ eid_x = 3'h0;
+ else
-
+
-
- if (breakpoint_exception == 1'b1)
- eid_x = 3'd1;
+ if (breakpoint_exception == 1'b1)
+ eid_x = 3'd1;
else
-
-
+
@@ -41803,89 +37957,77 @@ begin
-
-
-
- if (watchpoint_exception == 1'b1)
- eid_x = 3'd3;
- else
+ if (watchpoint_exception == 1'b1)
+ eid_x = 3'd3;
+ else
-
+
-
-
-
- if ( (interrupt_exception == 1'b1)
-
-
- && (dc_ss == 1'b0)
+ if ( (interrupt_exception == 1'b1)
+
+ && (dc_ss == 1'b0)
)
- eid_x = 3'h6;
+ eid_x = 3'h6;
else
-
- eid_x = 3'h7;
+ eid_x = 3'h7;
end
-assign stall_a = (stall_f == 1'b1);
+assign stall_a = (stall_f == 1'b1);
-assign stall_f = (stall_d == 1'b1);
+assign stall_f = (stall_d == 1'b1);
-assign stall_d = (stall_x == 1'b1)
- || ( (interlock == 1'b1)
- && (kill_d == 1'b0)
+assign stall_d = (stall_x == 1'b1)
+ || ( (interlock == 1'b1)
+ && (kill_d == 1'b0)
)
- || ( ( (eret_d == 1'b1)
- || (scall_d == 1'b1)
-
+ || ( ( (eret_d == 1'b1)
+ || (scall_d == 1'b1)
+
-
)
- && ( (load_q_x == 1'b1)
- || (load_q_m == 1'b1)
- || (store_q_x == 1'b1)
- || (store_q_m == 1'b1)
- || (D_CYC_O == 1'b1)
+ && ( (load_q_x == 1'b1)
+ || (load_q_m == 1'b1)
+ || (store_q_x == 1'b1)
+ || (store_q_m == 1'b1)
+ || (D_CYC_O == 1'b1)
)
- && (kill_d == 1'b0)
+ && (kill_d == 1'b0)
)
-
-
- || ( ( (break_d == 1'b1)
- || (bret_d == 1'b1)
+
+ || ( ( (break_d == 1'b1)
+ || (bret_d == 1'b1)
)
- && ( (load_q_x == 1'b1)
- || (store_q_x == 1'b1)
- || (load_q_m == 1'b1)
- || (store_q_m == 1'b1)
- || (D_CYC_O == 1'b1)
+ && ( (load_q_x == 1'b1)
+ || (store_q_x == 1'b1)
+ || (load_q_m == 1'b1)
+ || (store_q_m == 1'b1)
+ || (D_CYC_O == 1'b1)
)
- && (kill_d == 1'b0)
+ && (kill_d == 1'b0)
)
-
- || ( (csr_write_enable_d == 1'b1)
- && (load_q_x == 1'b1)
+ || ( (csr_write_enable_d == 1'b1)
+ && (load_q_x == 1'b1)
)
;
-assign stall_x = (stall_m == 1'b1)
-
+assign stall_x = (stall_m == 1'b1)
+
-
-
+
@@ -41894,16 +38036,14 @@ assign stall_x = (stall_m == 1'b1)
-
;
-assign stall_m = (stall_wb_load == 1'b1)
-
+assign stall_m = (stall_wb_load == 1'b1)
+
-
- || ( (D_CYC_O == 1'b1)
- && ( (store_m == 1'b1)
+ || ( (D_CYC_O == 1'b1)
+ && ( (store_m == 1'b1)
@@ -41917,234 +38057,182 @@ assign stall_m = (stall_wb_load == 1'b1)
-
-
- || ((store_x == 1'b1) && (interrupt_exception == 1'b1))
+ || ((store_x == 1'b1) && (interrupt_exception == 1'b1))
- || (load_m == 1'b1)
- || (load_x == 1'b1)
+ || (load_m == 1'b1)
+ || (load_x == 1'b1)
)
)
-
-
+
-
-
-
- || (icache_stall_request == 1'b1)
- || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1)))
+ || (icache_stall_request == 1'b1)
+ || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1)))
+
-
-
+
-
;
-
+
-
-
+
-
-
+
-
-
+
-
-assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
-assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
-assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
-
-
-assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1);
+assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
+assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
+assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1);
-assign load_q_x = (load_x == 1'b1)
- && (q_x == 1'b1)
-
-
- && (bp_match == 1'b0)
+assign load_q_x = (load_x == 1'b1)
+ && (q_x == 1'b1)
+ && (bp_match == 1'b0)
;
-assign store_q_x = (store_x == 1'b1)
- && (q_x == 1'b1)
-
-
- && (bp_match == 1'b0)
+assign store_q_x = (store_x == 1'b1)
+ && (q_x == 1'b1)
+ && (bp_match == 1'b0)
;
-
+
-
-assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
-assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
-assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
-
-assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1));
-assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1));
+assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
+assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
+assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
+assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1));
+assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1));
+
-assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
-assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
-assign write_enable_q_w = (write_enable_w == 1'b1) && (valid_w == 1'b1);
+assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
+assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
+assign write_enable_q_w = (write_enable_w == 1'b1) && (valid_w == 1'b1);
-assign reg_write_enable_q_w = (write_enable_w == 1'b1) && (kill_w == 1'b0) && (valid_w == 1'b1);
+assign reg_write_enable_q_w = (write_enable_w == 1'b1) && (kill_w == 1'b0) && (valid_w == 1'b1);
assign cfg = {
- 6'h02,
+ 6'h02,
watchpoints[3:0],
breakpoints[3:0],
interrupts[5:0],
-
-
- 1'b1,
-
-
+ 1'b1,
-
-
- 1'b0,
+
-
+ 1'b0,
- 1'b1,
-
-
+ 1'b1,
-
+
- 1'b1,
+ 1'b1,
+
+
+ 1'b1,
-
+
- 1'b1,
+ 1'b0,
-
+
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
+ 1'b1,
-
-
- 1'b0,
+ 1'b1,
-
-
- 1'b1,
-
-
-
-
- 1'b1,
+ 1'b0,
-
-
-
- 1'b0,
-
+ 1'b1
-
-
- 1'b1
-
-
};
assign cfg2 = {
30'b0,
-
+
+ 1'b0,
- 1'b0,
-
-
-
- 1'b0
-
+ 1'b0
};
-
-
-assign iflush = ( (csr_write_enable_d == 1'b1)
- && (csr_d == 5'h3)
- && (stall_d == 1'b0)
- && (kill_d == 1'b0)
- && (valid_d == 1'b1))
-
-
+
+assign iflush = ( (csr_write_enable_d == 1'b1)
+ && (csr_d == 5'h3)
+ && (stall_d == 1'b0)
+ && (kill_d == 1'b0)
+ && (valid_d == 1'b1))
- ||
- ( (jtag_csr_write_enable == 1'b1)
- && (jtag_csr == 5'h3))
+ ||
+ ( (jtag_csr_write_enable == 1'b1)
+ && (jtag_csr == 5'h3))
;
-
@@ -42154,43 +38242,35 @@ assign iflush = ( (csr_write_enable_d == 1'b1)
-
-assign csr_d = read_idx_0_d[ (5-1):0];
+assign csr_d = read_idx_0_d[(5-1):0];
always @(*)
begin
case (csr_x)
-
-
- 5'h0,
- 5'h1,
- 5'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 5'h0,
+ 5'h1,
+ 5'h2: csr_read_data_x = interrupt_csr_read_data_x;
-
+
-
- 5'h6: csr_read_data_x = cfg;
- 5'h7: csr_read_data_x = {eba, 8'h00};
-
-
- 5'h9: csr_read_data_x = {deba, 8'h00};
+ 5'h6: csr_read_data_x = cfg;
+ 5'h7: csr_read_data_x = {eba, 8'h00};
+ 5'h9: csr_read_data_x = {deba, 8'h00};
-
-
- 5'he: csr_read_data_x = jtx_csr_read_data;
- 5'hf: csr_read_data_x = jrx_csr_read_data;
+ 5'he: csr_read_data_x = jtx_csr_read_data;
+ 5'hf: csr_read_data_x = jrx_csr_read_data;
- 5'ha: csr_read_data_x = cfg2;
+ 5'ha: csr_read_data_x = cfg2;
- default: csr_read_data_x = { 32{1'bx}};
+ default: csr_read_data_x = {32{1'bx}};
endcase
end
@@ -42199,47 +38279,41 @@ end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if (rst_i == 1'b1)
+ eba <= eba_reset[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0))
- eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
-
- if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7))
- eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0))
+ eba <= operand_1_x[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7))
+ eba <= jtag_csr_write_data[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if (rst_i == 1'b1)
+ deba <= deba_reset[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0))
- deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
-
- if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9))
- deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0))
+ deba <= operand_1_x[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9))
+ deba <= jtag_csr_write_data[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
end
end
-
-
+
@@ -42249,8 +38323,7 @@ end
-
-
+
@@ -42267,13 +38340,11 @@ end
-
-
-
-
+
+
@@ -42287,20 +38358,18 @@ end
-
always @(*)
begin
- if (icache_refill_request == 1'b1)
- valid_a = 1'b0;
- else if (icache_restart_request == 1'b1)
- valid_a = 1'b1;
+ if (icache_refill_request == 1'b1)
+ valid_a = 1'b0;
+ else if (icache_restart_request == 1'b1)
+ valid_a = 1'b1;
else
valid_a = !icache_refilling;
end
-
-
+
@@ -42314,253 +38383,208 @@ end
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- valid_f <= 1'b0;
- valid_d <= 1'b0;
- valid_x <= 1'b0;
- valid_m <= 1'b0;
- valid_w <= 1'b0;
+ valid_f <= 1'b0;
+ valid_d <= 1'b0;
+ valid_x <= 1'b0;
+ valid_m <= 1'b0;
+ valid_w <= 1'b0;
end
else
begin
- if ((kill_f == 1'b1) || (stall_a == 1'b0))
-
-
- valid_f <= valid_a;
+ if ((kill_f == 1'b1) || (stall_a == 1'b0))
-
+ valid_f <= valid_a;
+
- else if (stall_f == 1'b0)
- valid_f <= 1'b0;
+ else if (stall_f == 1'b0)
+ valid_f <= 1'b0;
- if (kill_d == 1'b1)
- valid_d <= 1'b0;
- else if (stall_f == 1'b0)
+ if (kill_d == 1'b1)
+ valid_d <= 1'b0;
+ else if (stall_f == 1'b0)
valid_d <= valid_f & !kill_f;
- else if (stall_d == 1'b0)
- valid_d <= 1'b0;
+ else if (stall_d == 1'b0)
+ valid_d <= 1'b0;
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
valid_x <= valid_d & !kill_d;
- else if (kill_x == 1'b1)
- valid_x <= 1'b0;
- else if (stall_x == 1'b0)
- valid_x <= 1'b0;
-
- if (kill_m == 1'b1)
- valid_m <= 1'b0;
- else if (stall_x == 1'b0)
+ else if (kill_x == 1'b1)
+ valid_x <= 1'b0;
+ else if (stall_x == 1'b0)
+ valid_x <= 1'b0;
+
+ if (kill_m == 1'b1)
+ valid_m <= 1'b0;
+ else if (stall_x == 1'b0)
valid_m <= valid_x & !kill_x;
- else if (stall_m == 1'b0)
- valid_m <= 1'b0;
+ else if (stall_m == 1'b0)
+ valid_m <= 1'b0;
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
valid_w <= valid_m & !kill_m;
else
- valid_w <= 1'b0;
+ valid_w <= 1'b0;
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
-
+
-
- operand_0_x <= { 32{1'b0}};
- operand_1_x <= { 32{1'b0}};
- store_operand_x <= { 32{1'b0}};
- branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- x_result_sel_csr_x <= 1'b0;
-
+ operand_0_x <= {32{1'b0}};
+ operand_1_x <= {32{1'b0}};
+ store_operand_x <= {32{1'b0}};
+ branch_target_x <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ x_result_sel_csr_x <= 1'b0;
+
-
-
+
-
-
-
- x_result_sel_sext_x <= 1'b0;
+ x_result_sel_sext_x <= 1'b0;
- x_result_sel_logic_x <= 1'b0;
-
+ x_result_sel_logic_x <= 1'b0;
+
-
- x_result_sel_add_x <= 1'b0;
- m_result_sel_compare_x <= 1'b0;
-
-
- m_result_sel_shift_x <= 1'b0;
+ x_result_sel_add_x <= 1'b0;
+ m_result_sel_compare_x <= 1'b0;
+ m_result_sel_shift_x <= 1'b0;
- w_result_sel_load_x <= 1'b0;
-
-
- w_result_sel_mul_x <= 1'b0;
+ w_result_sel_load_x <= 1'b0;
+ w_result_sel_mul_x <= 1'b0;
- x_bypass_enable_x <= 1'b0;
- m_bypass_enable_x <= 1'b0;
- write_enable_x <= 1'b0;
- write_idx_x <= { 5{1'b0}};
- csr_x <= { 5{1'b0}};
- load_x <= 1'b0;
- store_x <= 1'b0;
- size_x <= { 2{1'b0}};
- sign_extend_x <= 1'b0;
- adder_op_x <= 1'b0;
- adder_op_x_n <= 1'b0;
+ x_bypass_enable_x <= 1'b0;
+ m_bypass_enable_x <= 1'b0;
+ write_enable_x <= 1'b0;
+ write_idx_x <= {5{1'b0}};
+ csr_x <= {5{1'b0}};
+ load_x <= 1'b0;
+ store_x <= 1'b0;
+ size_x <= {2{1'b0}};
+ sign_extend_x <= 1'b0;
+ adder_op_x <= 1'b0;
+ adder_op_x_n <= 1'b0;
logic_op_x <= 4'h0;
-
-
- direction_x <= 1'b0;
+ direction_x <= 1'b0;
-
+
-
- branch_x <= 1'b0;
- branch_predict_x <= 1'b0;
- branch_predict_taken_x <= 1'b0;
- condition_x <= 3'b000;
-
-
- break_x <= 1'b0;
+ branch_x <= 1'b0;
+ branch_predict_x <= 1'b0;
+ branch_predict_taken_x <= 1'b0;
+ condition_x <= 3'b000;
+ break_x <= 1'b0;
- scall_x <= 1'b0;
- eret_x <= 1'b0;
-
-
- bret_x <= 1'b0;
+ scall_x <= 1'b0;
+ eret_x <= 1'b0;
+ bret_x <= 1'b0;
-
+
-
- csr_write_enable_x <= 1'b0;
- operand_m <= { 32{1'b0}};
- branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- m_result_sel_compare_m <= 1'b0;
-
-
- m_result_sel_shift_m <= 1'b0;
+ csr_write_enable_x <= 1'b0;
+ operand_m <= {32{1'b0}};
+ branch_target_m <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ m_result_sel_compare_m <= 1'b0;
+ m_result_sel_shift_m <= 1'b0;
- w_result_sel_load_m <= 1'b0;
-
-
- w_result_sel_mul_m <= 1'b0;
+ w_result_sel_load_m <= 1'b0;
+ w_result_sel_mul_m <= 1'b0;
- m_bypass_enable_m <= 1'b0;
- branch_m <= 1'b0;
- branch_predict_m <= 1'b0;
- branch_predict_taken_m <= 1'b0;
- exception_m <= 1'b0;
- load_m <= 1'b0;
- store_m <= 1'b0;
-
-
- direction_m <= 1'b0;
+ m_bypass_enable_m <= 1'b0;
+ branch_m <= 1'b0;
+ branch_predict_m <= 1'b0;
+ branch_predict_taken_m <= 1'b0;
+ exception_m <= 1'b0;
+ load_m <= 1'b0;
+ store_m <= 1'b0;
+ direction_m <= 1'b0;
- write_enable_m <= 1'b0;
- write_idx_m <= { 5{1'b0}};
- condition_met_m <= 1'b0;
-
+ write_enable_m <= 1'b0;
+ write_idx_m <= {5{1'b0}};
+ condition_met_m <= 1'b0;
+
-
-
-
- debug_exception_m <= 1'b0;
- non_debug_exception_m <= 1'b0;
+ debug_exception_m <= 1'b0;
+ non_debug_exception_m <= 1'b0;
- operand_w <= { 32{1'b0}};
- w_result_sel_load_w <= 1'b0;
-
-
- w_result_sel_mul_w <= 1'b0;
+ operand_w <= {32{1'b0}};
+ w_result_sel_load_w <= 1'b0;
+ w_result_sel_mul_w <= 1'b0;
- write_idx_w <= { 5{1'b0}};
- write_enable_w <= 1'b0;
-
-
- debug_exception_w <= 1'b0;
- non_debug_exception_w <= 1'b0;
+ write_idx_w <= {5{1'b0}};
+ write_enable_w <= 1'b0;
-
-
+ debug_exception_w <= 1'b0;
+ non_debug_exception_w <= 1'b0;
-
+
+
end
else
begin
- if (stall_x == 1'b0)
+ if (stall_x == 1'b0)
begin
-
+
-
operand_0_x <= d_result_0;
operand_1_x <= d_result_1;
store_operand_x <= bypass_data_1;
- branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;
+ branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;
x_result_sel_csr_x <= x_result_sel_csr_d;
-
+
-
-
+
-
-
-
- x_result_sel_sext_x <= x_result_sel_sext_d;
+ x_result_sel_sext_x <= x_result_sel_sext_d;
x_result_sel_logic_x <= x_result_sel_logic_d;
-
+
-
x_result_sel_add_x <= x_result_sel_add_d;
m_result_sel_compare_x <= m_result_sel_compare_d;
-
-
- m_result_sel_shift_x <= m_result_sel_shift_d;
+ m_result_sel_shift_x <= m_result_sel_shift_d;
w_result_sel_load_x <= w_result_sel_load_d;
-
-
- w_result_sel_mul_x <= w_result_sel_mul_d;
+ w_result_sel_mul_x <= w_result_sel_mul_d;
x_bypass_enable_x <= x_bypass_enable_d;
m_bypass_enable_x <= m_bypass_enable_d;
@@ -42576,191 +38600,155 @@ begin
adder_op_x <= adder_op_d;
adder_op_x_n <= ~adder_op_d;
logic_op_x <= logic_op_d;
-
-
- direction_x <= direction_d;
+ direction_x <= direction_d;
-
+
-
condition_x <= condition_d;
csr_write_enable_x <= csr_write_enable_d;
-
-
- break_x <= break_d;
+ break_x <= break_d;
scall_x <= scall_d;
-
+
-
eret_x <= eret_d;
-
-
- bret_x <= bret_d;
+ bret_x <= bret_d;
write_enable_x <= write_enable_d;
end
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
operand_m <= x_result;
m_result_sel_compare_m <= m_result_sel_compare_x;
-
-
- m_result_sel_shift_m <= m_result_sel_shift_x;
+ m_result_sel_shift_m <= m_result_sel_shift_x;
- if (exception_x == 1'b1)
+ if (exception_x == 1'b1)
begin
- w_result_sel_load_m <= 1'b0;
-
-
- w_result_sel_mul_m <= 1'b0;
+ w_result_sel_load_m <= 1'b0;
+ w_result_sel_mul_m <= 1'b0;
end
else
begin
w_result_sel_load_m <= w_result_sel_load_x;
-
-
- w_result_sel_mul_m <= w_result_sel_mul_x;
+ w_result_sel_mul_m <= w_result_sel_mul_x;
end
m_bypass_enable_m <= m_bypass_enable_x;
-
-
- direction_m <= direction_x;
+ direction_m <= direction_x;
load_m <= load_x;
store_m <= store_x;
-
+
-
branch_m <= branch_x;
branch_predict_m <= branch_predict_x;
branch_predict_taken_m <= branch_predict_taken_x;
-
-
-
+
- if (non_debug_exception_x == 1'b1)
- write_idx_m <= 5'd30;
- else if (debug_exception_x == 1'b1)
- write_idx_m <= 5'd31;
+ if (non_debug_exception_x == 1'b1)
+ write_idx_m <= 5'd30;
+ else if (debug_exception_x == 1'b1)
+ write_idx_m <= 5'd31;
else
write_idx_m <= write_idx_x;
-
+
-
condition_met_m <= condition_met_x;
-
-
- if (exception_x == 1'b1)
- if ((dc_re == 1'b1)
- || ((debug_exception_x == 1'b1)
- && (non_debug_exception_x == 1'b0)))
+
+ if (exception_x == 1'b1)
+ if ((dc_re == 1'b1)
+ || ((debug_exception_x == 1'b1)
+ && (non_debug_exception_x == 1'b0)))
branch_target_m <= {deba, eid_x, {3{1'b0}}};
else
branch_target_m <= {eba, eid_x, {3{1'b0}}};
else
branch_target_m <= branch_target_x;
-
-
+
-
+
-
-
+
-
eret_m <= eret_q_x;
-
-
- bret_m <= bret_q_x;
+ bret_m <= bret_q_x;
- write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
-
-
+ write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
+
debug_exception_m <= debug_exception_x;
non_debug_exception_m <= non_debug_exception_x;
-
end
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
- if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
- exception_m <= 1'b1;
+ if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
+ exception_m <= 1'b1;
else
- exception_m <= 1'b0;
-
+ exception_m <= 1'b0;
+
-
end
-
+
-
- operand_w <= exception_m == 1'b1 ? {pc_m, 2'b00} : m_result;
-
+ operand_w <= exception_m == 1'b1 ? {pc_m, 2'b00} : m_result;
w_result_sel_load_w <= w_result_sel_load_m;
-
-
- w_result_sel_mul_w <= w_result_sel_mul_m;
+ w_result_sel_mul_w <= w_result_sel_mul_m;
write_idx_w <= write_idx_m;
-
+
-
write_enable_w <= write_enable_m;
-
-
+
debug_exception_w <= debug_exception_m;
non_debug_exception_w <= non_debug_exception_m;
-
-
+
-
+
@@ -42768,33 +38756,31 @@ begin
-
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- use_buf <= 1'b0;
- reg_data_buf_0 <= { 32{1'b0}};
- reg_data_buf_1 <= { 32{1'b0}};
+ use_buf <= 1'b0;
+ reg_data_buf_0 <= {32{1'b0}};
+ reg_data_buf_1 <= {32{1'b0}};
end
else
begin
- if (stall_d == 1'b0)
- use_buf <= 1'b0;
- else if (use_buf == 1'b0)
+ if (stall_d == 1'b0)
+ use_buf <= 1'b0;
+ else if (use_buf == 1'b0)
begin
reg_data_buf_0 <= reg_data_live_0;
reg_data_buf_1 <= reg_data_live_1;
- use_buf <= 1'b1;
+ use_buf <= 1'b1;
end
- if (reg_write_enable_q_w == 1'b1)
+ if (reg_write_enable_q_w == 1'b1)
begin
if (write_idx_w == read_idx_0_d)
reg_data_buf_0 <= w_result;
@@ -42803,13 +38789,11 @@ begin
end
end
end
-
-
-
+
@@ -42853,8 +38837,7 @@ end
-
-
+
@@ -42913,7 +38896,6 @@ end
-
@@ -42926,13 +38908,9 @@ end
initial
begin
-
-
- reg_0.ram[0] = { 32{1'b0}};
- reg_1.ram[0] = { 32{1'b0}};
-
+
end
@@ -42980,10 +38958,7 @@ endmodule
-
-
-
-
+
@@ -43013,9 +38988,9 @@ endmodule
-
+
@@ -43300,8 +39275,6 @@ endmodule
-
-
@@ -43328,14 +39301,12 @@ module lm32_load_store_unit_medium_debug (
store_q_m,
sign_extend_x,
size_x,
-
+
-
-
+
-
d_dat_i,
d_ack_i,
@@ -43343,19 +39314,17 @@ module lm32_load_store_unit_medium_debug (
d_rty_i,
-
+
-
-
+
-
load_data_w,
stall_wb_load,
@@ -43400,9 +39369,9 @@ input kill_x;
input kill_m;
input exception_m;
-input [ (32-1):0] store_operand_x;
-input [ (32-1):0] load_store_address_x;
-input [ (32-1):0] load_store_address_m;
+input [(32-1):0] store_operand_x;
+input [(32-1):0] load_store_address_x;
+input [(32-1):0] load_store_address_m;
input [1:0] load_store_address_w;
input load_x;
input store_x;
@@ -43411,19 +39380,17 @@ input store_q_x;
input load_q_m;
input store_q_m;
input sign_extend_x;
-input [ 1:0] size_x;
+input [1:0] size_x;
-
+
-
-
+
-
-input [ (32-1):0] d_dat_i;
+input [(32-1):0] d_dat_i;
input d_ack_i;
input d_err_i;
input d_rty_i;
@@ -43432,7 +39399,7 @@ input d_rty_i;
-
+
@@ -43443,8 +39410,7 @@ input d_rty_i;
-
-
+
@@ -43453,50 +39419,49 @@ input d_rty_i;
-
-output [ (32-1):0] load_data_w;
-reg [ (32-1):0] load_data_w;
+output [(32-1):0] load_data_w;
+reg [(32-1):0] load_data_w;
output stall_wb_load;
reg stall_wb_load;
-output [ (32-1):0] d_dat_o;
-reg [ (32-1):0] d_dat_o;
-output [ (32-1):0] d_adr_o;
-reg [ (32-1):0] d_adr_o;
+output [(32-1):0] d_dat_o;
+reg [(32-1):0] d_dat_o;
+output [(32-1):0] d_adr_o;
+reg [(32-1):0] d_adr_o;
output d_cyc_o;
reg d_cyc_o;
-output [ (4-1):0] d_sel_o;
-reg [ (4-1):0] d_sel_o;
+output [(4-1):0] d_sel_o;
+reg [(4-1):0] d_sel_o;
output d_stb_o;
reg d_stb_o;
output d_we_o;
reg d_we_o;
-output [ (3-1):0] d_cti_o;
-reg [ (3-1):0] d_cti_o;
+output [(3-1):0] d_cti_o;
+reg [(3-1):0] d_cti_o;
output d_lock_o;
reg d_lock_o;
-output [ (2-1):0] d_bte_o;
-wire [ (2-1):0] d_bte_o;
+output [(2-1):0] d_bte_o;
+wire [(2-1):0] d_bte_o;
-reg [ 1:0] size_m;
-reg [ 1:0] size_w;
+reg [1:0] size_m;
+reg [1:0] size_w;
reg sign_extend_m;
reg sign_extend_w;
-reg [ (32-1):0] store_data_x;
-reg [ (32-1):0] store_data_m;
-reg [ (4-1):0] byte_enable_x;
-reg [ (4-1):0] byte_enable_m;
-wire [ (32-1):0] data_m;
-reg [ (32-1):0] data_w;
+reg [(32-1):0] store_data_x;
+reg [(32-1):0] store_data_m;
+reg [(4-1):0] byte_enable_x;
+reg [(4-1):0] byte_enable_m;
+wire [(32-1):0] data_m;
+reg [(32-1):0] data_w;
-
+
@@ -43507,8 +39472,7 @@ reg [ (32-1):0] data_w;
-
-
+
@@ -43516,25 +39480,21 @@ reg [ (32-1):0] data_w;
-
wire wb_select_x;
-
+
-
reg wb_select_m;
-reg [ (32-1):0] wb_data_m;
+reg [(32-1):0] wb_data_m;
reg wb_load_complete;
-
-
-
+
@@ -43589,8 +39549,7 @@ endfunction
-
-
+
@@ -43674,8 +39633,7 @@ endfunction
-
-
+
@@ -43714,20 +39672,17 @@ endfunction
-
-
+
-
-
+
-
-
+
@@ -43737,32 +39692,28 @@ endfunction
-
- assign wb_select_x = 1'b1
-
+ assign wb_select_x = 1'b1
+
-
-
+
-
-
+
-
;
always @(*)
begin
case (size_x)
- 2'b00: store_data_x = {4{store_operand_x[7:0]}};
- 2'b11: store_data_x = {2{store_operand_x[15:0]}};
- 2'b10: store_data_x = store_operand_x;
- default: store_data_x = { 32{1'bx}};
+ 2'b00: store_data_x = {4{store_operand_x[7:0]}};
+ 2'b11: store_data_x = {2{store_operand_x[15:0]}};
+ 2'b10: store_data_x = store_operand_x;
+ default: store_data_x = {32{1'bx}};
endcase
end
@@ -43770,18 +39721,18 @@ end
always @(*)
begin
casez ({size_x, load_store_address_x[1:0]})
- { 2'b00, 2'b11}: byte_enable_x = 4'b0001;
- { 2'b00, 2'b10}: byte_enable_x = 4'b0010;
- { 2'b00, 2'b01}: byte_enable_x = 4'b0100;
- { 2'b00, 2'b00}: byte_enable_x = 4'b1000;
- { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
- { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
- { 2'b10, 2'b??}: byte_enable_x = 4'b1111;
+ {2'b00, 2'b11}: byte_enable_x = 4'b0001;
+ {2'b00, 2'b10}: byte_enable_x = 4'b0010;
+ {2'b00, 2'b01}: byte_enable_x = 4'b0100;
+ {2'b00, 2'b00}: byte_enable_x = 4'b1000;
+ {2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+ {2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+ {2'b10, 2'b??}: byte_enable_x = 4'b1111;
default: byte_enable_x = 4'bxxxx;
endcase
end
-
+
@@ -43789,8 +39740,7 @@ end
-
-
+
@@ -43798,8 +39748,7 @@ end
-
-
+
@@ -43819,9 +39768,8 @@ end
-
-
+
@@ -43856,8 +39804,7 @@ end
-
-
+
@@ -43872,20 +39819,15 @@ end
-
-
+
-
assign data_m = wb_data_m;
-
-
-
@@ -43893,21 +39835,21 @@ end
always @(*)
begin
casez ({size_w, load_store_address_w[1:0]})
- { 2'b00, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
- { 2'b00, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
- { 2'b00, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
- { 2'b00, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
- { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
- { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
- { 2'b10, 2'b??}: load_data_w = data_w;
- default: load_data_w = { 32{1'bx}};
+ {2'b00, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+ {2'b00, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+ {2'b00, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+ {2'b00, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+ {2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+ {2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+ {2'b10, 2'b??}: load_data_w = data_w;
+ default: load_data_w = {32{1'bx}};
endcase
end
-assign d_bte_o = 2'b00;
+assign d_bte_o = 2'b00;
-
+
@@ -43941,74 +39883,69 @@ assign d_bte_o = 2'b00;
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- d_cyc_o <= 1'b0;
- d_stb_o <= 1'b0;
- d_dat_o <= { 32{1'b0}};
- d_adr_o <= { 32{1'b0}};
- d_sel_o <= { 4{ 1'b0}};
- d_we_o <= 1'b0;
- d_cti_o <= 3'b111;
- d_lock_o <= 1'b0;
- wb_data_m <= { 32{1'b0}};
- wb_load_complete <= 1'b0;
- stall_wb_load <= 1'b0;
-
+ d_cyc_o <= 1'b0;
+ d_stb_o <= 1'b0;
+ d_dat_o <= {32{1'b0}};
+ d_adr_o <= {32{1'b0}};
+ d_sel_o <= {4{1'b0}};
+ d_we_o <= 1'b0;
+ d_cti_o <= 3'b111;
+ d_lock_o <= 1'b0;
+ wb_data_m <= {32{1'b0}};
+ wb_load_complete <= 1'b0;
+ stall_wb_load <= 1'b0;
+
-
end
else
begin
-
+
-
- if (d_cyc_o == 1'b1)
+ if (d_cyc_o == 1'b1)
begin
- if ((d_ack_i == 1'b1) || (d_err_i == 1'b1))
+ if ((d_ack_i == 1'b1) || (d_err_i == 1'b1))
begin
-
+
-
begin
- d_cyc_o <= 1'b0;
- d_stb_o <= 1'b0;
- d_lock_o <= 1'b0;
+ d_cyc_o <= 1'b0;
+ d_stb_o <= 1'b0;
+ d_lock_o <= 1'b0;
end
-
+
-
wb_data_m <= d_dat_i;
wb_load_complete <= !d_we_o;
end
- if (d_err_i == 1'b1)
+ if (d_err_i == 1'b1)
$display ("Data bus error. Address: %x", d_adr_o);
end
else
begin
-
+
@@ -44021,115 +39958,106 @@ begin
-
- if ( (store_q_m == 1'b1)
- && (stall_m == 1'b0)
-
+ if ( (store_q_m == 1'b1)
+ && (stall_m == 1'b0)
+
-
-
+
-
)
begin
d_dat_o <= store_data_m;
d_adr_o <= load_store_address_m;
- d_cyc_o <= 1'b1;
+ d_cyc_o <= 1'b1;
d_sel_o <= byte_enable_m;
- d_stb_o <= 1'b1;
- d_we_o <= 1'b1;
- d_cti_o <= 3'b111;
+ d_stb_o <= 1'b1;
+ d_we_o <= 1'b1;
+ d_cti_o <= 3'b111;
end
- else if ( (load_q_m == 1'b1)
- && (wb_select_m == 1'b1)
- && (wb_load_complete == 1'b0)
+ else if ( (load_q_m == 1'b1)
+ && (wb_select_m == 1'b1)
+ && (wb_load_complete == 1'b0)
)
begin
- stall_wb_load <= 1'b0;
+ stall_wb_load <= 1'b0;
d_adr_o <= load_store_address_m;
- d_cyc_o <= 1'b1;
+ d_cyc_o <= 1'b1;
d_sel_o <= byte_enable_m;
- d_stb_o <= 1'b1;
- d_we_o <= 1'b0;
- d_cti_o <= 3'b111;
+ d_stb_o <= 1'b1;
+ d_we_o <= 1'b0;
+ d_cti_o <= 3'b111;
end
end
- if (stall_m == 1'b0)
- wb_load_complete <= 1'b0;
+ if (stall_m == 1'b0)
+ wb_load_complete <= 1'b0;
- if ((load_q_x == 1'b1) && (wb_select_x == 1'b1) && (stall_x == 1'b0))
- stall_wb_load <= 1'b1;
+ if ((load_q_x == 1'b1) && (wb_select_x == 1'b1) && (stall_x == 1'b0))
+ stall_wb_load <= 1'b1;
- if ((kill_m == 1'b1) || (exception_m == 1'b1))
- stall_wb_load <= 1'b0;
+ if ((kill_m == 1'b1) || (exception_m == 1'b1))
+ stall_wb_load <= 1'b0;
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- sign_extend_m <= 1'b0;
+ sign_extend_m <= 1'b0;
size_m <= 2'b00;
- byte_enable_m <= 1'b0;
- store_data_m <= { 32{1'b0}};
-
+ byte_enable_m <= 1'b0;
+ store_data_m <= {32{1'b0}};
+
-
-
+
-
-
+
-
- wb_select_m <= 1'b0;
+ wb_select_m <= 1'b0;
end
else
begin
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
sign_extend_m <= sign_extend_x;
size_m <= size_x;
byte_enable_m <= byte_enable_x;
store_data_m <= store_data_x;
-
+
-
-
+
-
-
+
-
wb_select_m <= wb_select_x;
end
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
size_w <= 2'b00;
- data_w <= { 32{1'b0}};
- sign_extend_w <= 1'b0;
+ data_w <= {32{1'b0}};
+ sign_extend_w <= 1'b0;
end
else
begin
@@ -44148,11 +40076,11 @@ end
always @(posedge clk_i)
begin
- if (((load_q_m == 1'b1) || (store_q_m == 1'b1)) && (stall_m == 1'b0))
+ if (((load_q_m == 1'b1) || (store_q_m == 1'b1)) && (stall_m == 1'b0))
begin
- if ((size_m === 2'b11) && (load_store_address_m[0] !== 1'b0))
+ if ((size_m === 2'b11) && (load_store_address_m[0] !== 1'b0))
$display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
- if ((size_m === 2'b10) && (load_store_address_m[1:0] !== 2'b00))
+ if ((size_m === 2'b10) && (load_store_address_m[1:0] !== 2'b00))
$display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
end
end
@@ -44194,9 +40122,7 @@ endmodule
-
-
-
+
@@ -44227,9 +40153,8 @@ endmodule
-
-
+
@@ -44514,104 +40439,55 @@ endmodule
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -44624,36 +40500,27 @@ module lm32_decoder_medium_debug (
d_result_sel_0,
d_result_sel_1,
x_result_sel_csr,
-
+
-
-
+
-
-
-
- x_result_sel_sext,
+ x_result_sel_sext,
x_result_sel_logic,
-
+
-
x_result_sel_add,
m_result_sel_compare,
-
-
- m_result_sel_shift,
+ m_result_sel_shift,
w_result_sel_load,
-
-
- w_result_sel_mul,
+ w_result_sel_mul,
x_bypass_enable,
m_bypass_enable,
@@ -44671,46 +40538,36 @@ module lm32_decoder_medium_debug (
sign_extend,
adder_op,
logic_op,
-
-
- direction,
+ direction,
-
+
-
-
+
-
-
+
-
branch,
branch_reg,
condition,
bi_conditional,
bi_unconditional,
-
-
- break_opcode,
+ break_opcode,
scall,
eret,
-
-
- bret,
+ bret,
-
+
-
csr_write_enable
);
@@ -44718,58 +40575,49 @@ module lm32_decoder_medium_debug (
-input [ (32-1):0] instruction;
+input [(32-1):0] instruction;
-output [ 0:0] d_result_sel_0;
-reg [ 0:0] d_result_sel_0;
-output [ 1:0] d_result_sel_1;
-reg [ 1:0] d_result_sel_1;
+output [0:0] d_result_sel_0;
+reg [0:0] d_result_sel_0;
+output [1:0] d_result_sel_1;
+reg [1:0] d_result_sel_1;
output x_result_sel_csr;
reg x_result_sel_csr;
-
+
-
-
+
-
-
-
+
output x_result_sel_sext;
reg x_result_sel_sext;
-
output x_result_sel_logic;
reg x_result_sel_logic;
-
+
-
output x_result_sel_add;
reg x_result_sel_add;
output m_result_sel_compare;
reg m_result_sel_compare;
-
-
+
output m_result_sel_shift;
reg m_result_sel_shift;
-
output w_result_sel_load;
reg w_result_sel_load;
-
-
+
output w_result_sel_mul;
reg w_result_sel_mul;
-
output x_bypass_enable;
wire x_bypass_enable;
@@ -44777,88 +40625,78 @@ output m_bypass_enable;
wire m_bypass_enable;
output read_enable_0;
wire read_enable_0;
-output [ (5-1):0] read_idx_0;
-wire [ (5-1):0] read_idx_0;
+output [(5-1):0] read_idx_0;
+wire [(5-1):0] read_idx_0;
output read_enable_1;
wire read_enable_1;
-output [ (5-1):0] read_idx_1;
-wire [ (5-1):0] read_idx_1;
+output [(5-1):0] read_idx_1;
+wire [(5-1):0] read_idx_1;
output write_enable;
wire write_enable;
-output [ (5-1):0] write_idx;
-wire [ (5-1):0] write_idx;
-output [ (32-1):0] immediate;
-wire [ (32-1):0] immediate;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output [(5-1):0] write_idx;
+wire [(5-1):0] write_idx;
+output [(32-1):0] immediate;
+wire [(32-1):0] immediate;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
output load;
wire load;
output store;
wire store;
-output [ 1:0] size;
-wire [ 1:0] size;
+output [1:0] size;
+wire [1:0] size;
output sign_extend;
wire sign_extend;
output adder_op;
wire adder_op;
-output [ 3:0] logic_op;
-wire [ 3:0] logic_op;
-
-
+output [3:0] logic_op;
+wire [3:0] logic_op;
+
output direction;
wire direction;
-
-
+
-
-
+
-
-
+
-
output branch;
wire branch;
output branch_reg;
wire branch_reg;
-output [ (3-1):0] condition;
-wire [ (3-1):0] condition;
+output [(3-1):0] condition;
+wire [(3-1):0] condition;
output bi_conditional;
wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
-
-
+
output break_opcode;
wire break_opcode;
-
output scall;
wire scall;
output eret;
wire eret;
-
-
+
output bret;
wire bret;
-
-
+
-
output csr_write_enable;
wire csr_write_enable;
@@ -44866,10 +40704,10 @@ wire csr_write_enable;
-wire [ (32-1):0] extended_immediate;
-wire [ (32-1):0] high_immediate;
-wire [ (32-1):0] call_immediate;
-wire [ (32-1):0] branch_immediate;
+wire [(32-1):0] extended_immediate;
+wire [(32-1):0] high_immediate;
+wire [(32-1):0] call_immediate;
+wire [(32-1):0] branch_immediate;
wire sign_extend_immediate;
wire select_high_immediate;
wire select_call_immediate;
@@ -44878,9 +40716,7 @@ wire select_call_immediate;
-
-
-
+
@@ -44936,70 +40772,61 @@ endfunction
-
-assign op_add = instruction[ 30:26] == 5'b01101;
-assign op_and = instruction[ 30:26] == 5'b01000;
-assign op_andhi = instruction[ 31:26] == 6'b011000;
-assign op_b = instruction[ 31:26] == 6'b110000;
-assign op_bi = instruction[ 31:26] == 6'b111000;
-assign op_be = instruction[ 31:26] == 6'b010001;
-assign op_bg = instruction[ 31:26] == 6'b010010;
-assign op_bge = instruction[ 31:26] == 6'b010011;
-assign op_bgeu = instruction[ 31:26] == 6'b010100;
-assign op_bgu = instruction[ 31:26] == 6'b010101;
-assign op_bne = instruction[ 31:26] == 6'b010111;
-assign op_call = instruction[ 31:26] == 6'b110110;
-assign op_calli = instruction[ 31:26] == 6'b111110;
-assign op_cmpe = instruction[ 30:26] == 5'b11001;
-assign op_cmpg = instruction[ 30:26] == 5'b11010;
-assign op_cmpge = instruction[ 30:26] == 5'b11011;
-assign op_cmpgeu = instruction[ 30:26] == 5'b11100;
-assign op_cmpgu = instruction[ 30:26] == 5'b11101;
-assign op_cmpne = instruction[ 30:26] == 5'b11111;
-
+assign op_add = instruction[30:26] == 5'b01101;
+assign op_and = instruction[30:26] == 5'b01000;
+assign op_andhi = instruction[31:26] == 6'b011000;
+assign op_b = instruction[31:26] == 6'b110000;
+assign op_bi = instruction[31:26] == 6'b111000;
+assign op_be = instruction[31:26] == 6'b010001;
+assign op_bg = instruction[31:26] == 6'b010010;
+assign op_bge = instruction[31:26] == 6'b010011;
+assign op_bgeu = instruction[31:26] == 6'b010100;
+assign op_bgu = instruction[31:26] == 6'b010101;
+assign op_bne = instruction[31:26] == 6'b010111;
+assign op_call = instruction[31:26] == 6'b110110;
+assign op_calli = instruction[31:26] == 6'b111110;
+assign op_cmpe = instruction[30:26] == 5'b11001;
+assign op_cmpg = instruction[30:26] == 5'b11010;
+assign op_cmpge = instruction[30:26] == 5'b11011;
+assign op_cmpgeu = instruction[30:26] == 5'b11100;
+assign op_cmpgu = instruction[30:26] == 5'b11101;
+assign op_cmpne = instruction[30:26] == 5'b11111;
+
-
-assign op_lb = instruction[ 31:26] == 6'b000100;
-assign op_lbu = instruction[ 31:26] == 6'b010000;
-assign op_lh = instruction[ 31:26] == 6'b000111;
-assign op_lhu = instruction[ 31:26] == 6'b001011;
-assign op_lw = instruction[ 31:26] == 6'b001010;
-
+assign op_lb = instruction[31:26] == 6'b000100;
+assign op_lbu = instruction[31:26] == 6'b010000;
+assign op_lh = instruction[31:26] == 6'b000111;
+assign op_lhu = instruction[31:26] == 6'b001011;
+assign op_lw = instruction[31:26] == 6'b001010;
+
-
-
-
-assign op_mul = instruction[ 30:26] == 5'b00010;
+assign op_mul = instruction[30:26] == 5'b00010;
-assign op_nor = instruction[ 30:26] == 5'b00001;
-assign op_or = instruction[ 30:26] == 5'b01110;
-assign op_orhi = instruction[ 31:26] == 6'b011110;
-assign op_raise = instruction[ 31:26] == 6'b101011;
-assign op_rcsr = instruction[ 31:26] == 6'b100100;
-assign op_sb = instruction[ 31:26] == 6'b001100;
-
-
-assign op_sextb = instruction[ 31:26] == 6'b101100;
-assign op_sexth = instruction[ 31:26] == 6'b110111;
+assign op_nor = instruction[30:26] == 5'b00001;
+assign op_or = instruction[30:26] == 5'b01110;
+assign op_orhi = instruction[31:26] == 6'b011110;
+assign op_raise = instruction[31:26] == 6'b101011;
+assign op_rcsr = instruction[31:26] == 6'b100100;
+assign op_sb = instruction[31:26] == 6'b001100;
+assign op_sextb = instruction[31:26] == 6'b101100;
+assign op_sexth = instruction[31:26] == 6'b110111;
-assign op_sh = instruction[ 31:26] == 6'b000011;
-
-
-assign op_sl = instruction[ 30:26] == 5'b01111;
+assign op_sh = instruction[31:26] == 6'b000011;
+assign op_sl = instruction[30:26] == 5'b01111;
-assign op_sr = instruction[ 30:26] == 5'b00101;
-assign op_sru = instruction[ 30:26] == 5'b00000;
-assign op_sub = instruction[ 31:26] == 6'b110010;
-assign op_sw = instruction[ 31:26] == 6'b010110;
-assign op_user = instruction[ 31:26] == 6'b110011;
-assign op_wcsr = instruction[ 31:26] == 6'b110100;
-assign op_xnor = instruction[ 30:26] == 5'b01001;
-assign op_xor = instruction[ 30:26] == 5'b00110;
+assign op_sr = instruction[30:26] == 5'b00101;
+assign op_sru = instruction[30:26] == 5'b00000;
+assign op_sub = instruction[31:26] == 6'b110010;
+assign op_sw = instruction[31:26] == 6'b010110;
+assign op_user = instruction[31:26] == 6'b110011;
+assign op_wcsr = instruction[31:26] == 6'b110100;
+assign op_xnor = instruction[30:26] == 5'b01001;
+assign op_xor = instruction[30:26] == 5'b00110;
assign arith = op_add | op_sub;
@@ -45009,35 +40836,26 @@ assign bi_conditional = op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne;
assign bi_unconditional = op_bi;
assign bra = op_b | bi_unconditional | bi_conditional;
assign call = op_call | op_calli;
-
-
-assign shift = op_sl | op_sr | op_sru;
+assign shift = op_sl | op_sr | op_sru;
-
+
-
-
+
-
-
-
-assign sext = op_sextb | op_sexth;
+assign sext = op_sextb | op_sexth;
-
-
-assign multiply = op_mul;
+assign multiply = op_mul;
-
+
-
assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
assign store = op_sb | op_sh | op_sw;
@@ -45046,39 +40864,34 @@ always @(*)
begin
if (call)
- d_result_sel_0 = 1'b1;
+ d_result_sel_0 = 1'b1;
else
- d_result_sel_0 = 1'b0;
+ d_result_sel_0 = 1'b0;
if (call)
- d_result_sel_1 = 2'b00;
+ d_result_sel_1 = 2'b00;
else if ((instruction[31] == 1'b0) && !bra)
- d_result_sel_1 = 2'b10;
+ d_result_sel_1 = 2'b10;
else
- d_result_sel_1 = 2'b01;
+ d_result_sel_1 = 2'b01;
- x_result_sel_csr = 1'b0;
-
+ x_result_sel_csr = 1'b0;
+
-
-
+
-
-
-
- x_result_sel_sext = 1'b0;
+ x_result_sel_sext = 1'b0;
- x_result_sel_logic = 1'b0;
-
+ x_result_sel_logic = 1'b0;
+
-
- x_result_sel_add = 1'b0;
+ x_result_sel_add = 1'b0;
if (op_rcsr)
- x_result_sel_csr = 1'b1;
-
+ x_result_sel_csr = 1'b1;
+
@@ -45092,84 +40905,66 @@ begin
-
-
+
-
-
-
- else if (sext)
- x_result_sel_sext = 1'b1;
+ else if (sext)
+ x_result_sel_sext = 1'b1;
else if (logical)
- x_result_sel_logic = 1'b1;
-
+ x_result_sel_logic = 1'b1;
+
-
else
- x_result_sel_add = 1'b1;
+ x_result_sel_add = 1'b1;
m_result_sel_compare = cmp;
-
-
- m_result_sel_shift = shift;
+ m_result_sel_shift = shift;
w_result_sel_load = load;
-
-
- w_result_sel_mul = op_mul;
+ w_result_sel_mul = op_mul;
end
assign x_bypass_enable = arith
| logical
-
+
-
-
+
-
-
+
-
-
+
-
-
-
- | sext
+ | sext
-
+
-
| op_rcsr
;
assign m_bypass_enable = x_bypass_enable
-
-
- | shift
+ | shift
| cmp
;
@@ -45195,34 +40990,27 @@ assign sign_extend = instruction[28];
assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
assign logic_op = instruction[29:26];
-
-
+
assign direction = instruction[29];
-
assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
-
-
-assign break_opcode = op_raise & ~instruction[2];
+assign break_opcode = op_raise & ~instruction[2];
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
-
-
-assign bret = op_b & (instruction[25:21] == 5'd31);
+assign bret = op_b & (instruction[25:21] == 5'd31);
-
+
-
assign csr_write_enable = op_wcsr;
@@ -45236,11 +41024,11 @@ assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, inst
assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
-assign immediate = select_high_immediate == 1'b1
+assign immediate = select_high_immediate == 1'b1
? high_immediate
: extended_immediate;
-assign branch_offset = select_call_immediate == 1'b1
+assign branch_offset = select_call_immediate == 1'b1
? call_immediate
: branch_immediate;
@@ -45281,10 +41069,7 @@ endmodule
-
-
-
-
+
@@ -45314,9 +41099,9 @@ endmodule
-
+
@@ -45600,48 +41385,28 @@ endmodule
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
-
+
+
+
+
+
+
+
+
+
@@ -45659,10 +41424,9 @@ module lm32_icache_medium_debug (
refill_ready,
refill_data,
iflush,
-
+
-
valid_d,
branch_predict_taken_d,
@@ -45691,7 +41455,7 @@ localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
localparam addr_set_lsb = (addr_offset_msb+1);
localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
localparam addr_tag_lsb = (addr_set_msb+1);
-localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_msb = clogb2(32'h7fffffff-32'h0)-1;
localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
@@ -45707,18 +41471,17 @@ input stall_f;
input valid_d;
input branch_predict_taken_d;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;
input read_enable_f;
input refill_ready;
-input [ (32-1):0] refill_data;
+input [(32-1):0] refill_data;
input iflush;
-
+
-
@@ -45730,12 +41493,12 @@ output restart_request;
reg restart_request;
output refill_request;
wire refill_request;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
output refilling;
reg refilling;
-output [ (32-1):0] inst;
-wire [ (32-1):0] inst;
+output [(32-1):0] inst;
+wire [(32-1):0] inst;
@@ -45743,27 +41506,27 @@ wire [ (32-1):0] inst;
wire enable;
wire [0:associativity-1] way_mem_we;
-wire [ (32-1):0] way_data[0:associativity-1];
-wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [(32-1):0] way_data[0:associativity-1];
+wire [((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
wire [0:associativity-1] way_valid;
wire [0:associativity-1] way_match;
wire miss;
-wire [ (addr_set_width-1):0] tmem_read_address;
-wire [ (addr_set_width-1):0] tmem_write_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
-wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+wire [(addr_set_width-1):0] tmem_read_address;
+wire [(addr_set_width-1):0] tmem_write_address;
+wire [((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [((addr_tag_width+1)-1):0] tmem_write_data;
-reg [ 3:0] state;
+reg [3:0] state;
wire flushing;
wire check;
wire refill;
reg [associativity-1:0] refill_way_select;
-reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+reg [addr_offset_msb:addr_offset_lsb] refill_offset;
wire last_refill;
-reg [ (addr_set_width-1):0] flush_set;
+reg [(addr_set_width-1):0] flush_set;
genvar i;
@@ -45771,9 +41534,7 @@ genvar i;
-
-
-
+
@@ -45828,7 +41589,6 @@ endfunction
-
generate
for (i = 0; i < associativity; i = i + 1)
begin : memories
@@ -45837,7 +41597,7 @@ endfunction
#(
.data_width (32),
- .address_width ( (addr_offset_width+addr_set_width))
+ .address_width ((addr_offset_width+addr_set_width))
)
way_0_data_ram
@@ -45849,7 +41609,7 @@ endfunction
.read_address (dmem_read_address),
.enable_read (enable),
.write_address (dmem_write_address),
- .enable_write ( 1'b1),
+ .enable_write (1'b1),
.write_enable (way_mem_we[i]),
.write_data (refill_data),
@@ -45859,8 +41619,8 @@ endfunction
lm32_ram
#(
- .data_width ( (addr_tag_width+1)),
- .address_width ( addr_set_width)
+ .data_width ((addr_tag_width+1)),
+ .address_width (addr_set_width)
)
way_0_tag_ram
@@ -45872,7 +41632,7 @@ endfunction
.read_address (tmem_read_address),
.enable_read (enable),
.write_address (tmem_write_address),
- .enable_write ( 1'b1),
+ .enable_write (1'b1),
.write_enable (way_mem_we[i] | flushing),
.write_data (tmem_write_data),
@@ -45890,7 +41650,7 @@ endgenerate
generate
for (i = 0; i < associativity; i = i + 1)
begin : match
-assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb], 1'b1});
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[addr_tag_msb:addr_tag_lsb], 1'b1});
end
endgenerate
@@ -45909,55 +41669,55 @@ endgenerate
generate
if (bytes_per_line > 4)
-assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+assign dmem_write_address = {refill_address[addr_set_msb:addr_set_lsb], refill_offset};
else
-assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+assign dmem_write_address = refill_address[addr_set_msb:addr_set_lsb];
endgenerate
-assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+assign dmem_read_address = address_a[addr_set_msb:addr_offset_lsb];
-assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_read_address = address_a[addr_set_msb:addr_set_lsb];
assign tmem_write_address = flushing
? flush_set
- : refill_address[ addr_set_msb:addr_set_lsb];
+ : refill_address[addr_set_msb:addr_set_lsb];
generate
if (bytes_per_line > 4)
assign last_refill = refill_offset == {addr_offset_width{1'b1}};
else
-assign last_refill = 1'b1;
+assign last_refill = 1'b1;
endgenerate
-assign enable = (stall_a == 1'b0);
+assign enable = (stall_a == 1'b0);
generate
if (associativity == 1)
begin : we_1
-assign way_mem_we[0] = (refill_ready == 1'b1);
+assign way_mem_we[0] = (refill_ready == 1'b1);
end
else
begin : we_2
-assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1);
-assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1);
+assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1);
+assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1);
end
endgenerate
-assign tmem_write_data[ 0] = last_refill & !flushing;
-assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+assign tmem_write_data[0] = last_refill & !flushing;
+assign tmem_write_data[((addr_tag_width+1)-1):1] = refill_address[addr_tag_msb:addr_tag_lsb];
assign flushing = |state[1:0];
assign check = state[2];
assign refill = state[3];
-assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d);
-assign stall_request = (check == 1'b0);
-assign refill_request = (refill == 1'b1);
+assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check == 1'b0);
+assign refill_request = (refill == 1'b1);
@@ -45967,13 +41727,13 @@ assign refill_request = (refill == 1'b1);
generate
if (associativity >= 2)
begin : way_select
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
else
begin
- if (miss == 1'b1)
+ if (miss == 1'b1)
refill_way_select <= {refill_way_select[0], refill_way_select[1]};
end
end
@@ -45981,77 +41741,76 @@ end
endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- refilling <= 1'b0;
+ if (rst_i == 1'b1)
+ refilling <= 1'b0;
else
refilling <= refill;
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- state <= 4'b0001;
- flush_set <= { addr_set_width{1'b1}};
- refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
- restart_request <= 1'b0;
+ state <= 4'b0001;
+ flush_set <= {addr_set_width{1'b1}};
+ refill_address <= {(clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+ restart_request <= 1'b0;
end
else
begin
case (state)
- 4'b0001:
+ 4'b0001:
begin
- if (flush_set == { addr_set_width{1'b0}})
- state <= 4'b0100;
+ if (flush_set == {addr_set_width{1'b0}})
+ state <= 4'b0100;
flush_set <= flush_set - 1'b1;
end
- 4'b0010:
+ 4'b0010:
begin
- if (flush_set == { addr_set_width{1'b0}})
-
+ if (flush_set == {addr_set_width{1'b0}})
+
-
- state <= 4'b0100;
+ state <= 4'b0100;
flush_set <= flush_set - 1'b1;
end
- 4'b0100:
+ 4'b0100:
begin
- if (stall_a == 1'b0)
- restart_request <= 1'b0;
- if (iflush == 1'b1)
+ if (stall_a == 1'b0)
+ restart_request <= 1'b0;
+ if (iflush == 1'b1)
begin
refill_address <= address_f;
- state <= 4'b0010;
+ state <= 4'b0010;
end
- else if (miss == 1'b1)
+ else if (miss == 1'b1)
begin
refill_address <= address_f;
- state <= 4'b1000;
+ state <= 4'b1000;
end
end
- 4'b1000:
+ 4'b1000:
begin
- if (refill_ready == 1'b1)
+ if (refill_ready == 1'b1)
begin
- if (last_refill == 1'b1)
+ if (last_refill == 1'b1)
begin
- restart_request <= 1'b1;
- state <= 4'b0100;
+ restart_request <= 1'b1;
+ state <= 4'b0100;
end
end
end
@@ -46064,27 +41823,27 @@ generate
if (bytes_per_line > 4)
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
else
begin
case (state)
- 4'b0100:
+ 4'b0100:
begin
- if (iflush == 1'b1)
+ if (iflush == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
- else if (miss == 1'b1)
+ else if (miss == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
end
- 4'b1000:
+ 4'b1000:
begin
- if (refill_ready == 1'b1)
+ if (refill_ready == 1'b1)
refill_offset <= refill_offset + 1'b1;
end
@@ -46096,7 +41855,6 @@ endgenerate
endmodule
-
@@ -46129,10 +41887,7 @@ endmodule
-
-
-
-
+
@@ -46162,9 +41917,9 @@ endmodule
-
+
@@ -46448,9 +42203,7 @@ endmodule
-
-
-
+
@@ -46955,10 +42708,7 @@ endmodule
-
-
-
-
+
@@ -46989,9 +42739,8 @@ endmodule
-
-
+
@@ -47275,24 +43024,15 @@ endmodule
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
@@ -47309,31 +43049,24 @@ module lm32_debug_medium_debug (
csr_write_enable_x,
csr_write_data,
csr_x,
-
-
+
jtag_csr_write_enable,
jtag_csr_write_data,
jtag_csr,
-
-
-
+
eret_q_x,
bret_q_x,
stall_x,
exception_x,
q_x,
-
+
-
-
-
-
- dc_ss,
+ dc_ss,
dc_re,
bp_match,
@@ -47354,43 +43087,36 @@ parameter watchpoints = 0;
input clk_i;
input rst_i;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
input load_x;
input store_x;
-input [ (32-1):0] load_store_address_x;
+input [(32-1):0] load_store_address_x;
input csr_write_enable_x;
-input [ (32-1):0] csr_write_data;
-input [ (5-1):0] csr_x;
-
-
-input jtag_csr_write_enable;
-input [ (32-1):0] jtag_csr_write_data;
-input [ (5-1):0] jtag_csr;
+input [(32-1):0] csr_write_data;
+input [(5-1):0] csr_x;
+input jtag_csr_write_enable;
+input [(32-1):0] jtag_csr_write_data;
+input [(5-1):0] jtag_csr;
-
-
+
input eret_q_x;
input bret_q_x;
input stall_x;
input exception_x;
input q_x;
-
-
-
-
+
-
+
output dc_ss;
reg dc_ss;
-
output dc_re;
reg dc_re;
@@ -47407,33 +43133,29 @@ genvar i;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];
reg bp_e[0:breakpoints-1];
wire [0:breakpoints-1]bp_match_n;
-reg [ 1:0] wpc_c[0:watchpoints-1];
-reg [ (32-1):0] wp[0:watchpoints-1];
+reg [1:0] wpc_c[0:watchpoints-1];
+reg [(32-1):0] wp[0:watchpoints-1];
wire [0:watchpoints]wp_match_n;
wire debug_csr_write_enable;
-wire [ (32-1):0] debug_csr_write_data;
-wire [ (5-1):0] debug_csr;
+wire [(32-1):0] debug_csr_write_data;
+wire [(5-1):0] debug_csr;
-
+
+reg [2:0] state;
-reg [ 2:0] state;
-
-
-
-
-
+
@@ -47489,27 +43211,24 @@ endfunction
-
generate
for (i = 0; i < breakpoints; i = i + 1)
begin : bp_comb
-assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == 1'b1));
+assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == 1'b1));
end
endgenerate
generate
-
-
+
if (breakpoints > 0)
-assign bp_match = (|bp_match_n) || (state == 3'b011);
+assign bp_match = (|bp_match_n) || (state == 3'b011);
else
-assign bp_match = state == 3'b011;
-
+assign bp_match = state == 3'b011;
+
-
endgenerate
@@ -47523,16 +43242,15 @@ generate
if (watchpoints > 0)
assign wp_match = |wp_match_n;
else
-assign wp_match = 1'b0;
+assign wp_match = 1'b0;
endgenerate
-
-
+
+
+assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1);
+assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data;
+assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
-assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1);
-assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data;
-assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
-
@@ -47543,22 +43261,21 @@ assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
-
generate
for (i = 0; i < breakpoints; i = i + 1)
begin : bp_seq
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
- bp_e[i] <= 1'b0;
+ bp_a[i] <= {(clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+ bp_e[i] <= 1'b0;
end
else
begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i))
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i))
begin
- bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+ bp_a[i] <= debug_csr_write_data[((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
bp_e[i] <= debug_csr_write_data[0];
end
end
@@ -47570,20 +43287,20 @@ endgenerate
generate
for (i = 0; i < watchpoints; i = i + 1)
begin : wp_seq
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- wp[i] <= { 32{1'bx}};
- wpc_c[i] <= 2'b00;
+ wp[i] <= {32{1'bx}};
+ wpc_c[i] <= 2'b00;
end
else
begin
- if (debug_csr_write_enable == 1'b1)
+ if (debug_csr_write_enable == 1'b1)
begin
- if (debug_csr == 5'h8)
+ if (debug_csr == 5'h8)
wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
- if (debug_csr == 5'h18 + i)
+ if (debug_csr == 5'h18 + i)
wp[i] <= debug_csr_write_data;
end
end
@@ -47592,92 +43309,84 @@ end
endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- dc_re <= 1'b0;
+ if (rst_i == 1'b1)
+ dc_re <= 1'b0;
else
begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
dc_re <= debug_csr_write_data[1];
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- state <= 3'b000;
- dc_ss <= 1'b0;
+ state <= 3'b000;
+ dc_ss <= 1'b0;
end
else
begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
begin
dc_ss <= debug_csr_write_data[0];
- if (debug_csr_write_data[0] == 1'b0)
- state <= 3'b000;
+ if (debug_csr_write_data[0] == 1'b0)
+ state <= 3'b000;
else
- state <= 3'b001;
+ state <= 3'b001;
end
case (state)
- 3'b001:
+ 3'b001:
begin
- if ( ( (eret_q_x == 1'b1)
- || (bret_q_x == 1'b1)
+ if ( ( (eret_q_x == 1'b1)
+ || (bret_q_x == 1'b1)
)
- && (stall_x == 1'b0)
+ && (stall_x == 1'b0)
)
- state <= 3'b010;
+ state <= 3'b010;
end
- 3'b010:
+ 3'b010:
begin
- if ((q_x == 1'b1) && (stall_x == 1'b0))
- state <= 3'b011;
+ if ((q_x == 1'b1) && (stall_x == 1'b0))
+ state <= 3'b011;
end
- 3'b011:
+ 3'b011:
begin
-
+
-
- if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
+ if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
begin
- dc_ss <= 1'b0;
- state <= 3'b100;
+ dc_ss <= 1'b0;
+ state <= 3'b100;
end
end
- 3'b100:
+ 3'b100:
begin
-
+
-
- state <= 3'b000;
+ state <= 3'b000;
end
endcase
end
end
-
endmodule
-
-
-
-
@@ -47722,10 +43431,10 @@ endmodule
-
+
@@ -47755,9 +43464,9 @@ endmodule
-
+
@@ -48042,8 +43751,6 @@ endmodule
-
-
@@ -48062,48 +43769,39 @@ module lm32_instruction_unit_medium_debug (
kill_f,
branch_predict_taken_d,
branch_predict_address_d,
-
+
-
exception_m,
branch_taken_m,
branch_mispredict_taken_m,
branch_target_m,
-
-
- iflush,
+ iflush,
-
+
-
-
+
-
-
-
+
i_dat_i,
i_ack_i,
i_err_i,
i_rty_i,
-
-
-
+
jtag_read_enable,
jtag_write_enable,
jtag_write_data,
jtag_address,
-
@@ -48112,20 +43810,16 @@ module lm32_instruction_unit_medium_debug (
pc_x,
pc_m,
pc_w,
-
-
+
icache_stall_request,
icache_restart_request,
icache_refill_request,
icache_refilling,
-
-
+
-
-
-
+
i_dat_o,
i_adr_o,
@@ -48136,22 +43830,16 @@ module lm32_instruction_unit_medium_debug (
i_cti_o,
i_lock_o,
i_bte_o,
-
-
-
+
jtag_read_data,
jtag_access_complete,
-
-
+
-
-
-
- instruction_f,
+ instruction_f,
instruction_d
);
@@ -48188,72 +43876,62 @@ input valid_d;
input kill_f;
input branch_predict_taken_d;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
-
+
-
input exception_m;
input branch_taken_m;
input branch_mispredict_taken_m;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
-
-
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
-input iflush;
+input iflush;
-
+
-
-
+
-
-
-
-input [ (32-1):0] i_dat_i;
+
+input [(32-1):0] i_dat_i;
input i_ack_i;
input i_err_i;
input i_rty_i;
-
-
-
+
input jtag_read_enable;
input jtag_write_enable;
-input [ 7:0] jtag_write_data;
-input [ (32-1):0] jtag_address;
-
+input [7:0] jtag_write_data;
+input [(32-1):0] jtag_address;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-
-
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
output icache_stall_request;
wire icache_stall_request;
output icache_restart_request;
@@ -48262,138 +43940,111 @@ output icache_refill_request;
wire icache_refill_request;
output icache_refilling;
wire icache_refilling;
-
-
+
-
-
-
-output [ (32-1):0] i_dat_o;
-
-
-reg [ (32-1):0] i_dat_o;
-
+output [(32-1):0] i_dat_o;
+
+reg [(32-1):0] i_dat_o;
+
-output [ (32-1):0] i_adr_o;
-reg [ (32-1):0] i_adr_o;
+output [(32-1):0] i_adr_o;
+reg [(32-1):0] i_adr_o;
output i_cyc_o;
reg i_cyc_o;
-output [ (4-1):0] i_sel_o;
-
-
-reg [ (4-1):0] i_sel_o;
+output [(4-1):0] i_sel_o;
-
+reg [(4-1):0] i_sel_o;
+
output i_stb_o;
reg i_stb_o;
output i_we_o;
-
-
-reg i_we_o;
-
+reg i_we_o;
+
-output [ (3-1):0] i_cti_o;
-reg [ (3-1):0] i_cti_o;
+output [(3-1):0] i_cti_o;
+reg [(3-1):0] i_cti_o;
output i_lock_o;
reg i_lock_o;
-output [ (2-1):0] i_bte_o;
-wire [ (2-1):0] i_bte_o;
-
-
+output [(2-1):0] i_bte_o;
+wire [(2-1):0] i_bte_o;
-
-output [ 7:0] jtag_read_data;
-reg [ 7:0] jtag_read_data;
+
+output [7:0] jtag_read_data;
+reg [7:0] jtag_read_data;
output jtag_access_complete;
wire jtag_access_complete;
-
-
+
-
-
-
-output [ (32-1):0] instruction_f;
-wire [ (32-1):0] instruction_f;
+output [(32-1):0] instruction_f;
+wire [(32-1):0] instruction_f;
-output [ (32-1):0] instruction_d;
-reg [ (32-1):0] instruction_d;
+output [(32-1):0] instruction_d;
+reg [(32-1):0] instruction_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;
-
-
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;
-
-
+
wire icache_read_enable_f;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;
reg icache_refill_ready;
-reg [ (32-1):0] icache_refill_data;
-wire [ (32-1):0] icache_data_f;
-wire [ (3-1):0] first_cycle_type;
-wire [ (3-1):0] next_cycle_type;
+reg [(32-1):0] icache_refill_data;
+wire [(32-1):0] icache_data_f;
+wire [(3-1):0] first_cycle_type;
+wire [(3-1):0] next_cycle_type;
wire last_word;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;
-
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;
+
-
-
+
-
-
-
-
+
-
+
-
-
-
-reg jtag_access;
+reg jtag_access;
-
-
-
+
@@ -48449,8 +44100,7 @@ endfunction
-
-
+
@@ -48496,11 +44146,9 @@ endfunction
-
-
-
+
lm32_icache_medium_debug #(
.associativity (associativity),
@@ -48530,81 +44178,68 @@ lm32_icache_medium_debug #(
.refilling (icache_refilling),
.inst (icache_data_f)
);
-
-
-
+
-assign icache_read_enable_f = (valid_f == 1'b1)
- && (kill_f == 1'b0)
-
+assign icache_read_enable_f = (valid_f == 1'b1)
+ && (kill_f == 1'b0)
+
-
-
+
-
;
-
always @(*)
begin
-
+
-
- if (branch_taken_m == 1'b1)
- if ((branch_mispredict_taken_m == 1'b1) && (exception_m == 1'b0))
+ if (branch_taken_m == 1'b1)
+ if ((branch_mispredict_taken_m == 1'b1) && (exception_m == 1'b0))
pc_a = pc_x;
else
pc_a = branch_target_m;
-
+
-
else
- if ( (valid_d == 1'b1) && (branch_predict_taken_d == 1'b1) )
+ if ( (valid_d == 1'b1) && (branch_predict_taken_d == 1'b1) )
pc_a = branch_predict_address_d;
else
-
-
- if (icache_restart_request == 1'b1)
+
+ if (icache_restart_request == 1'b1)
pc_a = restart_address;
else
-
pc_a = pc_f + 1'b1;
end
-
+
-
-
-
-
+
+
-
assign instruction_f = icache_data_f;
-
-
+
@@ -48617,50 +44252,43 @@ assign instruction_f = icache_data_f;
-
-
-
-
-
+
+
-
-assign i_bte_o = 2'b00;
-
+assign i_bte_o = 2'b00;
-
-
+
generate
case (bytes_per_line)
4:
begin
-assign first_cycle_type = 3'b111;
-assign next_cycle_type = 3'b111;
-assign last_word = 1'b1;
+assign first_cycle_type = 3'b111;
+assign next_cycle_type = 3'b111;
+assign last_word = 1'b1;
assign first_address = icache_refill_address;
end
8:
begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = 3'b111;
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = 3'b111;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
-assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+assign first_address = {icache_refill_address[(clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
end
16:
begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
-assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+assign first_address = {icache_refill_address[(clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
end
endcase
endgenerate
-
@@ -48668,40 +44296,39 @@ endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- pc_f <= ( 32'h00000000-4)/4;
- pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_f <= (32'h00000000-4)/4;
+ pc_d <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_x <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_m <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_w <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
end
else
begin
- if (stall_f == 1'b0)
+ if (stall_f == 1'b0)
pc_f <= pc_a;
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
pc_d <= pc_f;
- if (stall_x == 1'b0)
+ if (stall_x == 1'b0)
pc_x <= pc_d;
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
pc_m <= pc_x;
pc_w <= pc_m;
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ if (rst_i == 1'b1)
+ restart_address <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
else
begin
-
+
@@ -48713,22 +44340,17 @@ begin
-
-
-
- if (icache_refill_request == 1'b1)
+
+ if (icache_refill_request == 1'b1)
restart_address <= icache_refill_address;
-
-
end
end
-
-
+
@@ -48741,121 +44363,106 @@ end
-
-
-
-assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1);
+
+assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1);
always @(*)
begin
case (jtag_address[1:0])
- 2'b00: jtag_read_data = i_dat_i[ 31:24];
- 2'b01: jtag_read_data = i_dat_i[ 23:16];
- 2'b10: jtag_read_data = i_dat_i[ 15:8];
- 2'b11: jtag_read_data = i_dat_i[ 7:0];
+ 2'b00: jtag_read_data = i_dat_i[31:24];
+ 2'b01: jtag_read_data = i_dat_i[23:16];
+ 2'b10: jtag_read_data = i_dat_i[15:8];
+ 2'b11: jtag_read_data = i_dat_i[7:0];
endcase
end
-
-
-
+
-
-
-always @(posedge clk_i )
+
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_adr_o <= { 32{1'b0}};
- i_cti_o <= 3'b111;
- i_lock_o <= 1'b0;
- icache_refill_data <= { 32{1'b0}};
- icache_refill_ready <= 1'b0;
-
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_adr_o <= {32{1'b0}};
+ i_cti_o <= 3'b111;
+ i_lock_o <= 1'b0;
+ icache_refill_data <= {32{1'b0}};
+ icache_refill_ready <= 1'b0;
+
-
-
-
- i_we_o <= 1'b0;
- i_sel_o <= 4'b1111;
- jtag_access <= 1'b0;
+ i_we_o <= 1'b0;
+ i_sel_o <= 4'b1111;
+ jtag_access <= 1'b0;
end
else
begin
- icache_refill_ready <= 1'b0;
+ icache_refill_ready <= 1'b0;
- if (i_cyc_o == 1'b1)
+ if (i_cyc_o == 1'b1)
begin
- if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
+ if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
begin
-
-
- if (jtag_access == 1'b1)
+
+ if (jtag_access == 1'b1)
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_we_o <= 1'b0;
- jtag_access <= 1'b0;
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_we_o <= 1'b0;
+ jtag_access <= 1'b0;
end
else
-
begin
- if (last_word == 1'b1)
+ if (last_word == 1'b1)
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_lock_o <= 1'b0;
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_lock_o <= 1'b0;
end
i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
i_cti_o <= next_cycle_type;
- icache_refill_ready <= 1'b1;
+ icache_refill_ready <= 1'b1;
icache_refill_data <= i_dat_i;
end
end
-
+
-
end
else
begin
- if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
+ if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
begin
-
-
+
i_sel_o <= 4'b1111;
-
i_adr_o <= {first_address, 2'b00};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
i_cti_o <= first_cycle_type;
-
+
-
end
-
-
+
else
begin
- if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1))
+ if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1))
begin
case (jtag_address[1:0])
2'b00: i_sel_o <= 4'b1000;
@@ -48865,16 +44472,15 @@ begin
endcase
i_adr_o <= jtag_address;
i_dat_o <= {4{jtag_write_data}};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
i_we_o <= jtag_write_enable;
- i_cti_o <= 3'b111;
- jtag_access <= 1'b1;
+ i_cti_o <= 3'b111;
+ jtag_access <= 1'b1;
end
end
-
-
+
@@ -48884,11 +44490,10 @@ begin
-
end
end
end
-
+
@@ -48962,30 +44567,26 @@ end
-
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- instruction_d <= { 32{1'b0}};
-
+ instruction_d <= {32{1'b0}};
+
-
end
else
begin
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
begin
instruction_d <= instruction_f;
-
+
-
end
end
end
@@ -49019,10 +44620,7 @@ endmodule
-
-
-
-
+
@@ -49052,9 +44650,9 @@ endmodule
-
+
@@ -49338,57 +44936,33 @@ endmodule
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
-
+
+
+
+
+
+
+
+
+
+
@@ -49402,34 +44976,25 @@ module lm32_jtag_medium_debug (
jtag_update,
jtag_reg_q,
jtag_reg_addr_q,
-
-
+
csr,
csr_write_enable,
csr_write_data,
stall_x,
-
-
-
+
jtag_read_data,
jtag_access_complete,
-
-
-
- exception_q_w,
+ exception_q_w,
-
-
+
jtx_csr_read_data,
jrx_csr_read_data,
-
-
-
+
jtag_csr_write_enable,
jtag_csr_write_data,
jtag_csr,
@@ -49437,13 +45002,10 @@ module lm32_jtag_medium_debug (
jtag_write_enable,
jtag_write_data,
jtag_address,
-
-
-
+
jtag_break,
jtag_reset,
-
jtag_reg_d,
jtag_reg_addr_d
@@ -49458,69 +45020,57 @@ input rst_i;
input jtag_clk;
input jtag_update;
-input [ 7:0] jtag_reg_q;
+input [7:0] jtag_reg_q;
input [2:0] jtag_reg_addr_q;
-
-
-input [ (5-1):0] csr;
+
+input [(5-1):0] csr;
input csr_write_enable;
-input [ (32-1):0] csr_write_data;
+input [(32-1):0] csr_write_data;
input stall_x;
-
-
-
-input [ 7:0] jtag_read_data;
-input jtag_access_complete;
+input [7:0] jtag_read_data;
+input jtag_access_complete;
-
-
-input exception_q_w;
+input exception_q_w;
-
-
-output [ (32-1):0] jtx_csr_read_data;
-wire [ (32-1):0] jtx_csr_read_data;
-output [ (32-1):0] jrx_csr_read_data;
-wire [ (32-1):0] jrx_csr_read_data;
+output [(32-1):0] jtx_csr_read_data;
+wire [(32-1):0] jtx_csr_read_data;
+output [(32-1):0] jrx_csr_read_data;
+wire [(32-1):0] jrx_csr_read_data;
-
-
+
output jtag_csr_write_enable;
reg jtag_csr_write_enable;
-output [ (32-1):0] jtag_csr_write_data;
-wire [ (32-1):0] jtag_csr_write_data;
-output [ (5-1):0] jtag_csr;
-wire [ (5-1):0] jtag_csr;
+output [(32-1):0] jtag_csr_write_data;
+wire [(32-1):0] jtag_csr_write_data;
+output [(5-1):0] jtag_csr;
+wire [(5-1):0] jtag_csr;
output jtag_read_enable;
reg jtag_read_enable;
output jtag_write_enable;
reg jtag_write_enable;
-output [ 7:0] jtag_write_data;
-wire [ 7:0] jtag_write_data;
-output [ (32-1):0] jtag_address;
-wire [ (32-1):0] jtag_address;
-
-
-
+output [7:0] jtag_write_data;
+wire [7:0] jtag_write_data;
+output [(32-1):0] jtag_address;
+wire [(32-1):0] jtag_address;
+
output jtag_break;
reg jtag_break;
output jtag_reset;
reg jtag_reset;
-
-output [ 7:0] jtag_reg_d;
-reg [ 7:0] jtag_reg_d;
+output [7:0] jtag_reg_d;
+reg [7:0] jtag_reg_d;
output [2:0] jtag_reg_addr_d;
wire [2:0] jtag_reg_addr_d;
@@ -49535,66 +45085,54 @@ reg rx_update_r_r_r;
-wire [ 7:0] rx_byte;
+wire [7:0] rx_byte;
wire [2:0] rx_addr;
-
-
-reg [ 7:0] uart_tx_byte;
+
+reg [7:0] uart_tx_byte;
reg uart_tx_valid;
-reg [ 7:0] uart_rx_byte;
+reg [7:0] uart_rx_byte;
reg uart_rx_valid;
-
-reg [ 3:0] command;
-
-
-reg [ 7:0] jtag_byte_0;
-reg [ 7:0] jtag_byte_1;
-reg [ 7:0] jtag_byte_2;
-reg [ 7:0] jtag_byte_3;
-reg [ 7:0] jtag_byte_4;
-reg processing;
+reg [3:0] command;
+reg [7:0] jtag_byte_0;
+reg [7:0] jtag_byte_1;
+reg [7:0] jtag_byte_2;
+reg [7:0] jtag_byte_3;
+reg [7:0] jtag_byte_4;
+reg processing;
-reg [ 3:0] state;
-
+reg [3:0] state;
-
+
assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
-assign jtag_csr = jtag_byte_4[ (5-1):0];
+assign jtag_csr = jtag_byte_4[(5-1):0];
assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
assign jtag_write_data = jtag_byte_4;
-
-
-
+
assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
-
-
-
-
+
-assign jtag_reg_addr_d[2] = processing;
-
+assign jtag_reg_addr_d[2] = processing;
+
-
-
-assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
-assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
-
+
+assign jtx_csr_read_data = {{32-9{1'b0}}, uart_tx_valid, 8'h00};
+assign jrx_csr_read_data = {{32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
@@ -49606,9 +45144,9 @@ assign rx_addr = jtag_reg_addr_q;
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
rx_update <= 1'b0;
rx_update_r <= 1'b0;
@@ -49625,232 +45163,210 @@ begin
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- state <= 4'h0;
+ state <= 4'h0;
command <= 4'b0000;
jtag_reg_d <= 8'h00;
-
-
- processing <= 1'b0;
- jtag_csr_write_enable <= 1'b0;
- jtag_read_enable <= 1'b0;
- jtag_write_enable <= 1'b0;
+ processing <= 1'b0;
+ jtag_csr_write_enable <= 1'b0;
+ jtag_read_enable <= 1'b0;
+ jtag_write_enable <= 1'b0;
-
-
- jtag_break <= 1'b0;
- jtag_reset <= 1'b0;
+ jtag_break <= 1'b0;
+ jtag_reset <= 1'b0;
-
-
+
uart_tx_byte <= 8'h00;
- uart_tx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
uart_rx_byte <= 8'h00;
- uart_rx_valid <= 1'b0;
-
+ uart_rx_valid <= 1'b0;
end
else
begin
-
-
- if ((csr_write_enable == 1'b1) && (stall_x == 1'b0))
+
+ if ((csr_write_enable == 1'b1) && (stall_x == 1'b0))
begin
case (csr)
- 5'he:
+ 5'he:
begin
- uart_tx_byte <= csr_write_data[ 7:0];
- uart_tx_valid <= 1'b1;
+ uart_tx_byte <= csr_write_data[7:0];
+ uart_tx_valid <= 1'b1;
end
- 5'hf:
+ 5'hf:
begin
- uart_rx_valid <= 1'b0;
+ uart_rx_valid <= 1'b0;
end
endcase
end
-
-
-
+
- if (exception_q_w == 1'b1)
+ if (exception_q_w == 1'b1)
begin
- jtag_break <= 1'b0;
- jtag_reset <= 1'b0;
+ jtag_break <= 1'b0;
+ jtag_reset <= 1'b0;
end
-
case (state)
- 4'h0:
+ 4'h0:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
command <= rx_byte[7:4];
case (rx_addr)
-
-
- 3'b000:
+
+ 3'b000:
begin
case (rx_byte[7:4])
-
-
- 4'b0001:
- state <= 4'h1;
- 4'b0011:
+
+ 4'b0001:
+ state <= 4'h1;
+ 4'b0011:
begin
{jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
- state <= 4'h6;
+ state <= 4'h6;
end
- 4'b0010:
- state <= 4'h1;
- 4'b0100:
+ 4'b0010:
+ state <= 4'h1;
+ 4'b0100:
begin
{jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
state <= 5;
end
- 4'b0101:
- state <= 4'h1;
-
+ 4'b0101:
+ state <= 4'h1;
- 4'b0110:
+ 4'b0110:
begin
-
-
- uart_rx_valid <= 1'b0;
- uart_tx_valid <= 1'b0;
-
+
+ uart_rx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
- jtag_break <= 1'b1;
+ jtag_break <= 1'b1;
end
- 4'b0111:
+ 4'b0111:
begin
-
-
- uart_rx_valid <= 1'b0;
- uart_tx_valid <= 1'b0;
-
+
+ uart_rx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
- jtag_reset <= 1'b1;
+ jtag_reset <= 1'b1;
end
endcase
end
-
-
-
- 3'b001:
+
+ 3'b001:
begin
uart_rx_byte <= rx_byte;
- uart_rx_valid <= 1'b1;
+ uart_rx_valid <= 1'b1;
end
- 3'b010:
+ 3'b010:
begin
jtag_reg_d <= uart_tx_byte;
- uart_tx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
end
-
default:
;
endcase
end
end
-
-
- 4'h1:
+
+ 4'h1:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
jtag_byte_0 <= rx_byte;
- state <= 4'h2;
+ state <= 4'h2;
end
end
- 4'h2:
+ 4'h2:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
jtag_byte_1 <= rx_byte;
- state <= 4'h3;
+ state <= 4'h3;
end
end
- 4'h3:
+ 4'h3:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
jtag_byte_2 <= rx_byte;
- state <= 4'h4;
+ state <= 4'h4;
end
end
- 4'h4:
+ 4'h4:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
jtag_byte_3 <= rx_byte;
- if (command == 4'b0001)
- state <= 4'h6;
+ if (command == 4'b0001)
+ state <= 4'h6;
else
- state <= 4'h5;
+ state <= 4'h5;
end
end
- 4'h5:
+ 4'h5:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
jtag_byte_4 <= rx_byte;
- state <= 4'h6;
+ state <= 4'h6;
end
end
- 4'h6:
+ 4'h6:
begin
case (command)
- 4'b0001,
- 4'b0011:
+ 4'b0001,
+ 4'b0011:
begin
- jtag_read_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h7;
+ jtag_read_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h7;
end
- 4'b0010,
- 4'b0100:
+ 4'b0010,
+ 4'b0100:
begin
- jtag_write_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h7;
+ jtag_write_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h7;
end
- 4'b0101:
+ 4'b0101:
begin
- jtag_csr_write_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h8;
+ jtag_csr_write_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h8;
end
endcase
end
- 4'h7:
+ 4'h7:
begin
- if (jtag_access_complete == 1'b1)
+ if (jtag_access_complete == 1'b1)
begin
- jtag_read_enable <= 1'b0;
+ jtag_read_enable <= 1'b0;
jtag_reg_d <= jtag_read_data;
- jtag_write_enable <= 1'b0;
- processing <= 1'b0;
- state <= 4'h0;
+ jtag_write_enable <= 1'b0;
+ processing <= 1'b0;
+ state <= 4'h0;
end
end
- 4'h8:
+ 4'h8:
begin
- jtag_csr_write_enable <= 1'b0;
- processing <= 1'b0;
- state <= 4'h0;
+ jtag_csr_write_enable <= 1'b0;
+ processing <= 1'b0;
+ state <= 4'h0;
end
-
endcase
end
@@ -49858,8 +45374,6 @@ end
endmodule
-
-
@@ -49888,10 +45402,8 @@ endmodule
-
-
-
+
@@ -49921,9 +45433,9 @@ endmodule
-
+
@@ -50208,8 +45720,6 @@ endmodule
-
-
@@ -50221,19 +45731,15 @@ module lm32_interrupt_medium_debug (
interrupt,
stall_x,
-
-
+
non_debug_exception,
debug_exception,
-
-
+
eret_q_x,
-
-
- bret_q_x,
+ bret_q_x,
csr,
csr_write_data,
@@ -50248,7 +45754,7 @@ module lm32_interrupt_medium_debug (
-parameter interrupts = 32;
+parameter interrupts = 32;
@@ -50261,23 +45767,19 @@ input [interrupts-1:0] interrupt;
input stall_x;
-
-
+
input non_debug_exception;
input debug_exception;
-
-
+
input eret_q_x;
-
-
-input bret_q_x;
+input bret_q_x;
-input [ (5-1):0] csr;
-input [ (32-1):0] csr_write_data;
+input [(5-1):0] csr;
+input [(32-1):0] csr_write_data;
input csr_write_enable;
@@ -50287,8 +45789,8 @@ input csr_write_enable;
output interrupt_exception;
wire interrupt_exception;
-output [ (32-1):0] csr_read_data;
-reg [ (32-1):0] csr_read_data;
+output [(32-1):0] csr_read_data;
+reg [(32-1):0] csr_read_data;
@@ -50302,10 +45804,8 @@ wire [interrupts-1:0] interrupt_n_exception;
reg ie;
reg eie;
-
-
-reg bie;
+reg bie;
reg [interrupts-1:0] ip;
reg [interrupts-1:0] im;
@@ -50323,13 +45823,11 @@ assign interrupt_exception = (|interrupt_n_exception) & ie;
assign asserted = ip | interrupt;
-assign ie_csr_read_data = {{ 32-3{1'b0}},
-
-
- bie,
+assign ie_csr_read_data = {{32-3{1'b0}},
-
+ bie,
+
eie,
ie
@@ -50343,20 +45841,18 @@ generate
always @(*)
begin
case (csr)
- 5'h0: csr_read_data = {{ 32-3{1'b0}},
-
-
- bie,
+ 5'h0: csr_read_data = {{32-3{1'b0}},
-
+ bie,
+
eie,
ie
};
- 5'h2: csr_read_data = ip;
- 5'h1: csr_read_data = im;
- default: csr_read_data = { 32{1'bx}};
+ 5'h2: csr_read_data = ip;
+ 5'h1: csr_read_data = im;
+ default: csr_read_data = {32{1'bx}};
endcase
end
end
@@ -50366,19 +45862,17 @@ end
always @(*)
begin
case (csr)
- 5'h0: csr_read_data = {{ 32-3{1'b0}},
-
-
- bie,
+ 5'h0: csr_read_data = {{32-3{1'b0}},
-
+ bie,
+
eie,
ie
};
- 5'h2: csr_read_data = ip;
- default: csr_read_data = { 32{1'bx}};
+ 5'h2: csr_read_data = ip;
+ default: csr_read_data = {32{1'bx}};
endcase
end
end
@@ -50388,9 +45882,8 @@ endgenerate
-
-
- reg [ 10:0] eie_delay = 0;
+
+ reg [10:0] eie_delay = 0;
generate
@@ -50399,16 +45892,14 @@ generate
if (interrupts > 1)
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- ie <= 1'b0;
- eie <= 1'b0;
-
-
- bie <= 1'b0;
+ ie <= 1'b0;
+ eie <= 1'b0;
+ bie <= 1'b0;
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
@@ -50419,21 +45910,20 @@ always @(posedge clk_i )
begin
ip <= asserted;
-
-
- if (non_debug_exception == 1'b1)
+
+ if (non_debug_exception == 1'b1)
begin
eie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
- else if (debug_exception == 1'b1)
+ else if (debug_exception == 1'b1)
begin
bie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
-
+
@@ -50441,46 +45931,41 @@ always @(posedge clk_i )
-
- else if (stall_x == 1'b0)
+ else if (stall_x == 1'b0)
begin
if(eie_delay[0])
ie <= eie;
- eie_delay <= {1'b0, eie_delay[ 10:1]};
+ eie_delay <= {1'b0, eie_delay[10:1]};
- if (eret_q_x == 1'b1) begin
+ if (eret_q_x == 1'b1) begin
- eie_delay[ 10] <= 1'b1;
- eie_delay[ 10-1:0] <= 0;
+ eie_delay[10] <= 1'b1;
+ eie_delay[10-1:0] <= 0;
end
-
-
- else if (bret_q_x == 1'b1)
+
+ else if (bret_q_x == 1'b1)
ie <= bie;
-
- else if (csr_write_enable == 1'b1)
+ else if (csr_write_enable == 1'b1)
begin
- if (csr == 5'h0)
+ if (csr == 5'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
-
- bie <= csr_write_data[2];
+ bie <= csr_write_data[2];
end
- if (csr == 5'h1)
+ if (csr == 5'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 5'h2)
+ if (csr == 5'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -50490,16 +45975,14 @@ end
else
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- ie <= 1'b0;
- eie <= 1'b0;
-
-
- bie <= 1'b0;
+ ie <= 1'b0;
+ eie <= 1'b0;
+ bie <= 1'b0;
ip <= {interrupts{1'b0}};
eie_delay <= 0;
@@ -50508,21 +45991,20 @@ always @(posedge clk_i )
begin
ip <= asserted;
-
-
- if (non_debug_exception == 1'b1)
+
+ if (non_debug_exception == 1'b1)
begin
eie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
- else if (debug_exception == 1'b1)
+ else if (debug_exception == 1'b1)
begin
bie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
-
+
@@ -50530,42 +46012,37 @@ always @(posedge clk_i )
-
- else if (stall_x == 1'b0)
+ else if (stall_x == 1'b0)
begin
if(eie_delay[0])
ie <= eie;
- eie_delay <= {1'b0, eie_delay[ 10:1]};
+ eie_delay <= {1'b0, eie_delay[10:1]};
- if (eret_q_x == 1'b1) begin
+ if (eret_q_x == 1'b1) begin
- eie_delay[ 10] <= 1'b1;
- eie_delay[ 10-1:0] <= 0;
+ eie_delay[10] <= 1'b1;
+ eie_delay[10-1:0] <= 0;
end
-
-
- else if (bret_q_x == 1'b1)
+
+ else if (bret_q_x == 1'b1)
ie <= bie;
-
- else if (csr_write_enable == 1'b1)
+ else if (csr_write_enable == 1'b1)
begin
- if (csr == 5'h0)
+ if (csr == 5'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
-
- bie <= csr_write_data[2];
+ bie <= csr_write_data[2];
end
- if (csr == 5'h2)
+ if (csr == 5'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -50605,50 +46082,27 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -50657,26 +46111,8 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
@@ -50694,271 +46130,197 @@ endmodule
-
-
-
-
-
-
-
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
-
+
+
+
+
-
+
+
-
-
+
+
+
+
+
+
-
+
+
+
-
+
+
+
-
-
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
-
-
-
-
-
-
+
+
+
+
-
-
-
-
+
+
-
+
+
-
+
+
-
-
-
+
+
-
+
+
-
+
-
-
+
-
-
+
+
+
+
+
+
+
+
+
+
-
+
+
+
+
+
+
-
+
-
-
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
-
-
-
-
+
+
-
-
+
@@ -50967,156 +46329,100 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
-
-
-
+
+
+
-
-
+
+
+
+
-
-
+
+
+
+
-
-
+
+
+
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
@@ -51135,19 +46441,16 @@ module lm32_top_medium_icache (
interrupt,
-
+
-
-
-
+
I_DAT_I,
I_ACK_I,
I_ERR_I,
I_RTY_I,
-
D_DAT_I,
@@ -51155,15 +46458,13 @@ module lm32_top_medium_icache (
D_ERR_I,
D_RTY_I,
-
+
-
-
-
+
I_DAT_O,
I_ADR_O,
@@ -51174,7 +46475,6 @@ module lm32_top_medium_icache (
I_CTI_O,
I_LOCK_O,
I_BTE_O,
-
D_DAT_O,
@@ -51196,25 +46496,22 @@ input clk_i;
input rst_i;
-input [ (32-1):0] interrupt;
+input [(32-1):0] interrupt;
-
+
-
-
-
-input [ (32-1):0] I_DAT_I;
+
+input [(32-1):0] I_DAT_I;
input I_ACK_I;
input I_ERR_I;
input I_RTY_I;
-
-input [ (32-1):0] D_DAT_I;
+input [(32-1):0] D_DAT_I;
input D_ACK_I;
input D_ERR_I;
input D_RTY_I;
@@ -51223,7 +46520,7 @@ input D_RTY_I;
-
+
@@ -51234,54 +46531,51 @@ input D_RTY_I;
-
-
-
-output [ (32-1):0] I_DAT_O;
-wire [ (32-1):0] I_DAT_O;
-output [ (32-1):0] I_ADR_O;
-wire [ (32-1):0] I_ADR_O;
+
+output [(32-1):0] I_DAT_O;
+wire [(32-1):0] I_DAT_O;
+output [(32-1):0] I_ADR_O;
+wire [(32-1):0] I_ADR_O;
output I_CYC_O;
wire I_CYC_O;
-output [ (4-1):0] I_SEL_O;
-wire [ (4-1):0] I_SEL_O;
+output [(4-1):0] I_SEL_O;
+wire [(4-1):0] I_SEL_O;
output I_STB_O;
wire I_STB_O;
output I_WE_O;
wire I_WE_O;
-output [ (3-1):0] I_CTI_O;
-wire [ (3-1):0] I_CTI_O;
+output [(3-1):0] I_CTI_O;
+wire [(3-1):0] I_CTI_O;
output I_LOCK_O;
wire I_LOCK_O;
-output [ (2-1):0] I_BTE_O;
-wire [ (2-1):0] I_BTE_O;
-
+output [(2-1):0] I_BTE_O;
+wire [(2-1):0] I_BTE_O;
-output [ (32-1):0] D_DAT_O;
-wire [ (32-1):0] D_DAT_O;
-output [ (32-1):0] D_ADR_O;
-wire [ (32-1):0] D_ADR_O;
+output [(32-1):0] D_DAT_O;
+wire [(32-1):0] D_DAT_O;
+output [(32-1):0] D_ADR_O;
+wire [(32-1):0] D_ADR_O;
output D_CYC_O;
wire D_CYC_O;
-output [ (4-1):0] D_SEL_O;
-wire [ (4-1):0] D_SEL_O;
+output [(4-1):0] D_SEL_O;
+wire [(4-1):0] D_SEL_O;
output D_STB_O;
wire D_STB_O;
output D_WE_O;
wire D_WE_O;
-output [ (3-1):0] D_CTI_O;
-wire [ (3-1):0] D_CTI_O;
+output [(3-1):0] D_CTI_O;
+wire [(3-1):0] D_CTI_O;
output D_LOCK_O;
wire D_LOCK_O;
-output [ (2-1):0] D_BTE_O;
-wire [ (2-1):0] D_BTE_O;
+output [(2-1):0] D_BTE_O;
+wire [(2-1):0] D_BTE_O;
-
+
@@ -51293,8 +46587,7 @@ wire [ (2-1):0] D_BTE_O;
-
-
+
@@ -51310,10 +46603,7 @@ wire [ (2-1):0] D_BTE_O;
-
-
-
-
+
@@ -51366,45 +46656,37 @@ endfunction
-
lm32_cpu_medium_icache cpu (
.clk_i (clk_i),
-
+
-
.rst_i (rst_i),
-
-
- .interrupt (interrupt),
+ .interrupt (interrupt),
-
+
-
-
+
-
-
-
+
.I_DAT_I (I_DAT_I),
.I_ACK_I (I_ACK_I),
.I_ERR_I (I_ERR_I),
.I_RTY_I (I_RTY_I),
-
.D_DAT_I (D_DAT_I),
@@ -51412,7 +46694,7 @@ lm32_cpu_medium_icache cpu (
.D_ERR_I (D_ERR_I),
.D_RTY_I (D_RTY_I),
-
+
@@ -51422,21 +46704,17 @@ lm32_cpu_medium_icache cpu (
-
-
+
-
-
+
-
-
-
+
.I_DAT_O (I_DAT_O),
.I_ADR_O (I_ADR_O),
@@ -51447,8 +46725,7 @@ lm32_cpu_medium_icache cpu (
.I_CTI_O (I_CTI_O),
.I_LOCK_O (I_LOCK_O),
.I_BTE_O (I_BTE_O),
-
-
+
.D_DAT_O (D_DAT_O),
.D_ADR_O (D_ADR_O),
@@ -51461,7 +46738,7 @@ lm32_cpu_medium_icache cpu (
.D_BTE_O (D_BTE_O)
);
-
+
@@ -51474,7 +46751,6 @@ lm32_cpu_medium_icache cpu (
-
endmodule
@@ -51506,10 +46782,7 @@ endmodule
-
-
-
-
+
@@ -51539,9 +46812,9 @@ endmodule
-
+
@@ -51823,24 +47096,15 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
@@ -51852,29 +47116,25 @@ module lm32_mc_arithmetic_medium_icache (
rst_i,
stall_d,
kill_x,
-
+
-
-
+
-
-
+
-
operand_0_d,
operand_1_d,
result_x,
-
+
-
stall_request_x
);
@@ -51886,35 +47146,31 @@ input clk_i;
input rst_i;
input stall_d;
input kill_x;
-
+
-
-
+
-
-
+
-
-input [ (32-1):0] operand_0_d;
-input [ (32-1):0] operand_1_d;
+input [(32-1):0] operand_0_d;
+input [(32-1):0] operand_1_d;
-output [ (32-1):0] result_x;
-reg [ (32-1):0] result_x;
-
+output [(32-1):0] result_x;
+reg [(32-1):0] result_x;
+
-
output stall_request_x;
wire stall_request_x;
@@ -51922,18 +47178,17 @@ wire stall_request_x;
-reg [ (32-1):0] p;
-reg [ (32-1):0] a;
-reg [ (32-1):0] b;
-
+reg [(32-1):0] p;
+reg [(32-1):0] a;
+reg [(32-1):0] b;
+
-
-reg [ 2:0] state;
+reg [2:0] state;
reg [5:0] cycles;
-
+
@@ -51943,16 +47198,14 @@ reg [5:0] cycles;
+assign stall_request_x = state != 3'b000;
-assign stall_request_x = state != 3'b000;
-
-
+
-
-
+
@@ -51962,54 +47215,48 @@ assign stall_request_x = state != 3'b000;
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
cycles <= {6{1'b0}};
- p <= { 32{1'b0}};
- a <= { 32{1'b0}};
- b <= { 32{1'b0}};
-
+ p <= {32{1'b0}};
+ a <= {32{1'b0}};
+ b <= {32{1'b0}};
+
-
-
+
-
- result_x <= { 32{1'b0}};
- state <= 3'b000;
+ result_x <= {32{1'b0}};
+ state <= 3'b000;
end
else
begin
-
+
-
case (state)
- 3'b000:
+ 3'b000:
begin
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
begin
- cycles <= 32;
+ cycles <= 32;
p <= 32'b0;
a <= operand_0_d;
b <= operand_1_d;
-
+
-
-
+
-
-
+
@@ -52026,11 +47273,10 @@ begin
-
end
end
-
+
@@ -52073,9 +47319,8 @@ begin
-
-
+
@@ -52087,9 +47332,8 @@ begin
-
-
+
@@ -52106,7 +47350,6 @@ begin
-
endcase
end
@@ -52177,10 +47420,7 @@ endmodule
-
-
-
-
+
@@ -52210,9 +47450,9 @@ endmodule
-
+
@@ -52497,47 +47737,38 @@ endmodule
-
-
module lm32_cpu_medium_icache (
clk_i,
-
+
-
rst_i,
-
-
- interrupt,
+ interrupt,
-
+
-
-
+
-
-
-
+
I_DAT_I,
I_ACK_I,
I_ERR_I,
I_RTY_I,
-
D_DAT_I,
@@ -52545,7 +47776,7 @@ module lm32_cpu_medium_icache (
D_ERR_I,
D_RTY_I,
-
+
@@ -52555,21 +47786,17 @@ module lm32_cpu_medium_icache (
-
-
+
-
-
+
-
-
-
+
I_DAT_O,
I_ADR_O,
@@ -52580,7 +47807,6 @@ module lm32_cpu_medium_icache (
I_CTI_O,
I_LOCK_O,
I_BTE_O,
-
D_DAT_O,
@@ -52598,20 +47824,18 @@ module lm32_cpu_medium_icache (
-parameter eba_reset = 32'h00000000;
-
+parameter eba_reset = 32'h00000000;
+
-
-
-
-parameter icache_associativity = 1;
-parameter icache_sets = 256;
-parameter icache_bytes_per_line = 16;
-parameter icache_base_address = 32'h0;
-parameter icache_limit = 32'h7fffffff;
+parameter icache_associativity = 1;
+parameter icache_sets = 256;
+parameter icache_bytes_per_line = 16;
+parameter icache_base_address = 32'h0;
+parameter icache_limit = 32'h7fffffff;
+
@@ -52619,44 +47843,35 @@ parameter icache_limit = 32'h7fffffff;
-
-
+
-
parameter dcache_associativity = 1;
parameter dcache_sets = 512;
parameter dcache_bytes_per_line = 16;
parameter dcache_base_address = 0;
parameter dcache_limit = 0;
-
-
+
-
parameter watchpoints = 0;
-
-
+
-
parameter breakpoints = 0;
-
-
-
-parameter interrupts = 32;
-
+parameter interrupts = 32;
+
@@ -52664,42 +47879,35 @@ parameter interrupts = 32;
input clk_i;
-
+
-
input rst_i;
-
-
-input [ (32-1):0] interrupt;
+input [(32-1):0] interrupt;
-
+
-
-
+
-
-
-
-input [ (32-1):0] I_DAT_I;
+
+input [(32-1):0] I_DAT_I;
input I_ACK_I;
input I_ERR_I;
input I_RTY_I;
-
-input [ (32-1):0] D_DAT_I;
+input [(32-1):0] D_DAT_I;
input D_ACK_I;
input D_ERR_I;
input D_RTY_I;
@@ -52708,7 +47916,7 @@ input D_RTY_I;
-
+
@@ -52725,16 +47933,14 @@ input D_RTY_I;
-
-
+
-
-
+
@@ -52745,48 +47951,45 @@ input D_RTY_I;
-
-
-
-output [ (32-1):0] I_DAT_O;
-wire [ (32-1):0] I_DAT_O;
-output [ (32-1):0] I_ADR_O;
-wire [ (32-1):0] I_ADR_O;
+
+output [(32-1):0] I_DAT_O;
+wire [(32-1):0] I_DAT_O;
+output [(32-1):0] I_ADR_O;
+wire [(32-1):0] I_ADR_O;
output I_CYC_O;
wire I_CYC_O;
-output [ (4-1):0] I_SEL_O;
-wire [ (4-1):0] I_SEL_O;
+output [(4-1):0] I_SEL_O;
+wire [(4-1):0] I_SEL_O;
output I_STB_O;
wire I_STB_O;
output I_WE_O;
wire I_WE_O;
-output [ (3-1):0] I_CTI_O;
-wire [ (3-1):0] I_CTI_O;
+output [(3-1):0] I_CTI_O;
+wire [(3-1):0] I_CTI_O;
output I_LOCK_O;
wire I_LOCK_O;
-output [ (2-1):0] I_BTE_O;
-wire [ (2-1):0] I_BTE_O;
-
+output [(2-1):0] I_BTE_O;
+wire [(2-1):0] I_BTE_O;
-output [ (32-1):0] D_DAT_O;
-wire [ (32-1):0] D_DAT_O;
-output [ (32-1):0] D_ADR_O;
-wire [ (32-1):0] D_ADR_O;
+output [(32-1):0] D_DAT_O;
+wire [(32-1):0] D_DAT_O;
+output [(32-1):0] D_ADR_O;
+wire [(32-1):0] D_ADR_O;
output D_CYC_O;
wire D_CYC_O;
-output [ (4-1):0] D_SEL_O;
-wire [ (4-1):0] D_SEL_O;
+output [(4-1):0] D_SEL_O;
+wire [(4-1):0] D_SEL_O;
output D_STB_O;
wire D_STB_O;
output D_WE_O;
wire D_WE_O;
-output [ (3-1):0] D_CTI_O;
-wire [ (3-1):0] D_CTI_O;
+output [(3-1):0] D_CTI_O;
+wire [(3-1):0] D_CTI_O;
output D_LOCK_O;
wire D_LOCK_O;
-output [ (2-1):0] D_BTE_O;
-wire [ (2-1):0] D_BTE_O;
+output [(2-1):0] D_BTE_O;
+wire [(2-1):0] D_BTE_O;
@@ -52794,10 +47997,8 @@ wire [ (2-1):0] D_BTE_O;
-
-
-reg valid_a;
+reg valid_a;
reg valid_f;
reg valid_d;
@@ -52806,7 +48007,7 @@ reg valid_m;
reg valid_w;
wire q_x;
-wire [ (32-1):0] immediate_d;
+wire [(32-1):0] immediate_d;
wire load_d;
reg load_x;
reg load_m;
@@ -52815,13 +48016,13 @@ wire store_q_x;
wire store_d;
reg store_x;
reg store_m;
-wire [ 1:0] size_d;
-reg [ 1:0] size_x;
+wire [1:0] size_d;
+reg [1:0] size_x;
wire branch_d;
wire branch_predict_d;
wire branch_predict_taken_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
wire bi_unconditional;
wire bi_conditional;
reg branch_x;
@@ -52833,60 +48034,51 @@ reg branch_predict_taken_m;
wire branch_mispredict_taken_m;
wire branch_flushX_m;
wire branch_reg_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
-wire [ 0:0] d_result_sel_0_d;
-wire [ 1:0] d_result_sel_1_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [0:0] d_result_sel_0_d;
+wire [1:0] d_result_sel_1_d;
wire x_result_sel_csr_d;
reg x_result_sel_csr_x;
-
+
-
-
+
-
-
-
+
wire x_result_sel_sext_d;
reg x_result_sel_sext_x;
-
wire x_result_sel_logic_d;
reg x_result_sel_logic_x;
-
+
-
wire x_result_sel_add_d;
reg x_result_sel_add_x;
wire m_result_sel_compare_d;
reg m_result_sel_compare_x;
reg m_result_sel_compare_m;
-
-
+
wire m_result_sel_shift_d;
reg m_result_sel_shift_x;
reg m_result_sel_shift_m;
-
wire w_result_sel_load_d;
reg w_result_sel_load_x;
reg w_result_sel_load_m;
reg w_result_sel_load_w;
-
-
+
wire w_result_sel_mul_d;
reg w_result_sel_mul_x;
reg w_result_sel_mul_m;
reg w_result_sel_mul_w;
-
wire x_bypass_enable_d;
reg x_bypass_enable_x;
@@ -52903,33 +48095,31 @@ wire write_enable_q_m;
reg write_enable_w;
wire write_enable_q_w;
wire read_enable_0_d;
-wire [ (5-1):0] read_idx_0_d;
+wire [(5-1):0] read_idx_0_d;
wire read_enable_1_d;
-wire [ (5-1):0] read_idx_1_d;
-wire [ (5-1):0] write_idx_d;
-reg [ (5-1):0] write_idx_x;
-reg [ (5-1):0] write_idx_m;
-reg [ (5-1):0] write_idx_w;
-wire [ (3-1):0] csr_d;
-reg [ (3-1):0] csr_x;
-wire [ (3-1):0] condition_d;
-reg [ (3-1):0] condition_x;
-
+wire [(5-1):0] read_idx_1_d;
+wire [(5-1):0] write_idx_d;
+reg [(5-1):0] write_idx_x;
+reg [(5-1):0] write_idx_m;
+reg [(5-1):0] write_idx_w;
+wire [(3-1):0] csr_d;
+reg [(3-1):0] csr_x;
+wire [(3-1):0] condition_d;
+reg [(3-1):0] condition_x;
+
-
wire scall_d;
reg scall_x;
wire eret_d;
reg eret_x;
wire eret_q_x;
reg eret_m;
-
+
-
-
+
@@ -52938,55 +48128,48 @@ reg eret_m;
-
wire csr_write_enable_d;
reg csr_write_enable_x;
wire csr_write_enable_q_x;
-
+
-
-
+
+reg [(32-1):0] d_result_0;
+reg [(32-1):0] d_result_1;
+reg [(32-1):0] x_result;
+reg [(32-1):0] m_result;
+reg [(32-1):0] w_result;
-reg [ (32-1):0] d_result_0;
-reg [ (32-1):0] d_result_1;
-reg [ (32-1):0] x_result;
-reg [ (32-1):0] m_result;
-reg [ (32-1):0] w_result;
-
-reg [ (32-1):0] operand_0_x;
-reg [ (32-1):0] operand_1_x;
-reg [ (32-1):0] store_operand_x;
-reg [ (32-1):0] operand_m;
-reg [ (32-1):0] operand_w;
+reg [(32-1):0] operand_0_x;
+reg [(32-1):0] operand_1_x;
+reg [(32-1):0] store_operand_x;
+reg [(32-1):0] operand_m;
+reg [(32-1):0] operand_w;
-
-
-reg [ (32-1):0] reg_data_live_0;
-reg [ (32-1):0] reg_data_live_1;
-reg use_buf;
-reg [ (32-1):0] reg_data_buf_0;
-reg [ (32-1):0] reg_data_buf_1;
-
-
+reg [(32-1):0] reg_data_live_0;
+reg [(32-1):0] reg_data_live_1;
+reg use_buf;
+reg [(32-1):0] reg_data_buf_0;
+reg [(32-1):0] reg_data_buf_1;
-
+
-wire [ (32-1):0] reg_data_0;
-wire [ (32-1):0] reg_data_1;
-reg [ (32-1):0] bypass_data_0;
-reg [ (32-1):0] bypass_data_1;
+wire [(32-1):0] reg_data_0;
+wire [(32-1):0] reg_data_1;
+reg [(32-1):0] bypass_data_0;
+reg [(32-1):0] bypass_data_1;
wire reg_write_enable_q_w;
reg interlock;
@@ -53001,64 +48184,54 @@ wire stall_m;
wire adder_op_d;
reg adder_op_x;
reg adder_op_x_n;
-wire [ (32-1):0] adder_result_x;
+wire [(32-1):0] adder_result_x;
wire adder_overflow_x;
wire adder_carry_n_x;
-wire [ 3:0] logic_op_d;
-reg [ 3:0] logic_op_x;
-wire [ (32-1):0] logic_result_x;
+wire [3:0] logic_op_d;
+reg [3:0] logic_op_x;
+wire [(32-1):0] logic_result_x;
-
-
-
-wire [ (32-1):0] sextb_result_x;
-wire [ (32-1):0] sexth_result_x;
-wire [ (32-1):0] sext_result_x;
+wire [(32-1):0] sextb_result_x;
+wire [(32-1):0] sexth_result_x;
+wire [(32-1):0] sext_result_x;
-
-
+
+
-
wire direction_d;
reg direction_x;
reg direction_m;
-wire [ (32-1):0] shifter_result_m;
-
+wire [(32-1):0] shifter_result_m;
-
+
-
-
+
-
-
-
-wire [ (32-1):0] multiplier_result_w;
+wire [(32-1):0] multiplier_result_w;
-
+
-
-
+
@@ -53067,55 +48240,45 @@ wire [ (32-1):0] multiplier_result_w;
-
-
+
-
-
-
-wire [ (32-1):0] interrupt_csr_read_data_x;
+wire [(32-1):0] interrupt_csr_read_data_x;
-wire [ (32-1):0] cfg;
-wire [ (32-1):0] cfg2;
-
+wire [(32-1):0] cfg;
+wire [(32-1):0] cfg2;
+
-
-reg [ (32-1):0] csr_read_data_x;
+reg [(32-1):0] csr_read_data_x;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
-
-
-
-wire [ (32-1):0] instruction_f;
+wire [(32-1):0] instruction_f;
-wire [ (32-1):0] instruction_d;
-
-
+wire [(32-1):0] instruction_d;
+
wire iflush;
wire icache_stall_request;
wire icache_restart_request;
wire icache_refill_request;
wire icache_refilling;
-
-
+
@@ -53124,8 +48287,7 @@ wire icache_refilling;
-
-
+
@@ -53133,12 +48295,11 @@ wire icache_refilling;
-
-wire [ (32-1):0] load_data_w;
+wire [(32-1):0] load_data_w;
wire stall_wb_load;
-
+
@@ -53158,7 +48319,6 @@ wire stall_wb_load;
-
wire raw_x_0;
@@ -53175,10 +48335,9 @@ wire cmp_overflow;
wire cmp_carry_n;
reg condition_met_x;
reg condition_met_m;
-
+
-
wire branch_taken_m;
wire kill_f;
@@ -53187,19 +48346,17 @@ wire kill_x;
wire kill_m;
wire kill_w;
-reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
-
+reg [(clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
+
-
-reg [ (3-1):0] eid_x;
-
+reg [(3-1):0] eid_x;
+
-
-
+
@@ -53214,43 +48371,35 @@ reg [ (3-1):0] eid_x;
-
wire exception_x;
reg exception_m;
reg exception_w;
wire exception_q_w;
-
-
+
-
-
-
-wire interrupt_exception;
+wire interrupt_exception;
-
+
-
-
+
-
-
+
-
wire system_call_exception;
-
+
@@ -53258,10 +48407,7 @@ wire system_call_exception;
-
-
-
-
+
@@ -53317,7 +48463,6 @@ endfunction
-
lm32_instruction_unit_medium_icache #(
.associativity (icache_associativity),
.sets (icache_sets),
@@ -53339,48 +48484,40 @@ lm32_instruction_unit_medium_icache #(
.kill_f (kill_f),
.branch_predict_taken_d (branch_predict_taken_d),
.branch_predict_address_d (branch_predict_address_d),
-
+
-
.exception_m (exception_m),
.branch_taken_m (branch_taken_m),
.branch_mispredict_taken_m (branch_mispredict_taken_m),
.branch_target_m (branch_target_m),
-
-
- .iflush (iflush),
+ .iflush (iflush),
-
+
-
-
+
-
-
-
+
.i_dat_i (I_DAT_I),
.i_ack_i (I_ACK_I),
.i_err_i (I_ERR_I),
.i_rty_i (I_RTY_I),
-
-
+
-
.pc_f (pc_f),
@@ -53388,20 +48525,16 @@ lm32_instruction_unit_medium_icache #(
.pc_x (pc_x),
.pc_m (pc_m),
.pc_w (pc_w),
-
-
+
.icache_stall_request (icache_stall_request),
.icache_restart_request (icache_restart_request),
.icache_refill_request (icache_refill_request),
.icache_refilling (icache_refilling),
-
-
+
-
-
-
+
.i_dat_o (I_DAT_O),
.i_adr_o (I_ADR_O),
@@ -53412,21 +48545,16 @@ lm32_instruction_unit_medium_icache #(
.i_cti_o (I_CTI_O),
.i_lock_o (I_LOCK_O),
.i_bte_o (I_BTE_O),
-
-
+
-
-
+
-
-
-
- .instruction_f (instruction_f),
+ .instruction_f (instruction_f),
.instruction_d (instruction_d)
);
@@ -53439,36 +48567,27 @@ lm32_decoder_medium_icache decoder (
.d_result_sel_0 (d_result_sel_0_d),
.d_result_sel_1 (d_result_sel_1_d),
.x_result_sel_csr (x_result_sel_csr_d),
-
+
-
-
+
-
-
-
- .x_result_sel_sext (x_result_sel_sext_d),
+ .x_result_sel_sext (x_result_sel_sext_d),
.x_result_sel_logic (x_result_sel_logic_d),
-
+
-
.x_result_sel_add (x_result_sel_add_d),
.m_result_sel_compare (m_result_sel_compare_d),
-
-
- .m_result_sel_shift (m_result_sel_shift_d),
+ .m_result_sel_shift (m_result_sel_shift_d),
.w_result_sel_load (w_result_sel_load_d),
-
-
- .w_result_sel_mul (w_result_sel_mul_d),
+ .w_result_sel_mul (w_result_sel_mul_d),
.x_bypass_enable (x_bypass_enable_d),
.m_bypass_enable (m_bypass_enable_d),
@@ -53486,44 +48605,36 @@ lm32_decoder_medium_icache decoder (
.sign_extend (sign_extend_d),
.adder_op (adder_op_d),
.logic_op (logic_op_d),
-
-
- .direction (direction_d),
+ .direction (direction_d),
-
+
-
-
+
-
-
+
-
.branch (branch_d),
.bi_unconditional (bi_unconditional),
.bi_conditional (bi_conditional),
.branch_reg (branch_reg_d),
.condition (condition_d),
-
+
-
.scall (scall_d),
.eret (eret_d),
-
+
-
-
+
-
.csr_write_enable (csr_write_enable_d)
);
@@ -53557,14 +48668,12 @@ lm32_load_store_unit_medium_icache #(
.store_q_m (store_q_m),
.sign_extend_x (sign_extend_x),
.size_x (size_x),
-
+
-
-
+
-
.d_dat_i (D_DAT_I),
.d_ack_i (D_ACK_I),
@@ -53572,20 +48681,18 @@ lm32_load_store_unit_medium_icache #(
.d_rty_i (D_RTY_I),
-
+
-
-
+
-
.load_data_w (load_data_w),
.stall_wb_load (stall_wb_load),
@@ -53624,8 +48731,7 @@ lm32_logic_op logic_op (
.logic_result_x (logic_result_x)
);
-
-
+
lm32_shifter shifter (
@@ -53639,11 +48745,9 @@ lm32_shifter shifter (
.shifter_result_m (shifter_result_m)
);
-
-
-
+
lm32_multiplier multiplier (
@@ -53656,10 +48760,9 @@ lm32_multiplier multiplier (
.result (multiplier_result_w)
);
-
-
+
@@ -53688,11 +48791,9 @@ lm32_multiplier multiplier (
-
-
-
+
lm32_interrupt_medium_icache interrupt_unit (
@@ -53702,19 +48803,16 @@ lm32_interrupt_medium_icache interrupt_unit (
.interrupt (interrupt),
.stall_x (stall_x),
-
+
-
.exception (exception_q_w),
-
.eret_q_x (eret_q_x),
-
+
-
.csr (csr_x),
.csr_write_data (operand_1_x),
.csr_write_enable (csr_write_enable_q_x),
@@ -53723,10 +48821,9 @@ lm32_interrupt_medium_icache interrupt_unit (
.csr_read_data (interrupt_csr_read_data_x)
);
-
-
+
@@ -53776,8 +48873,7 @@ lm32_interrupt_medium_icache interrupt_unit (
-
-
+
@@ -53820,9 +48916,7 @@ lm32_interrupt_medium_icache interrupt_unit (
-
-
-
+
@@ -53883,8 +48977,8 @@ lm32_interrupt_medium_icache interrupt_unit (
- always @(posedge clk_i )
- if (rst_i == 1'b1)
+ always @(posedge clk_i )
+ if (rst_i == 1'b1)
begin
regfile_raw_0 <= 1'b0;
regfile_raw_1 <= 1'b0;
@@ -53939,10 +49033,9 @@ lm32_interrupt_medium_icache interrupt_unit (
.rdata_o (regfile_data_1)
);
-
-
+
@@ -54015,58 +49108,53 @@ lm32_interrupt_medium_icache interrupt_unit (
-
-
-
+
assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
-
-
-
+
-
-assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == 1'b1);
-assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == 1'b1);
-assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == 1'b1);
-assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == 1'b1);
-assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == 1'b1);
-assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == 1'b1);
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == 1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == 1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == 1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == 1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == 1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == 1'b1);
always @(*)
begin
- if ( ( (x_bypass_enable_x == 1'b0)
- && ( ((read_enable_0_d == 1'b1) && (raw_x_0 == 1'b1))
- || ((read_enable_1_d == 1'b1) && (raw_x_1 == 1'b1))
+ if ( ( (x_bypass_enable_x == 1'b0)
+ && ( ((read_enable_0_d == 1'b1) && (raw_x_0 == 1'b1))
+ || ((read_enable_1_d == 1'b1) && (raw_x_1 == 1'b1))
)
)
- || ( (m_bypass_enable_m == 1'b0)
- && ( ((read_enable_0_d == 1'b1) && (raw_m_0 == 1'b1))
- || ((read_enable_1_d == 1'b1) && (raw_m_1 == 1'b1))
+ || ( (m_bypass_enable_m == 1'b0)
+ && ( ((read_enable_0_d == 1'b1) && (raw_m_0 == 1'b1))
+ || ((read_enable_1_d == 1'b1) && (raw_m_1 == 1'b1))
)
)
)
- interlock = 1'b1;
+ interlock = 1'b1;
else
- interlock = 1'b0;
+ interlock = 1'b0;
end
always @(*)
begin
- if (raw_x_0 == 1'b1)
+ if (raw_x_0 == 1'b1)
bypass_data_0 = x_result;
- else if (raw_m_0 == 1'b1)
+ else if (raw_m_0 == 1'b1)
bypass_data_0 = m_result;
- else if (raw_w_0 == 1'b1)
+ else if (raw_w_0 == 1'b1)
bypass_data_0 = w_result;
else
bypass_data_0 = reg_data_0;
@@ -54075,11 +49163,11 @@ end
always @(*)
begin
- if (raw_x_1 == 1'b1)
+ if (raw_x_1 == 1'b1)
bypass_data_1 = x_result;
- else if (raw_m_1 == 1'b1)
+ else if (raw_m_1 == 1'b1)
bypass_data_1 = m_result;
- else if (raw_w_1 == 1'b1)
+ else if (raw_w_1 == 1'b1)
bypass_data_1 = w_result;
else
bypass_data_1 = reg_data_1;
@@ -54107,51 +49195,47 @@ always @(*)
begin
d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
case (d_result_sel_1_d)
- 2'b00: d_result_1 = { 32{1'b0}};
- 2'b01: d_result_1 = bypass_data_1;
- 2'b10: d_result_1 = immediate_d;
- default: d_result_1 = { 32{1'bx}};
+ 2'b00: d_result_1 = {32{1'b0}};
+ 2'b01: d_result_1 = bypass_data_1;
+ 2'b10: d_result_1 = immediate_d;
+ default: d_result_1 = {32{1'bx}};
endcase
end
-
+
-
-
-
+
assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
-assign sext_result_x = size_x == 2'b00 ? sextb_result_x : sexth_result_x;
-
+assign sext_result_x = size_x == 2'b00 ? sextb_result_x : sexth_result_x;
-
+
-
assign cmp_zero = operand_0_x == operand_1_x;
-assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_negative = adder_result_x[32-1];
assign cmp_overflow = adder_overflow_x;
assign cmp_carry_n = adder_carry_n_x;
always @(*)
begin
case (condition_x)
- 3'b000: condition_met_x = 1'b1;
- 3'b110: condition_met_x = 1'b1;
- 3'b001: condition_met_x = cmp_zero;
- 3'b111: condition_met_x = !cmp_zero;
- 3'b010: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
- 3'b101: condition_met_x = cmp_carry_n && !cmp_zero;
- 3'b011: condition_met_x = cmp_negative == cmp_overflow;
- 3'b100: condition_met_x = cmp_carry_n;
+ 3'b000: condition_met_x = 1'b1;
+ 3'b110: condition_met_x = 1'b1;
+ 3'b001: condition_met_x = cmp_zero;
+ 3'b111: condition_met_x = !cmp_zero;
+ 3'b010: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+ 3'b101: condition_met_x = cmp_carry_n && !cmp_zero;
+ 3'b011: condition_met_x = cmp_negative == cmp_overflow;
+ 3'b100: condition_met_x = cmp_carry_n;
default: condition_met_x = 1'bx;
endcase
end
@@ -54161,34 +49245,27 @@ always @(*)
begin
x_result = x_result_sel_add_x ? adder_result_x
: x_result_sel_csr_x ? csr_read_data_x
-
-
- : x_result_sel_sext_x ? sext_result_x
+ : x_result_sel_sext_x ? sext_result_x
-
+
-
-
+
-
-
+
-
: logic_result_x;
end
always @(*)
begin
- m_result = m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
-
-
- : m_result_sel_shift_m ? shifter_result_m
+ m_result = m_result_sel_compare_m ? {{32-1{1'b0}}, condition_met_m}
+ : m_result_sel_shift_m ? shifter_result_m
: operand_m;
end
@@ -54197,15 +49274,13 @@ end
always @(*)
begin
w_result = w_result_sel_load_w ? load_data_w
-
-
- : w_result_sel_mul_w ? multiplier_result_w
+ : w_result_sel_mul_w ? multiplier_result_w
: operand_w;
end
-
+
@@ -54216,97 +49291,85 @@ end
-
-assign branch_taken_m = (stall_m == 1'b0)
- && ( ( (branch_m == 1'b1)
- && (valid_m == 1'b1)
- && ( ( (condition_met_m == 1'b1)
- && (branch_predict_taken_m == 1'b0)
+assign branch_taken_m = (stall_m == 1'b0)
+ && ( ( (branch_m == 1'b1)
+ && (valid_m == 1'b1)
+ && ( ( (condition_met_m == 1'b1)
+ && (branch_predict_taken_m == 1'b0)
)
- || ( (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1)
+ || ( (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1)
)
)
)
- || (exception_m == 1'b1)
+ || (exception_m == 1'b1)
);
-assign branch_mispredict_taken_m = (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1);
+assign branch_mispredict_taken_m = (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1);
-assign branch_flushX_m = (stall_m == 1'b0)
- && ( ( (branch_m == 1'b1)
- && (valid_m == 1'b1)
- && ( (condition_met_m == 1'b1)
- || ( (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1)
+assign branch_flushX_m = (stall_m == 1'b0)
+ && ( ( (branch_m == 1'b1)
+ && (valid_m == 1'b1)
+ && ( (condition_met_m == 1'b1)
+ || ( (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1)
)
)
)
- || (exception_m == 1'b1)
+ || (exception_m == 1'b1)
);
-assign kill_f = ( (valid_d == 1'b1)
- && (branch_predict_taken_d == 1'b1)
+assign kill_f = ( (valid_d == 1'b1)
+ && (branch_predict_taken_d == 1'b1)
)
- || (branch_taken_m == 1'b1)
-
+ || (branch_taken_m == 1'b1)
+
-
-
-
- || (icache_refill_request == 1'b1)
+ || (icache_refill_request == 1'b1)
-
+
-
;
-assign kill_d = (branch_taken_m == 1'b1)
-
+assign kill_d = (branch_taken_m == 1'b1)
+
-
-
-
- || (icache_refill_request == 1'b1)
+ || (icache_refill_request == 1'b1)
-
+
-
;
-assign kill_x = (branch_flushX_m == 1'b1)
-
+assign kill_x = (branch_flushX_m == 1'b1)
+
-
;
-assign kill_m = 1'b0
-
+assign kill_m = 1'b0
+
-
;
-assign kill_w = 1'b0
-
+assign kill_w = 1'b0
+
-
;
-
+
@@ -54318,33 +49381,28 @@ assign kill_w = 1'b0
-
-
+
-
-
+
-
-
+
-
-assign system_call_exception = ( (scall_x == 1'b1)
-
+assign system_call_exception = ( (scall_x == 1'b1)
+
-
);
-
+
@@ -54375,40 +49433,32 @@ assign system_call_exception = ( (scall_x == 1'b1)
-
-assign exception_x = (system_call_exception == 1'b1)
-
+assign exception_x = (system_call_exception == 1'b1)
+
-
-
+
-
-
-
- || ( (interrupt_exception == 1'b1)
-
+
+ || ( (interrupt_exception == 1'b1)
+
-
-
+
-
)
-
;
-
always @(*)
begin
-
+
@@ -54423,8 +49473,7 @@ begin
-
-
+
@@ -54432,60 +49481,53 @@ begin
-
-
+
-
-
+
-
-
-
- if ( (interrupt_exception == 1'b1)
-
+
+ if ( (interrupt_exception == 1'b1)
+
-
)
- eid_x = 3'h6;
+ eid_x = 3'h6;
else
-
- eid_x = 3'h7;
+ eid_x = 3'h7;
end
-assign stall_a = (stall_f == 1'b1);
+assign stall_a = (stall_f == 1'b1);
-assign stall_f = (stall_d == 1'b1);
+assign stall_f = (stall_d == 1'b1);
-assign stall_d = (stall_x == 1'b1)
- || ( (interlock == 1'b1)
- && (kill_d == 1'b0)
+assign stall_d = (stall_x == 1'b1)
+ || ( (interlock == 1'b1)
+ && (kill_d == 1'b0)
)
- || ( ( (eret_d == 1'b1)
- || (scall_d == 1'b1)
-
+ || ( ( (eret_d == 1'b1)
+ || (scall_d == 1'b1)
+
-
)
- && ( (load_q_x == 1'b1)
- || (load_q_m == 1'b1)
- || (store_q_x == 1'b1)
- || (store_q_m == 1'b1)
- || (D_CYC_O == 1'b1)
+ && ( (load_q_x == 1'b1)
+ || (load_q_m == 1'b1)
+ || (store_q_x == 1'b1)
+ || (store_q_m == 1'b1)
+ || (D_CYC_O == 1'b1)
)
- && (kill_d == 1'b0)
+ && (kill_d == 1'b0)
)
-
+
@@ -54497,21 +49539,19 @@ assign stall_d = (stall_x == 1'b1)
-
- || ( (csr_write_enable_d == 1'b1)
- && (load_q_x == 1'b1)
+ || ( (csr_write_enable_d == 1'b1)
+ && (load_q_x == 1'b1)
)
;
-assign stall_x = (stall_m == 1'b1)
-
+assign stall_x = (stall_m == 1'b1)
+
-
-
+
@@ -54520,16 +49560,14 @@ assign stall_x = (stall_m == 1'b1)
-
;
-assign stall_m = (stall_wb_load == 1'b1)
-
+assign stall_m = (stall_wb_load == 1'b1)
+
-
- || ( (D_CYC_O == 1'b1)
- && ( (store_m == 1'b1)
+ || ( (D_CYC_O == 1'b1)
+ && ( (store_m == 1'b1)
@@ -54543,230 +49581,182 @@ assign stall_m = (stall_wb_load == 1'b1)
-
-
- || ((store_x == 1'b1) && (interrupt_exception == 1'b1))
+ || ((store_x == 1'b1) && (interrupt_exception == 1'b1))
- || (load_m == 1'b1)
- || (load_x == 1'b1)
+ || (load_m == 1'b1)
+ || (load_x == 1'b1)
)
)
-
-
+
-
-
-
- || (icache_stall_request == 1'b1)
- || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1)))
+ || (icache_stall_request == 1'b1)
+ || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1)))
+
-
-
+
-
;
-
+
-
-
+
-
-
+
-
-
+
-
-assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
-assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
-assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
-
+assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
+assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
+
-
-assign load_q_x = (load_x == 1'b1)
- && (q_x == 1'b1)
-
+assign load_q_x = (load_x == 1'b1)
+ && (q_x == 1'b1)
+
-
;
-assign store_q_x = (store_x == 1'b1)
- && (q_x == 1'b1)
-
+assign store_q_x = (store_x == 1'b1)
+ && (q_x == 1'b1)
+
-
;
-
+
-
-assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
-assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
-assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
+assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
+assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
+assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
+
-
-assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1));
-
+assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1));
-assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
-assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
-assign write_enable_q_w = (write_enable_w == 1'b1) && (valid_w == 1'b1);
+assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
+assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
+assign write_enable_q_w = (write_enable_w == 1'b1) && (valid_w == 1'b1);
-assign reg_write_enable_q_w = (write_enable_w == 1'b1) && (kill_w == 1'b0) && (valid_w == 1'b1);
+assign reg_write_enable_q_w = (write_enable_w == 1'b1) && (kill_w == 1'b0) && (valid_w == 1'b1);
assign cfg = {
- 6'h02,
+ 6'h02,
watchpoints[3:0],
breakpoints[3:0],
interrupts[5:0],
-
+
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
+ 1'b1,
-
+
- 1'b1,
+ 1'b0,
-
+
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
+ 1'b1,
-
-
- 1'b0,
+ 1'b1,
-
-
- 1'b1,
-
-
-
-
- 1'b1,
+ 1'b0,
-
-
+ 1'b1
- 1'b0,
-
-
-
-
- 1'b1
-
-
};
assign cfg2 = {
30'b0,
-
+
+ 1'b0,
- 1'b0,
-
-
-
- 1'b0
-
+ 1'b0
};
-
-
-assign iflush = ( (csr_write_enable_d == 1'b1)
- && (csr_d == 3'h3)
- && (stall_d == 1'b0)
- && (kill_d == 1'b0)
- && (valid_d == 1'b1))
+
+assign iflush = ( (csr_write_enable_d == 1'b1)
+ && (csr_d == 3'h3)
+ && (stall_d == 1'b0)
+ && (kill_d == 1'b0)
+ && (valid_d == 1'b1))
-
+
-
;
-
@@ -54776,41 +49766,35 @@ assign iflush = ( (csr_write_enable_d == 1'b1)
-
-assign csr_d = read_idx_0_d[ (3-1):0];
+assign csr_d = read_idx_0_d[(3-1):0];
always @(*)
begin
case (csr_x)
-
-
- 3'h0,
- 3'h1,
- 3'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 3'h0,
+ 3'h1,
+ 3'h2: csr_read_data_x = interrupt_csr_read_data_x;
-
+
-
- 3'h6: csr_read_data_x = cfg;
- 3'h7: csr_read_data_x = {eba, 8'h00};
-
+ 3'h6: csr_read_data_x = cfg;
+ 3'h7: csr_read_data_x = {eba, 8'h00};
+
-
-
+
-
- 3'ha: csr_read_data_x = cfg2;
+ 3'ha: csr_read_data_x = cfg2;
- default: csr_read_data_x = { 32{1'bx}};
+ default: csr_read_data_x = {32{1'bx}};
endcase
end
@@ -54819,23 +49803,22 @@ end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if (rst_i == 1'b1)
+ eba <= eba_reset[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 3'h7) && (stall_x == 1'b0))
- eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 3'h7) && (stall_x == 1'b0))
+ eba <= operand_1_x[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+
-
end
end
-
+
@@ -54854,8 +49837,7 @@ end
-
-
+
@@ -54865,8 +49847,7 @@ end
-
-
+
@@ -54883,13 +49864,11 @@ end
-
-
-
-
+
+
@@ -54903,20 +49882,18 @@ end
-
always @(*)
begin
- if (icache_refill_request == 1'b1)
- valid_a = 1'b0;
- else if (icache_restart_request == 1'b1)
- valid_a = 1'b1;
+ if (icache_refill_request == 1'b1)
+ valid_a = 1'b0;
+ else if (icache_restart_request == 1'b1)
+ valid_a = 1'b1;
else
valid_a = !icache_refilling;
end
-
-
+
@@ -54930,250 +49907,208 @@ end
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- valid_f <= 1'b0;
- valid_d <= 1'b0;
- valid_x <= 1'b0;
- valid_m <= 1'b0;
- valid_w <= 1'b0;
+ valid_f <= 1'b0;
+ valid_d <= 1'b0;
+ valid_x <= 1'b0;
+ valid_m <= 1'b0;
+ valid_w <= 1'b0;
end
else
begin
- if ((kill_f == 1'b1) || (stall_a == 1'b0))
-
-
- valid_f <= valid_a;
+ if ((kill_f == 1'b1) || (stall_a == 1'b0))
-
+ valid_f <= valid_a;
+
- else if (stall_f == 1'b0)
- valid_f <= 1'b0;
+ else if (stall_f == 1'b0)
+ valid_f <= 1'b0;
- if (kill_d == 1'b1)
- valid_d <= 1'b0;
- else if (stall_f == 1'b0)
+ if (kill_d == 1'b1)
+ valid_d <= 1'b0;
+ else if (stall_f == 1'b0)
valid_d <= valid_f & !kill_f;
- else if (stall_d == 1'b0)
- valid_d <= 1'b0;
+ else if (stall_d == 1'b0)
+ valid_d <= 1'b0;
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
valid_x <= valid_d & !kill_d;
- else if (kill_x == 1'b1)
- valid_x <= 1'b0;
- else if (stall_x == 1'b0)
- valid_x <= 1'b0;
-
- if (kill_m == 1'b1)
- valid_m <= 1'b0;
- else if (stall_x == 1'b0)
+ else if (kill_x == 1'b1)
+ valid_x <= 1'b0;
+ else if (stall_x == 1'b0)
+ valid_x <= 1'b0;
+
+ if (kill_m == 1'b1)
+ valid_m <= 1'b0;
+ else if (stall_x == 1'b0)
valid_m <= valid_x & !kill_x;
- else if (stall_m == 1'b0)
- valid_m <= 1'b0;
+ else if (stall_m == 1'b0)
+ valid_m <= 1'b0;
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
valid_w <= valid_m & !kill_m;
else
- valid_w <= 1'b0;
+ valid_w <= 1'b0;
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
-
+
-
- operand_0_x <= { 32{1'b0}};
- operand_1_x <= { 32{1'b0}};
- store_operand_x <= { 32{1'b0}};
- branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- x_result_sel_csr_x <= 1'b0;
-
+ operand_0_x <= {32{1'b0}};
+ operand_1_x <= {32{1'b0}};
+ store_operand_x <= {32{1'b0}};
+ branch_target_x <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ x_result_sel_csr_x <= 1'b0;
+
-
-
+
-
-
-
- x_result_sel_sext_x <= 1'b0;
+ x_result_sel_sext_x <= 1'b0;
- x_result_sel_logic_x <= 1'b0;
-
+ x_result_sel_logic_x <= 1'b0;
+
-
- x_result_sel_add_x <= 1'b0;
- m_result_sel_compare_x <= 1'b0;
-
-
- m_result_sel_shift_x <= 1'b0;
+ x_result_sel_add_x <= 1'b0;
+ m_result_sel_compare_x <= 1'b0;
+ m_result_sel_shift_x <= 1'b0;
- w_result_sel_load_x <= 1'b0;
-
-
- w_result_sel_mul_x <= 1'b0;
+ w_result_sel_load_x <= 1'b0;
+ w_result_sel_mul_x <= 1'b0;
- x_bypass_enable_x <= 1'b0;
- m_bypass_enable_x <= 1'b0;
- write_enable_x <= 1'b0;
- write_idx_x <= { 5{1'b0}};
- csr_x <= { 3{1'b0}};
- load_x <= 1'b0;
- store_x <= 1'b0;
- size_x <= { 2{1'b0}};
- sign_extend_x <= 1'b0;
- adder_op_x <= 1'b0;
- adder_op_x_n <= 1'b0;
+ x_bypass_enable_x <= 1'b0;
+ m_bypass_enable_x <= 1'b0;
+ write_enable_x <= 1'b0;
+ write_idx_x <= {5{1'b0}};
+ csr_x <= {3{1'b0}};
+ load_x <= 1'b0;
+ store_x <= 1'b0;
+ size_x <= {2{1'b0}};
+ sign_extend_x <= 1'b0;
+ adder_op_x <= 1'b0;
+ adder_op_x_n <= 1'b0;
logic_op_x <= 4'h0;
-
-
- direction_x <= 1'b0;
+ direction_x <= 1'b0;
-
+
-
- branch_x <= 1'b0;
- branch_predict_x <= 1'b0;
- branch_predict_taken_x <= 1'b0;
- condition_x <= 3'b000;
-
+ branch_x <= 1'b0;
+ branch_predict_x <= 1'b0;
+ branch_predict_taken_x <= 1'b0;
+ condition_x <= 3'b000;
+
-
- scall_x <= 1'b0;
- eret_x <= 1'b0;
-
+ scall_x <= 1'b0;
+ eret_x <= 1'b0;
+
-
-
+
-
- csr_write_enable_x <= 1'b0;
- operand_m <= { 32{1'b0}};
- branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- m_result_sel_compare_m <= 1'b0;
-
-
- m_result_sel_shift_m <= 1'b0;
+ csr_write_enable_x <= 1'b0;
+ operand_m <= {32{1'b0}};
+ branch_target_m <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ m_result_sel_compare_m <= 1'b0;
+ m_result_sel_shift_m <= 1'b0;
- w_result_sel_load_m <= 1'b0;
-
-
- w_result_sel_mul_m <= 1'b0;
+ w_result_sel_load_m <= 1'b0;
+ w_result_sel_mul_m <= 1'b0;
- m_bypass_enable_m <= 1'b0;
- branch_m <= 1'b0;
- branch_predict_m <= 1'b0;
- branch_predict_taken_m <= 1'b0;
- exception_m <= 1'b0;
- load_m <= 1'b0;
- store_m <= 1'b0;
-
-
- direction_m <= 1'b0;
+ m_bypass_enable_m <= 1'b0;
+ branch_m <= 1'b0;
+ branch_predict_m <= 1'b0;
+ branch_predict_taken_m <= 1'b0;
+ exception_m <= 1'b0;
+ load_m <= 1'b0;
+ store_m <= 1'b0;
+ direction_m <= 1'b0;
- write_enable_m <= 1'b0;
- write_idx_m <= { 5{1'b0}};
- condition_met_m <= 1'b0;
-
+ write_enable_m <= 1'b0;
+ write_idx_m <= {5{1'b0}};
+ condition_met_m <= 1'b0;
+
-
-
+
-
- operand_w <= { 32{1'b0}};
- w_result_sel_load_w <= 1'b0;
-
-
- w_result_sel_mul_w <= 1'b0;
+ operand_w <= {32{1'b0}};
+ w_result_sel_load_w <= 1'b0;
+ w_result_sel_mul_w <= 1'b0;
- write_idx_w <= { 5{1'b0}};
- write_enable_w <= 1'b0;
-
+ write_idx_w <= {5{1'b0}};
+ write_enable_w <= 1'b0;
+
+ exception_w <= 1'b0;
- exception_w <= 1'b0;
-
-
-
end
else
begin
- if (stall_x == 1'b0)
+ if (stall_x == 1'b0)
begin
-
+
-
operand_0_x <= d_result_0;
operand_1_x <= d_result_1;
store_operand_x <= bypass_data_1;
- branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;
+ branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;
x_result_sel_csr_x <= x_result_sel_csr_d;
-
+
-
-
+
-
-
-
- x_result_sel_sext_x <= x_result_sel_sext_d;
+ x_result_sel_sext_x <= x_result_sel_sext_d;
x_result_sel_logic_x <= x_result_sel_logic_d;
-
+
-
x_result_sel_add_x <= x_result_sel_add_d;
m_result_sel_compare_x <= m_result_sel_compare_d;
-
-
- m_result_sel_shift_x <= m_result_sel_shift_d;
+ m_result_sel_shift_x <= m_result_sel_shift_d;
w_result_sel_load_x <= w_result_sel_load_d;
-
-
- w_result_sel_mul_x <= w_result_sel_mul_d;
+ w_result_sel_mul_x <= w_result_sel_mul_d;
x_bypass_enable_x <= x_bypass_enable_d;
m_bypass_enable_x <= m_bypass_enable_d;
@@ -55189,81 +50124,65 @@ begin
adder_op_x <= adder_op_d;
adder_op_x_n <= ~adder_op_d;
logic_op_x <= logic_op_d;
-
-
- direction_x <= direction_d;
+ direction_x <= direction_d;
-
+
-
condition_x <= condition_d;
csr_write_enable_x <= csr_write_enable_d;
-
+
-
scall_x <= scall_d;
-
+
-
eret_x <= eret_d;
-
+
-
write_enable_x <= write_enable_d;
end
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
operand_m <= x_result;
m_result_sel_compare_m <= m_result_sel_compare_x;
-
-
- m_result_sel_shift_m <= m_result_sel_shift_x;
+ m_result_sel_shift_m <= m_result_sel_shift_x;
- if (exception_x == 1'b1)
+ if (exception_x == 1'b1)
begin
- w_result_sel_load_m <= 1'b0;
-
-
- w_result_sel_mul_m <= 1'b0;
+ w_result_sel_load_m <= 1'b0;
+ w_result_sel_mul_m <= 1'b0;
end
else
begin
w_result_sel_load_m <= w_result_sel_load_x;
-
-
- w_result_sel_mul_m <= w_result_sel_mul_x;
+ w_result_sel_mul_m <= w_result_sel_mul_x;
end
m_bypass_enable_m <= m_bypass_enable_x;
-
-
- direction_m <= direction_x;
+ direction_m <= direction_x;
load_m <= load_x;
store_m <= store_x;
-
+
-
branch_m <= branch_x;
branch_predict_m <= branch_predict_x;
branch_predict_taken_m <= branch_predict_taken_x;
-
-
+
@@ -55276,15 +50195,13 @@ begin
-
- if (exception_x == 1'b1)
- write_idx_m <= 5'd30;
+ if (exception_x == 1'b1)
+ write_idx_m <= 5'd30;
else
write_idx_m <= write_idx_x;
-
condition_met_m <= condition_met_x;
-
+
@@ -55295,81 +50212,67 @@ begin
+ branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
- branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
-
-
-
-
+
-
eret_m <= eret_q_x;
-
+
-
- write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
-
+ write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
+
-
end
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
- if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
- exception_m <= 1'b1;
+ if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
+ exception_m <= 1'b1;
else
- exception_m <= 1'b0;
-
+ exception_m <= 1'b0;
+
-
end
-
+
-
- operand_w <= exception_m == 1'b1 ? {pc_m, 2'b00} : m_result;
-
+ operand_w <= exception_m == 1'b1 ? {pc_m, 2'b00} : m_result;
w_result_sel_load_w <= w_result_sel_load_m;
-
-
- w_result_sel_mul_w <= w_result_sel_mul_m;
+ w_result_sel_mul_w <= w_result_sel_mul_m;
write_idx_w <= write_idx_m;
-
+
-
write_enable_w <= write_enable_m;
-
+
-
exception_w <= exception_m;
-
-
+
@@ -55377,33 +50280,31 @@ begin
-
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- use_buf <= 1'b0;
- reg_data_buf_0 <= { 32{1'b0}};
- reg_data_buf_1 <= { 32{1'b0}};
+ use_buf <= 1'b0;
+ reg_data_buf_0 <= {32{1'b0}};
+ reg_data_buf_1 <= {32{1'b0}};
end
else
begin
- if (stall_d == 1'b0)
- use_buf <= 1'b0;
- else if (use_buf == 1'b0)
+ if (stall_d == 1'b0)
+ use_buf <= 1'b0;
+ else if (use_buf == 1'b0)
begin
reg_data_buf_0 <= reg_data_live_0;
reg_data_buf_1 <= reg_data_live_1;
- use_buf <= 1'b1;
+ use_buf <= 1'b1;
end
- if (reg_write_enable_q_w == 1'b1)
+ if (reg_write_enable_q_w == 1'b1)
begin
if (write_idx_w == read_idx_0_d)
reg_data_buf_0 <= w_result;
@@ -55412,13 +50313,11 @@ begin
end
end
end
-
-
-
+
@@ -55462,8 +50361,7 @@ end
-
-
+
@@ -55522,7 +50420,6 @@ end
-
@@ -55535,13 +50432,9 @@ end
initial
begin
-
-
- reg_0.ram[0] = { 32{1'b0}};
- reg_1.ram[0] = { 32{1'b0}};
-
+
end
@@ -55589,10 +50482,7 @@ endmodule
-
-
-
-
+
@@ -55622,9 +50512,9 @@ endmodule
-
+
@@ -55909,8 +50799,6 @@ endmodule
-
-
@@ -55937,14 +50825,12 @@ module lm32_load_store_unit_medium_icache (
store_q_m,
sign_extend_x,
size_x,
-
+
-
-
+
-
d_dat_i,
d_ack_i,
@@ -55952,19 +50838,17 @@ module lm32_load_store_unit_medium_icache (
d_rty_i,
-
+
-
-
+
-
load_data_w,
stall_wb_load,
@@ -56009,9 +50893,9 @@ input kill_x;
input kill_m;
input exception_m;
-input [ (32-1):0] store_operand_x;
-input [ (32-1):0] load_store_address_x;
-input [ (32-1):0] load_store_address_m;
+input [(32-1):0] store_operand_x;
+input [(32-1):0] load_store_address_x;
+input [(32-1):0] load_store_address_m;
input [1:0] load_store_address_w;
input load_x;
input store_x;
@@ -56020,19 +50904,17 @@ input store_q_x;
input load_q_m;
input store_q_m;
input sign_extend_x;
-input [ 1:0] size_x;
+input [1:0] size_x;
-
+
-
-
+
-
-input [ (32-1):0] d_dat_i;
+input [(32-1):0] d_dat_i;
input d_ack_i;
input d_err_i;
input d_rty_i;
@@ -56041,7 +50923,7 @@ input d_rty_i;
-
+
@@ -56052,8 +50934,7 @@ input d_rty_i;
-
-
+
@@ -56062,50 +50943,49 @@ input d_rty_i;
-
-output [ (32-1):0] load_data_w;
-reg [ (32-1):0] load_data_w;
+output [(32-1):0] load_data_w;
+reg [(32-1):0] load_data_w;
output stall_wb_load;
reg stall_wb_load;
-output [ (32-1):0] d_dat_o;
-reg [ (32-1):0] d_dat_o;
-output [ (32-1):0] d_adr_o;
-reg [ (32-1):0] d_adr_o;
+output [(32-1):0] d_dat_o;
+reg [(32-1):0] d_dat_o;
+output [(32-1):0] d_adr_o;
+reg [(32-1):0] d_adr_o;
output d_cyc_o;
reg d_cyc_o;
-output [ (4-1):0] d_sel_o;
-reg [ (4-1):0] d_sel_o;
+output [(4-1):0] d_sel_o;
+reg [(4-1):0] d_sel_o;
output d_stb_o;
reg d_stb_o;
output d_we_o;
reg d_we_o;
-output [ (3-1):0] d_cti_o;
-reg [ (3-1):0] d_cti_o;
+output [(3-1):0] d_cti_o;
+reg [(3-1):0] d_cti_o;
output d_lock_o;
reg d_lock_o;
-output [ (2-1):0] d_bte_o;
-wire [ (2-1):0] d_bte_o;
+output [(2-1):0] d_bte_o;
+wire [(2-1):0] d_bte_o;
-reg [ 1:0] size_m;
-reg [ 1:0] size_w;
+reg [1:0] size_m;
+reg [1:0] size_w;
reg sign_extend_m;
reg sign_extend_w;
-reg [ (32-1):0] store_data_x;
-reg [ (32-1):0] store_data_m;
-reg [ (4-1):0] byte_enable_x;
-reg [ (4-1):0] byte_enable_m;
-wire [ (32-1):0] data_m;
-reg [ (32-1):0] data_w;
+reg [(32-1):0] store_data_x;
+reg [(32-1):0] store_data_m;
+reg [(4-1):0] byte_enable_x;
+reg [(4-1):0] byte_enable_m;
+wire [(32-1):0] data_m;
+reg [(32-1):0] data_w;
-
+
@@ -56116,8 +50996,7 @@ reg [ (32-1):0] data_w;
-
-
+
@@ -56125,25 +51004,21 @@ reg [ (32-1):0] data_w;
-
wire wb_select_x;
-
+
-
reg wb_select_m;
-reg [ (32-1):0] wb_data_m;
+reg [(32-1):0] wb_data_m;
reg wb_load_complete;
-
-
-
+
@@ -56198,8 +51073,7 @@ endfunction
-
-
+
@@ -56283,8 +51157,7 @@ endfunction
-
-
+
@@ -56323,20 +51196,17 @@ endfunction
-
-
+
-
-
+
-
-
+
@@ -56346,32 +51216,28 @@ endfunction
-
- assign wb_select_x = 1'b1
-
+ assign wb_select_x = 1'b1
+
-
-
+
-
-
+
-
;
always @(*)
begin
case (size_x)
- 2'b00: store_data_x = {4{store_operand_x[7:0]}};
- 2'b11: store_data_x = {2{store_operand_x[15:0]}};
- 2'b10: store_data_x = store_operand_x;
- default: store_data_x = { 32{1'bx}};
+ 2'b00: store_data_x = {4{store_operand_x[7:0]}};
+ 2'b11: store_data_x = {2{store_operand_x[15:0]}};
+ 2'b10: store_data_x = store_operand_x;
+ default: store_data_x = {32{1'bx}};
endcase
end
@@ -56379,18 +51245,18 @@ end
always @(*)
begin
casez ({size_x, load_store_address_x[1:0]})
- { 2'b00, 2'b11}: byte_enable_x = 4'b0001;
- { 2'b00, 2'b10}: byte_enable_x = 4'b0010;
- { 2'b00, 2'b01}: byte_enable_x = 4'b0100;
- { 2'b00, 2'b00}: byte_enable_x = 4'b1000;
- { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
- { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
- { 2'b10, 2'b??}: byte_enable_x = 4'b1111;
+ {2'b00, 2'b11}: byte_enable_x = 4'b0001;
+ {2'b00, 2'b10}: byte_enable_x = 4'b0010;
+ {2'b00, 2'b01}: byte_enable_x = 4'b0100;
+ {2'b00, 2'b00}: byte_enable_x = 4'b1000;
+ {2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+ {2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+ {2'b10, 2'b??}: byte_enable_x = 4'b1111;
default: byte_enable_x = 4'bxxxx;
endcase
end
-
+
@@ -56398,8 +51264,7 @@ end
-
-
+
@@ -56407,8 +51272,7 @@ end
-
-
+
@@ -56428,9 +51292,8 @@ end
-
-
+
@@ -56465,8 +51328,7 @@ end
-
-
+
@@ -56481,20 +51343,15 @@ end
-
-
+
-
assign data_m = wb_data_m;
-
-
-
@@ -56502,21 +51359,21 @@ end
always @(*)
begin
casez ({size_w, load_store_address_w[1:0]})
- { 2'b00, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
- { 2'b00, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
- { 2'b00, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
- { 2'b00, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
- { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
- { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
- { 2'b10, 2'b??}: load_data_w = data_w;
- default: load_data_w = { 32{1'bx}};
+ {2'b00, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+ {2'b00, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+ {2'b00, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+ {2'b00, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+ {2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+ {2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+ {2'b10, 2'b??}: load_data_w = data_w;
+ default: load_data_w = {32{1'bx}};
endcase
end
-assign d_bte_o = 2'b00;
+assign d_bte_o = 2'b00;
-
+
@@ -56550,74 +51407,69 @@ assign d_bte_o = 2'b00;
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- d_cyc_o <= 1'b0;
- d_stb_o <= 1'b0;
- d_dat_o <= { 32{1'b0}};
- d_adr_o <= { 32{1'b0}};
- d_sel_o <= { 4{ 1'b0}};
- d_we_o <= 1'b0;
- d_cti_o <= 3'b111;
- d_lock_o <= 1'b0;
- wb_data_m <= { 32{1'b0}};
- wb_load_complete <= 1'b0;
- stall_wb_load <= 1'b0;
-
+ d_cyc_o <= 1'b0;
+ d_stb_o <= 1'b0;
+ d_dat_o <= {32{1'b0}};
+ d_adr_o <= {32{1'b0}};
+ d_sel_o <= {4{1'b0}};
+ d_we_o <= 1'b0;
+ d_cti_o <= 3'b111;
+ d_lock_o <= 1'b0;
+ wb_data_m <= {32{1'b0}};
+ wb_load_complete <= 1'b0;
+ stall_wb_load <= 1'b0;
+
-
end
else
begin
-
+
-
- if (d_cyc_o == 1'b1)
+ if (d_cyc_o == 1'b1)
begin
- if ((d_ack_i == 1'b1) || (d_err_i == 1'b1))
+ if ((d_ack_i == 1'b1) || (d_err_i == 1'b1))
begin
-
+
-
begin
- d_cyc_o <= 1'b0;
- d_stb_o <= 1'b0;
- d_lock_o <= 1'b0;
+ d_cyc_o <= 1'b0;
+ d_stb_o <= 1'b0;
+ d_lock_o <= 1'b0;
end
-
+
-
wb_data_m <= d_dat_i;
wb_load_complete <= !d_we_o;
end
- if (d_err_i == 1'b1)
+ if (d_err_i == 1'b1)
$display ("Data bus error. Address: %x", d_adr_o);
end
else
begin
-
+
@@ -56630,115 +51482,106 @@ begin
-
- if ( (store_q_m == 1'b1)
- && (stall_m == 1'b0)
-
+ if ( (store_q_m == 1'b1)
+ && (stall_m == 1'b0)
+
-
-
+
-
)
begin
d_dat_o <= store_data_m;
d_adr_o <= load_store_address_m;
- d_cyc_o <= 1'b1;
+ d_cyc_o <= 1'b1;
d_sel_o <= byte_enable_m;
- d_stb_o <= 1'b1;
- d_we_o <= 1'b1;
- d_cti_o <= 3'b111;
+ d_stb_o <= 1'b1;
+ d_we_o <= 1'b1;
+ d_cti_o <= 3'b111;
end
- else if ( (load_q_m == 1'b1)
- && (wb_select_m == 1'b1)
- && (wb_load_complete == 1'b0)
+ else if ( (load_q_m == 1'b1)
+ && (wb_select_m == 1'b1)
+ && (wb_load_complete == 1'b0)
)
begin
- stall_wb_load <= 1'b0;
+ stall_wb_load <= 1'b0;
d_adr_o <= load_store_address_m;
- d_cyc_o <= 1'b1;
+ d_cyc_o <= 1'b1;
d_sel_o <= byte_enable_m;
- d_stb_o <= 1'b1;
- d_we_o <= 1'b0;
- d_cti_o <= 3'b111;
+ d_stb_o <= 1'b1;
+ d_we_o <= 1'b0;
+ d_cti_o <= 3'b111;
end
end
- if (stall_m == 1'b0)
- wb_load_complete <= 1'b0;
+ if (stall_m == 1'b0)
+ wb_load_complete <= 1'b0;
- if ((load_q_x == 1'b1) && (wb_select_x == 1'b1) && (stall_x == 1'b0))
- stall_wb_load <= 1'b1;
+ if ((load_q_x == 1'b1) && (wb_select_x == 1'b1) && (stall_x == 1'b0))
+ stall_wb_load <= 1'b1;
- if ((kill_m == 1'b1) || (exception_m == 1'b1))
- stall_wb_load <= 1'b0;
+ if ((kill_m == 1'b1) || (exception_m == 1'b1))
+ stall_wb_load <= 1'b0;
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- sign_extend_m <= 1'b0;
+ sign_extend_m <= 1'b0;
size_m <= 2'b00;
- byte_enable_m <= 1'b0;
- store_data_m <= { 32{1'b0}};
-
+ byte_enable_m <= 1'b0;
+ store_data_m <= {32{1'b0}};
+
-
-
+
-
-
+
-
- wb_select_m <= 1'b0;
+ wb_select_m <= 1'b0;
end
else
begin
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
sign_extend_m <= sign_extend_x;
size_m <= size_x;
byte_enable_m <= byte_enable_x;
store_data_m <= store_data_x;
-
+
-
-
+
-
-
+
-
wb_select_m <= wb_select_x;
end
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
size_w <= 2'b00;
- data_w <= { 32{1'b0}};
- sign_extend_w <= 1'b0;
+ data_w <= {32{1'b0}};
+ sign_extend_w <= 1'b0;
end
else
begin
@@ -56757,11 +51600,11 @@ end
always @(posedge clk_i)
begin
- if (((load_q_m == 1'b1) || (store_q_m == 1'b1)) && (stall_m == 1'b0))
+ if (((load_q_m == 1'b1) || (store_q_m == 1'b1)) && (stall_m == 1'b0))
begin
- if ((size_m === 2'b11) && (load_store_address_m[0] !== 1'b0))
+ if ((size_m === 2'b11) && (load_store_address_m[0] !== 1'b0))
$display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
- if ((size_m === 2'b10) && (load_store_address_m[1:0] !== 2'b00))
+ if ((size_m === 2'b10) && (load_store_address_m[1:0] !== 2'b00))
$display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
end
end
@@ -56803,10 +51646,7 @@ endmodule
-
-
-
-
+
@@ -56836,9 +51676,9 @@ endmodule
-
+
@@ -57123,104 +51963,55 @@ endmodule
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
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-
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-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -57233,36 +52024,27 @@ module lm32_decoder_medium_icache (
d_result_sel_0,
d_result_sel_1,
x_result_sel_csr,
-
+
-
-
+
-
-
-
- x_result_sel_sext,
+ x_result_sel_sext,
x_result_sel_logic,
-
+
-
x_result_sel_add,
m_result_sel_compare,
-
-
- m_result_sel_shift,
+ m_result_sel_shift,
w_result_sel_load,
-
-
- w_result_sel_mul,
+ w_result_sel_mul,
x_bypass_enable,
m_bypass_enable,
@@ -57280,44 +52062,36 @@ module lm32_decoder_medium_icache (
sign_extend,
adder_op,
logic_op,
-
-
- direction,
+ direction,
-
+
-
-
+
-
-
+
-
branch,
branch_reg,
condition,
bi_conditional,
bi_unconditional,
-
+
-
scall,
eret,
-
+
-
-
+
-
csr_write_enable
);
@@ -57325,58 +52099,49 @@ module lm32_decoder_medium_icache (
-input [ (32-1):0] instruction;
+input [(32-1):0] instruction;
-output [ 0:0] d_result_sel_0;
-reg [ 0:0] d_result_sel_0;
-output [ 1:0] d_result_sel_1;
-reg [ 1:0] d_result_sel_1;
+output [0:0] d_result_sel_0;
+reg [0:0] d_result_sel_0;
+output [1:0] d_result_sel_1;
+reg [1:0] d_result_sel_1;
output x_result_sel_csr;
reg x_result_sel_csr;
-
+
-
-
+
-
-
-
+
output x_result_sel_sext;
reg x_result_sel_sext;
-
output x_result_sel_logic;
reg x_result_sel_logic;
-
+
-
output x_result_sel_add;
reg x_result_sel_add;
output m_result_sel_compare;
reg m_result_sel_compare;
-
-
+
output m_result_sel_shift;
reg m_result_sel_shift;
-
output w_result_sel_load;
reg w_result_sel_load;
-
-
+
output w_result_sel_mul;
reg w_result_sel_mul;
-
output x_bypass_enable;
wire x_bypass_enable;
@@ -57384,86 +52149,78 @@ output m_bypass_enable;
wire m_bypass_enable;
output read_enable_0;
wire read_enable_0;
-output [ (5-1):0] read_idx_0;
-wire [ (5-1):0] read_idx_0;
+output [(5-1):0] read_idx_0;
+wire [(5-1):0] read_idx_0;
output read_enable_1;
wire read_enable_1;
-output [ (5-1):0] read_idx_1;
-wire [ (5-1):0] read_idx_1;
+output [(5-1):0] read_idx_1;
+wire [(5-1):0] read_idx_1;
output write_enable;
wire write_enable;
-output [ (5-1):0] write_idx;
-wire [ (5-1):0] write_idx;
-output [ (32-1):0] immediate;
-wire [ (32-1):0] immediate;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output [(5-1):0] write_idx;
+wire [(5-1):0] write_idx;
+output [(32-1):0] immediate;
+wire [(32-1):0] immediate;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
output load;
wire load;
output store;
wire store;
-output [ 1:0] size;
-wire [ 1:0] size;
+output [1:0] size;
+wire [1:0] size;
output sign_extend;
wire sign_extend;
output adder_op;
wire adder_op;
-output [ 3:0] logic_op;
-wire [ 3:0] logic_op;
-
-
+output [3:0] logic_op;
+wire [3:0] logic_op;
+
output direction;
wire direction;
-
-
+
-
-
+
-
-
+
-
output branch;
wire branch;
output branch_reg;
wire branch_reg;
-output [ (3-1):0] condition;
-wire [ (3-1):0] condition;
+output [(3-1):0] condition;
+wire [(3-1):0] condition;
output bi_conditional;
wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
-
+
-
output scall;
wire scall;
output eret;
wire eret;
-
+
-
-
+
-
output csr_write_enable;
wire csr_write_enable;
@@ -57471,10 +52228,10 @@ wire csr_write_enable;
-wire [ (32-1):0] extended_immediate;
-wire [ (32-1):0] high_immediate;
-wire [ (32-1):0] call_immediate;
-wire [ (32-1):0] branch_immediate;
+wire [(32-1):0] extended_immediate;
+wire [(32-1):0] high_immediate;
+wire [(32-1):0] call_immediate;
+wire [(32-1):0] branch_immediate;
wire sign_extend_immediate;
wire select_high_immediate;
wire select_call_immediate;
@@ -57483,9 +52240,7 @@ wire select_call_immediate;
-
-
-
+
@@ -57541,70 +52296,61 @@ endfunction
-
-assign op_add = instruction[ 30:26] == 5'b01101;
-assign op_and = instruction[ 30:26] == 5'b01000;
-assign op_andhi = instruction[ 31:26] == 6'b011000;
-assign op_b = instruction[ 31:26] == 6'b110000;
-assign op_bi = instruction[ 31:26] == 6'b111000;
-assign op_be = instruction[ 31:26] == 6'b010001;
-assign op_bg = instruction[ 31:26] == 6'b010010;
-assign op_bge = instruction[ 31:26] == 6'b010011;
-assign op_bgeu = instruction[ 31:26] == 6'b010100;
-assign op_bgu = instruction[ 31:26] == 6'b010101;
-assign op_bne = instruction[ 31:26] == 6'b010111;
-assign op_call = instruction[ 31:26] == 6'b110110;
-assign op_calli = instruction[ 31:26] == 6'b111110;
-assign op_cmpe = instruction[ 30:26] == 5'b11001;
-assign op_cmpg = instruction[ 30:26] == 5'b11010;
-assign op_cmpge = instruction[ 30:26] == 5'b11011;
-assign op_cmpgeu = instruction[ 30:26] == 5'b11100;
-assign op_cmpgu = instruction[ 30:26] == 5'b11101;
-assign op_cmpne = instruction[ 30:26] == 5'b11111;
-
+assign op_add = instruction[30:26] == 5'b01101;
+assign op_and = instruction[30:26] == 5'b01000;
+assign op_andhi = instruction[31:26] == 6'b011000;
+assign op_b = instruction[31:26] == 6'b110000;
+assign op_bi = instruction[31:26] == 6'b111000;
+assign op_be = instruction[31:26] == 6'b010001;
+assign op_bg = instruction[31:26] == 6'b010010;
+assign op_bge = instruction[31:26] == 6'b010011;
+assign op_bgeu = instruction[31:26] == 6'b010100;
+assign op_bgu = instruction[31:26] == 6'b010101;
+assign op_bne = instruction[31:26] == 6'b010111;
+assign op_call = instruction[31:26] == 6'b110110;
+assign op_calli = instruction[31:26] == 6'b111110;
+assign op_cmpe = instruction[30:26] == 5'b11001;
+assign op_cmpg = instruction[30:26] == 5'b11010;
+assign op_cmpge = instruction[30:26] == 5'b11011;
+assign op_cmpgeu = instruction[30:26] == 5'b11100;
+assign op_cmpgu = instruction[30:26] == 5'b11101;
+assign op_cmpne = instruction[30:26] == 5'b11111;
+
-
-assign op_lb = instruction[ 31:26] == 6'b000100;
-assign op_lbu = instruction[ 31:26] == 6'b010000;
-assign op_lh = instruction[ 31:26] == 6'b000111;
-assign op_lhu = instruction[ 31:26] == 6'b001011;
-assign op_lw = instruction[ 31:26] == 6'b001010;
-
+assign op_lb = instruction[31:26] == 6'b000100;
+assign op_lbu = instruction[31:26] == 6'b010000;
+assign op_lh = instruction[31:26] == 6'b000111;
+assign op_lhu = instruction[31:26] == 6'b001011;
+assign op_lw = instruction[31:26] == 6'b001010;
+
-
-
-
-assign op_mul = instruction[ 30:26] == 5'b00010;
+assign op_mul = instruction[30:26] == 5'b00010;
-assign op_nor = instruction[ 30:26] == 5'b00001;
-assign op_or = instruction[ 30:26] == 5'b01110;
-assign op_orhi = instruction[ 31:26] == 6'b011110;
-assign op_raise = instruction[ 31:26] == 6'b101011;
-assign op_rcsr = instruction[ 31:26] == 6'b100100;
-assign op_sb = instruction[ 31:26] == 6'b001100;
-
-
-assign op_sextb = instruction[ 31:26] == 6'b101100;
-assign op_sexth = instruction[ 31:26] == 6'b110111;
+assign op_nor = instruction[30:26] == 5'b00001;
+assign op_or = instruction[30:26] == 5'b01110;
+assign op_orhi = instruction[31:26] == 6'b011110;
+assign op_raise = instruction[31:26] == 6'b101011;
+assign op_rcsr = instruction[31:26] == 6'b100100;
+assign op_sb = instruction[31:26] == 6'b001100;
+assign op_sextb = instruction[31:26] == 6'b101100;
+assign op_sexth = instruction[31:26] == 6'b110111;
-assign op_sh = instruction[ 31:26] == 6'b000011;
-
-
-assign op_sl = instruction[ 30:26] == 5'b01111;
+assign op_sh = instruction[31:26] == 6'b000011;
+assign op_sl = instruction[30:26] == 5'b01111;
-assign op_sr = instruction[ 30:26] == 5'b00101;
-assign op_sru = instruction[ 30:26] == 5'b00000;
-assign op_sub = instruction[ 31:26] == 6'b110010;
-assign op_sw = instruction[ 31:26] == 6'b010110;
-assign op_user = instruction[ 31:26] == 6'b110011;
-assign op_wcsr = instruction[ 31:26] == 6'b110100;
-assign op_xnor = instruction[ 30:26] == 5'b01001;
-assign op_xor = instruction[ 30:26] == 5'b00110;
+assign op_sr = instruction[30:26] == 5'b00101;
+assign op_sru = instruction[30:26] == 5'b00000;
+assign op_sub = instruction[31:26] == 6'b110010;
+assign op_sw = instruction[31:26] == 6'b010110;
+assign op_user = instruction[31:26] == 6'b110011;
+assign op_wcsr = instruction[31:26] == 6'b110100;
+assign op_xnor = instruction[30:26] == 5'b01001;
+assign op_xor = instruction[30:26] == 5'b00110;
assign arith = op_add | op_sub;
@@ -57614,35 +52360,26 @@ assign bi_conditional = op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne;
assign bi_unconditional = op_bi;
assign bra = op_b | bi_unconditional | bi_conditional;
assign call = op_call | op_calli;
-
-
-assign shift = op_sl | op_sr | op_sru;
+assign shift = op_sl | op_sr | op_sru;
-
+
-
-
+
-
-
-
-assign sext = op_sextb | op_sexth;
+assign sext = op_sextb | op_sexth;
-
-
-assign multiply = op_mul;
+assign multiply = op_mul;
-
+
-
assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
assign store = op_sb | op_sh | op_sw;
@@ -57651,39 +52388,34 @@ always @(*)
begin
if (call)
- d_result_sel_0 = 1'b1;
+ d_result_sel_0 = 1'b1;
else
- d_result_sel_0 = 1'b0;
+ d_result_sel_0 = 1'b0;
if (call)
- d_result_sel_1 = 2'b00;
+ d_result_sel_1 = 2'b00;
else if ((instruction[31] == 1'b0) && !bra)
- d_result_sel_1 = 2'b10;
+ d_result_sel_1 = 2'b10;
else
- d_result_sel_1 = 2'b01;
+ d_result_sel_1 = 2'b01;
- x_result_sel_csr = 1'b0;
-
+ x_result_sel_csr = 1'b0;
+
-
-
+
-
-
-
- x_result_sel_sext = 1'b0;
+ x_result_sel_sext = 1'b0;
- x_result_sel_logic = 1'b0;
-
+ x_result_sel_logic = 1'b0;
+
-
- x_result_sel_add = 1'b0;
+ x_result_sel_add = 1'b0;
if (op_rcsr)
- x_result_sel_csr = 1'b1;
-
+ x_result_sel_csr = 1'b1;
+
@@ -57697,84 +52429,66 @@ begin
-
-
+
-
-
-
- else if (sext)
- x_result_sel_sext = 1'b1;
+ else if (sext)
+ x_result_sel_sext = 1'b1;
else if (logical)
- x_result_sel_logic = 1'b1;
-
+ x_result_sel_logic = 1'b1;
+
-
else
- x_result_sel_add = 1'b1;
+ x_result_sel_add = 1'b1;
m_result_sel_compare = cmp;
-
-
- m_result_sel_shift = shift;
+ m_result_sel_shift = shift;
w_result_sel_load = load;
-
-
- w_result_sel_mul = op_mul;
+ w_result_sel_mul = op_mul;
end
assign x_bypass_enable = arith
| logical
-
+
-
-
+
-
-
+
-
-
+
-
-
-
- | sext
+ | sext
-
+
-
| op_rcsr
;
assign m_bypass_enable = x_bypass_enable
-
-
- | shift
+ | shift
| cmp
;
@@ -57800,32 +52514,27 @@ assign sign_extend = instruction[28];
assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
assign logic_op = instruction[29:26];
-
-
+
assign direction = instruction[29];
-
assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
-
+
-
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
-
+
-
-
+
-
assign csr_write_enable = op_wcsr;
@@ -57839,11 +52548,11 @@ assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, inst
assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
-assign immediate = select_high_immediate == 1'b1
+assign immediate = select_high_immediate == 1'b1
? high_immediate
: extended_immediate;
-assign branch_offset = select_call_immediate == 1'b1
+assign branch_offset = select_call_immediate == 1'b1
? call_immediate
: branch_immediate;
@@ -57884,10 +52593,7 @@ endmodule
-
-
-
-
+
@@ -57917,9 +52623,9 @@ endmodule
-
+
@@ -58203,48 +52909,28 @@ endmodule
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
-
+
+
+
+
+
+
+
+
+
@@ -58262,10 +52948,9 @@ module lm32_icache_medium_icache (
refill_ready,
refill_data,
iflush,
-
+
-
valid_d,
branch_predict_taken_d,
@@ -58294,7 +52979,7 @@ localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
localparam addr_set_lsb = (addr_offset_msb+1);
localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
localparam addr_tag_lsb = (addr_set_msb+1);
-localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_msb = clogb2(32'h7fffffff-32'h0)-1;
localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
@@ -58310,18 +52995,17 @@ input stall_f;
input valid_d;
input branch_predict_taken_d;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;
input read_enable_f;
input refill_ready;
-input [ (32-1):0] refill_data;
+input [(32-1):0] refill_data;
input iflush;
-
+
-
@@ -58333,12 +53017,12 @@ output restart_request;
reg restart_request;
output refill_request;
wire refill_request;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
output refilling;
reg refilling;
-output [ (32-1):0] inst;
-wire [ (32-1):0] inst;
+output [(32-1):0] inst;
+wire [(32-1):0] inst;
@@ -58346,27 +53030,27 @@ wire [ (32-1):0] inst;
wire enable;
wire [0:associativity-1] way_mem_we;
-wire [ (32-1):0] way_data[0:associativity-1];
-wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [(32-1):0] way_data[0:associativity-1];
+wire [((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
wire [0:associativity-1] way_valid;
wire [0:associativity-1] way_match;
wire miss;
-wire [ (addr_set_width-1):0] tmem_read_address;
-wire [ (addr_set_width-1):0] tmem_write_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
-wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+wire [(addr_set_width-1):0] tmem_read_address;
+wire [(addr_set_width-1):0] tmem_write_address;
+wire [((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [((addr_tag_width+1)-1):0] tmem_write_data;
-reg [ 3:0] state;
+reg [3:0] state;
wire flushing;
wire check;
wire refill;
reg [associativity-1:0] refill_way_select;
-reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+reg [addr_offset_msb:addr_offset_lsb] refill_offset;
wire last_refill;
-reg [ (addr_set_width-1):0] flush_set;
+reg [(addr_set_width-1):0] flush_set;
genvar i;
@@ -58374,9 +53058,7 @@ genvar i;
-
-
-
+
@@ -58431,7 +53113,6 @@ endfunction
-
generate
for (i = 0; i < associativity; i = i + 1)
begin : memories
@@ -58440,7 +53121,7 @@ endfunction
#(
.data_width (32),
- .address_width ( (addr_offset_width+addr_set_width))
+ .address_width ((addr_offset_width+addr_set_width))
)
way_0_data_ram
@@ -58452,7 +53133,7 @@ endfunction
.read_address (dmem_read_address),
.enable_read (enable),
.write_address (dmem_write_address),
- .enable_write ( 1'b1),
+ .enable_write (1'b1),
.write_enable (way_mem_we[i]),
.write_data (refill_data),
@@ -58462,8 +53143,8 @@ endfunction
lm32_ram
#(
- .data_width ( (addr_tag_width+1)),
- .address_width ( addr_set_width)
+ .data_width ((addr_tag_width+1)),
+ .address_width (addr_set_width)
)
way_0_tag_ram
@@ -58475,7 +53156,7 @@ endfunction
.read_address (tmem_read_address),
.enable_read (enable),
.write_address (tmem_write_address),
- .enable_write ( 1'b1),
+ .enable_write (1'b1),
.write_enable (way_mem_we[i] | flushing),
.write_data (tmem_write_data),
@@ -58493,7 +53174,7 @@ endgenerate
generate
for (i = 0; i < associativity; i = i + 1)
begin : match
-assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb], 1'b1});
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[addr_tag_msb:addr_tag_lsb], 1'b1});
end
endgenerate
@@ -58512,55 +53193,55 @@ endgenerate
generate
if (bytes_per_line > 4)
-assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+assign dmem_write_address = {refill_address[addr_set_msb:addr_set_lsb], refill_offset};
else
-assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+assign dmem_write_address = refill_address[addr_set_msb:addr_set_lsb];
endgenerate
-assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+assign dmem_read_address = address_a[addr_set_msb:addr_offset_lsb];
-assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_read_address = address_a[addr_set_msb:addr_set_lsb];
assign tmem_write_address = flushing
? flush_set
- : refill_address[ addr_set_msb:addr_set_lsb];
+ : refill_address[addr_set_msb:addr_set_lsb];
generate
if (bytes_per_line > 4)
assign last_refill = refill_offset == {addr_offset_width{1'b1}};
else
-assign last_refill = 1'b1;
+assign last_refill = 1'b1;
endgenerate
-assign enable = (stall_a == 1'b0);
+assign enable = (stall_a == 1'b0);
generate
if (associativity == 1)
begin : we_1
-assign way_mem_we[0] = (refill_ready == 1'b1);
+assign way_mem_we[0] = (refill_ready == 1'b1);
end
else
begin : we_2
-assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1);
-assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1);
+assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1);
+assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1);
end
endgenerate
-assign tmem_write_data[ 0] = last_refill & !flushing;
-assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+assign tmem_write_data[0] = last_refill & !flushing;
+assign tmem_write_data[((addr_tag_width+1)-1):1] = refill_address[addr_tag_msb:addr_tag_lsb];
assign flushing = |state[1:0];
assign check = state[2];
assign refill = state[3];
-assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d);
-assign stall_request = (check == 1'b0);
-assign refill_request = (refill == 1'b1);
+assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check == 1'b0);
+assign refill_request = (refill == 1'b1);
@@ -58570,13 +53251,13 @@ assign refill_request = (refill == 1'b1);
generate
if (associativity >= 2)
begin : way_select
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
else
begin
- if (miss == 1'b1)
+ if (miss == 1'b1)
refill_way_select <= {refill_way_select[0], refill_way_select[1]};
end
end
@@ -58584,77 +53265,76 @@ end
endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- refilling <= 1'b0;
+ if (rst_i == 1'b1)
+ refilling <= 1'b0;
else
refilling <= refill;
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- state <= 4'b0001;
- flush_set <= { addr_set_width{1'b1}};
- refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
- restart_request <= 1'b0;
+ state <= 4'b0001;
+ flush_set <= {addr_set_width{1'b1}};
+ refill_address <= {(clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+ restart_request <= 1'b0;
end
else
begin
case (state)
- 4'b0001:
+ 4'b0001:
begin
- if (flush_set == { addr_set_width{1'b0}})
- state <= 4'b0100;
+ if (flush_set == {addr_set_width{1'b0}})
+ state <= 4'b0100;
flush_set <= flush_set - 1'b1;
end
- 4'b0010:
+ 4'b0010:
begin
- if (flush_set == { addr_set_width{1'b0}})
-
+ if (flush_set == {addr_set_width{1'b0}})
+
-
- state <= 4'b0100;
+ state <= 4'b0100;
flush_set <= flush_set - 1'b1;
end
- 4'b0100:
+ 4'b0100:
begin
- if (stall_a == 1'b0)
- restart_request <= 1'b0;
- if (iflush == 1'b1)
+ if (stall_a == 1'b0)
+ restart_request <= 1'b0;
+ if (iflush == 1'b1)
begin
refill_address <= address_f;
- state <= 4'b0010;
+ state <= 4'b0010;
end
- else if (miss == 1'b1)
+ else if (miss == 1'b1)
begin
refill_address <= address_f;
- state <= 4'b1000;
+ state <= 4'b1000;
end
end
- 4'b1000:
+ 4'b1000:
begin
- if (refill_ready == 1'b1)
+ if (refill_ready == 1'b1)
begin
- if (last_refill == 1'b1)
+ if (last_refill == 1'b1)
begin
- restart_request <= 1'b1;
- state <= 4'b0100;
+ restart_request <= 1'b1;
+ state <= 4'b0100;
end
end
end
@@ -58667,27 +53347,27 @@ generate
if (bytes_per_line > 4)
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
else
begin
case (state)
- 4'b0100:
+ 4'b0100:
begin
- if (iflush == 1'b1)
+ if (iflush == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
- else if (miss == 1'b1)
+ else if (miss == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
end
- 4'b1000:
+ 4'b1000:
begin
- if (refill_ready == 1'b1)
+ if (refill_ready == 1'b1)
refill_offset <= refill_offset + 1'b1;
end
@@ -58699,7 +53379,6 @@ endgenerate
endmodule
-
@@ -58732,10 +53411,7 @@ endmodule
-
-
-
-
+
@@ -58765,9 +53441,9 @@ endmodule
-
+
@@ -59051,9 +53727,7 @@ endmodule
-
-
-
+
@@ -59558,11 +54232,7 @@ endmodule
-
-
-
-
-
+
@@ -59592,9 +54262,9 @@ endmodule
-
+
@@ -59878,9 +54548,7 @@ endmodule
-
-
-
+
@@ -60241,10 +54909,7 @@ endmodule
-
-
-
-
+
@@ -60275,9 +54940,8 @@ endmodule
-
-
+
@@ -60562,8 +55226,6 @@ endmodule
-
-
@@ -60582,48 +55244,40 @@ module lm32_instruction_unit_medium_icache (
kill_f,
branch_predict_taken_d,
branch_predict_address_d,
-
+
-
exception_m,
branch_taken_m,
branch_mispredict_taken_m,
branch_target_m,
-
-
- iflush,
+ iflush,
-
+
-
-
+
-
-
-
+
i_dat_i,
i_ack_i,
i_err_i,
i_rty_i,
-
-
+
-
pc_f,
@@ -60631,20 +55285,16 @@ module lm32_instruction_unit_medium_icache (
pc_x,
pc_m,
pc_w,
-
-
+
icache_stall_request,
icache_restart_request,
icache_refill_request,
icache_refilling,
-
-
+
-
-
-
+
i_dat_o,
i_adr_o,
@@ -60655,21 +55305,16 @@ module lm32_instruction_unit_medium_icache (
i_cti_o,
i_lock_o,
i_bte_o,
-
-
+
-
-
+
-
-
-
- instruction_f,
+ instruction_f,
instruction_d
);
@@ -60706,47 +55351,40 @@ input valid_d;
input kill_f;
input branch_predict_taken_d;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
-
+
-
input exception_m;
input branch_taken_m;
input branch_mispredict_taken_m;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
-
-
-input iflush;
+input iflush;
-
+
-
-
+
-
-
-
-input [ (32-1):0] i_dat_i;
+
+input [(32-1):0] i_dat_i;
input i_ack_i;
input i_err_i;
input i_rty_i;
-
-
+
@@ -60756,21 +55394,19 @@ input i_rty_i;
-
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-
-
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
output icache_stall_request;
wire icache_stall_request;
output icache_restart_request;
@@ -60779,136 +55415,111 @@ output icache_refill_request;
wire icache_refill_request;
output icache_refilling;
wire icache_refilling;
-
-
+
-
-
-
-output [ (32-1):0] i_dat_o;
-
+
+output [(32-1):0] i_dat_o;
+
+wire [(32-1):0] i_dat_o;
-wire [ (32-1):0] i_dat_o;
-
-
-output [ (32-1):0] i_adr_o;
-reg [ (32-1):0] i_adr_o;
+output [(32-1):0] i_adr_o;
+reg [(32-1):0] i_adr_o;
output i_cyc_o;
reg i_cyc_o;
-output [ (4-1):0] i_sel_o;
-
+output [(4-1):0] i_sel_o;
+
-
-wire [ (4-1):0] i_sel_o;
-
+wire [(4-1):0] i_sel_o;
output i_stb_o;
reg i_stb_o;
output i_we_o;
-
+
-
wire i_we_o;
-
-output [ (3-1):0] i_cti_o;
-reg [ (3-1):0] i_cti_o;
+output [(3-1):0] i_cti_o;
+reg [(3-1):0] i_cti_o;
output i_lock_o;
reg i_lock_o;
-output [ (2-1):0] i_bte_o;
-wire [ (2-1):0] i_bte_o;
-
+output [(2-1):0] i_bte_o;
+wire [(2-1):0] i_bte_o;
-
+
-
-
+
-
-
-
-output [ (32-1):0] instruction_f;
-wire [ (32-1):0] instruction_f;
+output [(32-1):0] instruction_f;
+wire [(32-1):0] instruction_f;
-output [ (32-1):0] instruction_d;
-reg [ (32-1):0] instruction_d;
+output [(32-1):0] instruction_d;
+reg [(32-1):0] instruction_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;
-
-
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;
-
-
+
wire icache_read_enable_f;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;
reg icache_refill_ready;
-reg [ (32-1):0] icache_refill_data;
-wire [ (32-1):0] icache_data_f;
-wire [ (3-1):0] first_cycle_type;
-wire [ (3-1):0] next_cycle_type;
+reg [(32-1):0] icache_refill_data;
+wire [(32-1):0] icache_data_f;
+wire [(3-1):0] first_cycle_type;
+wire [(3-1):0] next_cycle_type;
wire last_word;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;
-
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;
+
-
-
+
+
-
+
-
+
-
+
-
-
-
-
-
-
-
-
-
+
@@ -60964,8 +55575,7 @@ endfunction
-
-
+
@@ -61011,11 +55621,9 @@ endfunction
-
-
-
+
lm32_icache_medium_icache #(
.associativity (associativity),
@@ -61045,81 +55653,68 @@ lm32_icache_medium_icache #(
.refilling (icache_refilling),
.inst (icache_data_f)
);
-
-
-
+
-assign icache_read_enable_f = (valid_f == 1'b1)
- && (kill_f == 1'b0)
-
+assign icache_read_enable_f = (valid_f == 1'b1)
+ && (kill_f == 1'b0)
+
-
-
+
-
;
-
always @(*)
begin
-
+
-
- if (branch_taken_m == 1'b1)
- if ((branch_mispredict_taken_m == 1'b1) && (exception_m == 1'b0))
+ if (branch_taken_m == 1'b1)
+ if ((branch_mispredict_taken_m == 1'b1) && (exception_m == 1'b0))
pc_a = pc_x;
else
pc_a = branch_target_m;
-
+
-
else
- if ( (valid_d == 1'b1) && (branch_predict_taken_d == 1'b1) )
+ if ( (valid_d == 1'b1) && (branch_predict_taken_d == 1'b1) )
pc_a = branch_predict_address_d;
else
-
-
- if (icache_restart_request == 1'b1)
+
+ if (icache_restart_request == 1'b1)
pc_a = restart_address;
else
-
pc_a = pc_f + 1'b1;
end
-
+
-
-
-
-
+
+
-
assign instruction_f = icache_data_f;
-
-
+
@@ -61132,50 +55727,43 @@ assign instruction_f = icache_data_f;
-
-
-
-
-
+
+
assign i_dat_o = 32'd0;
-assign i_we_o = 1'b0;
+assign i_we_o = 1'b0;
assign i_sel_o = 4'b1111;
-
-
-assign i_bte_o = 2'b00;
-
+assign i_bte_o = 2'b00;
-
+
generate
case (bytes_per_line)
4:
begin
-assign first_cycle_type = 3'b111;
-assign next_cycle_type = 3'b111;
-assign last_word = 1'b1;
+assign first_cycle_type = 3'b111;
+assign next_cycle_type = 3'b111;
+assign last_word = 1'b1;
assign first_address = icache_refill_address;
end
8:
begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = 3'b111;
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = 3'b111;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
-assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+assign first_address = {icache_refill_address[(clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
end
16:
begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
-assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+assign first_address = {icache_refill_address[(clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
end
endcase
endgenerate
-
@@ -61183,40 +55771,39 @@ endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- pc_f <= ( 32'h00000000-4)/4;
- pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_f <= (32'h00000000-4)/4;
+ pc_d <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_x <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_m <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_w <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
end
else
begin
- if (stall_f == 1'b0)
+ if (stall_f == 1'b0)
pc_f <= pc_a;
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
pc_d <= pc_f;
- if (stall_x == 1'b0)
+ if (stall_x == 1'b0)
pc_x <= pc_d;
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
pc_m <= pc_x;
pc_w <= pc_m;
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ if (rst_i == 1'b1)
+ restart_address <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
else
begin
-
+
@@ -61228,22 +55815,17 @@ begin
-
-
-
- if (icache_refill_request == 1'b1)
+
+ if (icache_refill_request == 1'b1)
restart_address <= icache_refill_address;
-
-
end
end
-
-
+
@@ -61256,8 +55838,7 @@ end
-
-
+
@@ -61270,44 +55851,39 @@ end
+
-
-
-
-
-
-always @(posedge clk_i )
+
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_adr_o <= { 32{1'b0}};
- i_cti_o <= 3'b111;
- i_lock_o <= 1'b0;
- icache_refill_data <= { 32{1'b0}};
- icache_refill_ready <= 1'b0;
-
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_adr_o <= {32{1'b0}};
+ i_cti_o <= 3'b111;
+ i_lock_o <= 1'b0;
+ icache_refill_data <= {32{1'b0}};
+ icache_refill_ready <= 1'b0;
+
-
-
+
-
end
else
begin
- icache_refill_ready <= 1'b0;
+ icache_refill_ready <= 1'b0;
- if (i_cyc_o == 1'b1)
+ if (i_cyc_o == 1'b1)
begin
- if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
+ if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
begin
-
+
@@ -61317,52 +55893,48 @@ begin
-
begin
- if (last_word == 1'b1)
+ if (last_word == 1'b1)
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_lock_o <= 1'b0;
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_lock_o <= 1'b0;
end
i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
i_cti_o <= next_cycle_type;
- icache_refill_ready <= 1'b1;
+ icache_refill_ready <= 1'b1;
icache_refill_data <= i_dat_i;
end
end
-
+
-
end
else
begin
- if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
+ if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
begin
-
+
-
i_adr_o <= {first_address, 2'b00};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
i_cti_o <= first_cycle_type;
-
+
-
end
-
+
@@ -61382,9 +55954,8 @@ begin
-
-
+
@@ -61393,12 +55964,11 @@ begin
-
end
end
end
-
+
@@ -61473,29 +56043,25 @@ end
-
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- instruction_d <= { 32{1'b0}};
-
+ instruction_d <= {32{1'b0}};
+
-
end
else
begin
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
begin
instruction_d <= instruction_f;
-
+
-
end
end
end
@@ -61529,10 +56095,7 @@ endmodule
-
-
-
-
+
@@ -61562,9 +56125,9 @@ endmodule
-
+
@@ -61848,9 +56411,7 @@ endmodule
-
-
-
+
@@ -62317,10 +56878,7 @@ endmodule
-
-
-
-
+
@@ -62351,9 +56909,8 @@ endmodule
-
-
+
@@ -62638,8 +57195,6 @@ endmodule
-
-
@@ -62651,19 +57206,16 @@ module lm32_interrupt_medium_icache (
interrupt,
stall_x,
-
+
-
exception,
-
eret_q_x,
-
+
-
csr,
csr_write_data,
csr_write_enable,
@@ -62677,7 +57229,7 @@ module lm32_interrupt_medium_icache (
-parameter interrupts = 32;
+parameter interrupts = 32;
@@ -62690,22 +57242,19 @@ input [interrupts-1:0] interrupt;
input stall_x;
-
+
-
input exception;
-
input eret_q_x;
-
+
-
-input [ (3-1):0] csr;
-input [ (32-1):0] csr_write_data;
+input [(3-1):0] csr;
+input [(32-1):0] csr_write_data;
input csr_write_enable;
@@ -62715,8 +57264,8 @@ input csr_write_enable;
output interrupt_exception;
wire interrupt_exception;
-output [ (32-1):0] csr_read_data;
-reg [ (32-1):0] csr_read_data;
+output [(32-1):0] csr_read_data;
+reg [(32-1):0] csr_read_data;
@@ -62730,10 +57279,9 @@ wire [interrupts-1:0] interrupt_n_exception;
reg ie;
reg eie;
-
+
-
reg [interrupts-1:0] ip;
reg [interrupts-1:0] im;
@@ -62750,13 +57298,11 @@ assign interrupt_exception = (|interrupt_n_exception) & ie;
assign asserted = ip | interrupt;
-assign ie_csr_read_data = {{ 32-3{1'b0}},
-
+assign ie_csr_read_data = {{32-3{1'b0}},
+
-
1'b0,
-
eie,
ie
@@ -62770,20 +57316,18 @@ generate
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
-
+ 3'h0: csr_read_data = {{32-3{1'b0}},
+
-
1'b0,
-
eie,
ie
};
- 3'h2: csr_read_data = ip;
- 3'h1: csr_read_data = im;
- default: csr_read_data = { 32{1'bx}};
+ 3'h2: csr_read_data = ip;
+ 3'h1: csr_read_data = im;
+ default: csr_read_data = {32{1'bx}};
endcase
end
end
@@ -62793,19 +57337,17 @@ end
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
-
+ 3'h0: csr_read_data = {{32-3{1'b0}},
+
-
1'b0,
-
eie,
ie
};
- 3'h2: csr_read_data = ip;
- default: csr_read_data = { 32{1'bx}};
+ 3'h2: csr_read_data = ip;
+ default: csr_read_data = {32{1'bx}};
endcase
end
end
@@ -62815,9 +57357,8 @@ endgenerate
-
-
- reg [ 10:0] eie_delay = 0;
+
+ reg [10:0] eie_delay = 0;
generate
@@ -62826,16 +57367,15 @@ generate
if (interrupts > 1)
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- ie <= 1'b0;
- eie <= 1'b0;
-
+ ie <= 1'b0;
+ eie <= 1'b0;
+
-
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
eie_delay <= 0;
@@ -62845,7 +57385,7 @@ always @(posedge clk_i )
begin
ip <= asserted;
-
+
@@ -62859,52 +57399,48 @@ always @(posedge clk_i )
-
- if (exception == 1'b1)
+ if (exception == 1'b1)
begin
eie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
-
- else if (stall_x == 1'b0)
+ else if (stall_x == 1'b0)
begin
if(eie_delay[0])
ie <= eie;
- eie_delay <= {1'b0, eie_delay[ 10:1]};
+ eie_delay <= {1'b0, eie_delay[10:1]};
- if (eret_q_x == 1'b1) begin
+ if (eret_q_x == 1'b1) begin
- eie_delay[ 10] <= 1'b1;
- eie_delay[ 10-1:0] <= 0;
+ eie_delay[10] <= 1'b1;
+ eie_delay[10-1:0] <= 0;
end
-
+
-
- else if (csr_write_enable == 1'b1)
+ else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 3'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
+
-
end
- if (csr == 3'h1)
+ if (csr == 3'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 3'h2)
+ if (csr == 3'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -62914,16 +57450,15 @@ end
else
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- ie <= 1'b0;
- eie <= 1'b0;
-
+ ie <= 1'b0;
+ eie <= 1'b0;
+
-
ip <= {interrupts{1'b0}};
eie_delay <= 0;
end
@@ -62931,7 +57466,7 @@ always @(posedge clk_i )
begin
ip <= asserted;
-
+
@@ -62945,48 +57480,44 @@ always @(posedge clk_i )
-
- if (exception == 1'b1)
+ if (exception == 1'b1)
begin
eie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
-
- else if (stall_x == 1'b0)
+ else if (stall_x == 1'b0)
begin
if(eie_delay[0])
ie <= eie;
- eie_delay <= {1'b0, eie_delay[ 10:1]};
+ eie_delay <= {1'b0, eie_delay[10:1]};
- if (eret_q_x == 1'b1) begin
+ if (eret_q_x == 1'b1) begin
- eie_delay[ 10] <= 1'b1;
- eie_delay[ 10-1:0] <= 0;
+ eie_delay[10] <= 1'b1;
+ eie_delay[10-1:0] <= 0;
end
-
+
-
- else if (csr_write_enable == 1'b1)
+ else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 3'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
+
-
end
- if (csr == 3'h2)
+ if (csr == 3'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -63026,72 +57557,41 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
@@ -63119,236 +57619,157 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
-
+
+
+
+
-
+
+
-
-
+
+
+
+
+
+
-
+
+
+
-
+
+
+
-
-
+
+
-
-
-
-
-
-
-
-
-
+
-
-
+
+
+
+
-
-
+
+
+
+
-
+
-
-
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
-
-
-
+
-
-
+
+
+
+
+
+
+
+
+
+
+
-
-
+
+
+
+
+
+
-
+
+
+
@@ -63358,209 +57779,126 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
-
+
+
+
+
-
+
+
-
-
+
+
+
+
-
-
-
+
+
+
-
-
+
+
+
+
-
-
+
+
+
+
-
-
+
+
+
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
@@ -63579,19 +57917,16 @@ module lm32_top_medium_icache_debug (
interrupt,
-
+
-
-
-
+
I_DAT_I,
I_ACK_I,
I_ERR_I,
I_RTY_I,
-
D_DAT_I,
@@ -63599,15 +57934,13 @@ module lm32_top_medium_icache_debug (
D_ERR_I,
D_RTY_I,
-
+
-
-
-
+
I_DAT_O,
I_ADR_O,
@@ -63618,7 +57951,6 @@ module lm32_top_medium_icache_debug (
I_CTI_O,
I_LOCK_O,
I_BTE_O,
-
D_DAT_O,
@@ -63640,25 +57972,22 @@ input clk_i;
input rst_i;
-input [ (32-1):0] interrupt;
+input [(32-1):0] interrupt;
-
+
-
-
-
-input [ (32-1):0] I_DAT_I;
+
+input [(32-1):0] I_DAT_I;
input I_ACK_I;
input I_ERR_I;
input I_RTY_I;
-
-input [ (32-1):0] D_DAT_I;
+input [(32-1):0] D_DAT_I;
input D_ACK_I;
input D_ERR_I;
input D_RTY_I;
@@ -63667,7 +57996,7 @@ input D_RTY_I;
-
+
@@ -63678,68 +58007,63 @@ input D_RTY_I;
-
-
-
-output [ (32-1):0] I_DAT_O;
-wire [ (32-1):0] I_DAT_O;
-output [ (32-1):0] I_ADR_O;
-wire [ (32-1):0] I_ADR_O;
+
+output [(32-1):0] I_DAT_O;
+wire [(32-1):0] I_DAT_O;
+output [(32-1):0] I_ADR_O;
+wire [(32-1):0] I_ADR_O;
output I_CYC_O;
wire I_CYC_O;
-output [ (4-1):0] I_SEL_O;
-wire [ (4-1):0] I_SEL_O;
+output [(4-1):0] I_SEL_O;
+wire [(4-1):0] I_SEL_O;
output I_STB_O;
wire I_STB_O;
output I_WE_O;
wire I_WE_O;
-output [ (3-1):0] I_CTI_O;
-wire [ (3-1):0] I_CTI_O;
+output [(3-1):0] I_CTI_O;
+wire [(3-1):0] I_CTI_O;
output I_LOCK_O;
wire I_LOCK_O;
-output [ (2-1):0] I_BTE_O;
-wire [ (2-1):0] I_BTE_O;
-
+output [(2-1):0] I_BTE_O;
+wire [(2-1):0] I_BTE_O;
-output [ (32-1):0] D_DAT_O;
-wire [ (32-1):0] D_DAT_O;
-output [ (32-1):0] D_ADR_O;
-wire [ (32-1):0] D_ADR_O;
+output [(32-1):0] D_DAT_O;
+wire [(32-1):0] D_DAT_O;
+output [(32-1):0] D_ADR_O;
+wire [(32-1):0] D_ADR_O;
output D_CYC_O;
wire D_CYC_O;
-output [ (4-1):0] D_SEL_O;
-wire [ (4-1):0] D_SEL_O;
+output [(4-1):0] D_SEL_O;
+wire [(4-1):0] D_SEL_O;
output D_STB_O;
wire D_STB_O;
output D_WE_O;
wire D_WE_O;
-output [ (3-1):0] D_CTI_O;
-wire [ (3-1):0] D_CTI_O;
+output [(3-1):0] D_CTI_O;
+wire [(3-1):0] D_CTI_O;
output D_LOCK_O;
wire D_LOCK_O;
-output [ (2-1):0] D_BTE_O;
-wire [ (2-1):0] D_BTE_O;
+output [(2-1):0] D_BTE_O;
+wire [(2-1):0] D_BTE_O;
-
-
+
-wire [ 7:0] jtag_reg_d;
-wire [ 7:0] jtag_reg_q;
+wire [7:0] jtag_reg_d;
+wire [7:0] jtag_reg_q;
wire jtag_update;
wire [2:0] jtag_reg_addr_d;
wire [2:0] jtag_reg_addr_q;
wire jtck;
wire jrstn;
-
-
+
@@ -63755,10 +58079,7 @@ wire jrstn;
-
-
-
-
+
@@ -63811,46 +58132,37 @@ endfunction
-
lm32_cpu_medium_icache_debug cpu (
.clk_i (clk_i),
-
+
-
.rst_i (rst_i),
-
-
- .interrupt (interrupt),
+ .interrupt (interrupt),
-
+
-
-
-
+
.jtag_clk (jtck),
.jtag_update (jtag_update),
.jtag_reg_q (jtag_reg_q),
.jtag_reg_addr_q (jtag_reg_addr_q),
-
-
-
+
.I_DAT_I (I_DAT_I),
.I_ACK_I (I_ACK_I),
.I_ERR_I (I_ERR_I),
.I_RTY_I (I_RTY_I),
-
.D_DAT_I (D_DAT_I),
@@ -63858,7 +58170,7 @@ lm32_cpu_medium_icache_debug cpu (
.D_ERR_I (D_ERR_I),
.D_RTY_I (D_RTY_I),
-
+
@@ -63868,22 +58180,17 @@ lm32_cpu_medium_icache_debug cpu (
-
-
-
+
.jtag_reg_d (jtag_reg_d),
.jtag_reg_addr_d (jtag_reg_addr_d),
-
-
+
-
-
-
+
.I_DAT_O (I_DAT_O),
.I_ADR_O (I_ADR_O),
@@ -63894,8 +58201,7 @@ lm32_cpu_medium_icache_debug cpu (
.I_CTI_O (I_CTI_O),
.I_LOCK_O (I_LOCK_O),
.I_BTE_O (I_BTE_O),
-
-
+
.D_DAT_O (D_DAT_O),
.D_ADR_O (D_ADR_O),
@@ -63908,8 +58214,7 @@ lm32_cpu_medium_icache_debug cpu (
.D_BTE_O (D_BTE_O)
);
-
-
+
jtag_cores jtag_cores (
@@ -63922,7 +58227,6 @@ jtag_cores jtag_cores (
.jtck (jtck),
.jrstn (jrstn)
);
-
endmodule
@@ -63954,10 +58258,7 @@ endmodule
-
-
-
-
+
@@ -63987,9 +58288,9 @@ endmodule
-
+
@@ -64271,24 +58572,15 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
@@ -64300,29 +58592,25 @@ module lm32_mc_arithmetic_medium_icache_debug (
rst_i,
stall_d,
kill_x,
-
+
-
-
+
-
-
+
-
operand_0_d,
operand_1_d,
result_x,
-
+
-
stall_request_x
);
@@ -64334,35 +58622,31 @@ input clk_i;
input rst_i;
input stall_d;
input kill_x;
-
+
-
-
+
-
-
+
-
-input [ (32-1):0] operand_0_d;
-input [ (32-1):0] operand_1_d;
+input [(32-1):0] operand_0_d;
+input [(32-1):0] operand_1_d;
-output [ (32-1):0] result_x;
-reg [ (32-1):0] result_x;
-
+output [(32-1):0] result_x;
+reg [(32-1):0] result_x;
+
-
output stall_request_x;
wire stall_request_x;
@@ -64370,18 +58654,17 @@ wire stall_request_x;
-reg [ (32-1):0] p;
-reg [ (32-1):0] a;
-reg [ (32-1):0] b;
-
+reg [(32-1):0] p;
+reg [(32-1):0] a;
+reg [(32-1):0] b;
+
-
-reg [ 2:0] state;
+reg [2:0] state;
reg [5:0] cycles;
-
+
@@ -64391,16 +58674,14 @@ reg [5:0] cycles;
+assign stall_request_x = state != 3'b000;
-assign stall_request_x = state != 3'b000;
-
-
+
-
-
+
@@ -64410,54 +58691,48 @@ assign stall_request_x = state != 3'b000;
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
cycles <= {6{1'b0}};
- p <= { 32{1'b0}};
- a <= { 32{1'b0}};
- b <= { 32{1'b0}};
-
+ p <= {32{1'b0}};
+ a <= {32{1'b0}};
+ b <= {32{1'b0}};
+
-
-
+
-
- result_x <= { 32{1'b0}};
- state <= 3'b000;
+ result_x <= {32{1'b0}};
+ state <= 3'b000;
end
else
begin
-
+
-
case (state)
- 3'b000:
+ 3'b000:
begin
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
begin
- cycles <= 32;
+ cycles <= 32;
p <= 32'b0;
a <= operand_0_d;
b <= operand_1_d;
-
+
-
-
+
-
-
+
@@ -64474,11 +58749,10 @@ begin
-
end
end
-
+
@@ -64521,9 +58795,8 @@ begin
-
-
+
@@ -64535,9 +58808,8 @@ begin
-
-
+
@@ -64554,7 +58826,6 @@ begin
-
endcase
end
@@ -64625,10 +58896,7 @@ endmodule
-
-
-
-
+
@@ -64658,9 +58926,9 @@ endmodule
-
+
@@ -64945,48 +59213,38 @@ endmodule
-
-
module lm32_cpu_medium_icache_debug (
clk_i,
-
+
-
rst_i,
-
-
- interrupt,
+ interrupt,
-
+
-
-
-
+
jtag_clk,
jtag_update,
jtag_reg_q,
jtag_reg_addr_q,
-
-
-
+
I_DAT_I,
I_ACK_I,
I_ERR_I,
I_RTY_I,
-
D_DAT_I,
@@ -64994,7 +59252,7 @@ module lm32_cpu_medium_icache_debug (
D_ERR_I,
D_RTY_I,
-
+
@@ -65004,22 +59262,17 @@ module lm32_cpu_medium_icache_debug (
-
-
-
+
jtag_reg_d,
jtag_reg_addr_d,
-
-
+
-
-
-
+
I_DAT_O,
I_ADR_O,
@@ -65030,7 +59283,6 @@ module lm32_cpu_medium_icache_debug (
I_CTI_O,
I_LOCK_O,
I_BTE_O,
-
D_DAT_O,
@@ -65048,21 +59300,18 @@ module lm32_cpu_medium_icache_debug (
-parameter eba_reset = 32'h00000000;
-
-
-parameter deba_reset = 32'h10000000;
+parameter eba_reset = 32'h00000000;
+parameter deba_reset = 32'h10000000;
-
-
-parameter icache_associativity = 1;
-parameter icache_sets = 256;
-parameter icache_bytes_per_line = 16;
-parameter icache_base_address = 32'h0;
-parameter icache_limit = 32'h7fffffff;
+parameter icache_associativity = 1;
+parameter icache_sets = 256;
+parameter icache_bytes_per_line = 16;
+parameter icache_base_address = 32'h0;
+parameter icache_limit = 32'h7fffffff;
+
@@ -65070,44 +59319,35 @@ parameter icache_limit = 32'h7fffffff;
-
-
+
-
parameter dcache_associativity = 1;
parameter dcache_sets = 512;
parameter dcache_bytes_per_line = 16;
parameter dcache_base_address = 0;
parameter dcache_limit = 0;
-
-
-
-parameter watchpoints = 32'h4;
-
+parameter watchpoints = 32'h4;
+
-
+
-
parameter breakpoints = 0;
-
-
-
-parameter interrupts = 32;
-
+parameter interrupts = 32;
+
@@ -65115,43 +59355,35 @@ parameter interrupts = 32;
input clk_i;
-
+
-
input rst_i;
-
-
-input [ (32-1):0] interrupt;
+input [(32-1):0] interrupt;
-
+
-
-
-
+
input jtag_clk;
input jtag_update;
-input [ 7:0] jtag_reg_q;
+input [7:0] jtag_reg_q;
input [2:0] jtag_reg_addr_q;
-
-
-
-input [ (32-1):0] I_DAT_I;
+
+input [(32-1):0] I_DAT_I;
input I_ACK_I;
input I_ERR_I;
input I_RTY_I;
-
-input [ (32-1):0] D_DAT_I;
+input [(32-1):0] D_DAT_I;
input D_ACK_I;
input D_ERR_I;
input D_RTY_I;
@@ -65160,7 +59392,7 @@ input D_RTY_I;
-
+
@@ -65177,17 +59409,14 @@ input D_RTY_I;
-
-
-
-output [ 7:0] jtag_reg_d;
-wire [ 7:0] jtag_reg_d;
+
+output [7:0] jtag_reg_d;
+wire [7:0] jtag_reg_d;
output [2:0] jtag_reg_addr_d;
wire [2:0] jtag_reg_addr_d;
-
-
+
@@ -65198,59 +59427,54 @@ wire [2:0] jtag_reg_addr_d;
-
-
-
-output [ (32-1):0] I_DAT_O;
-wire [ (32-1):0] I_DAT_O;
-output [ (32-1):0] I_ADR_O;
-wire [ (32-1):0] I_ADR_O;
+
+output [(32-1):0] I_DAT_O;
+wire [(32-1):0] I_DAT_O;
+output [(32-1):0] I_ADR_O;
+wire [(32-1):0] I_ADR_O;
output I_CYC_O;
wire I_CYC_O;
-output [ (4-1):0] I_SEL_O;
-wire [ (4-1):0] I_SEL_O;
+output [(4-1):0] I_SEL_O;
+wire [(4-1):0] I_SEL_O;
output I_STB_O;
wire I_STB_O;
output I_WE_O;
wire I_WE_O;
-output [ (3-1):0] I_CTI_O;
-wire [ (3-1):0] I_CTI_O;
+output [(3-1):0] I_CTI_O;
+wire [(3-1):0] I_CTI_O;
output I_LOCK_O;
wire I_LOCK_O;
-output [ (2-1):0] I_BTE_O;
-wire [ (2-1):0] I_BTE_O;
-
+output [(2-1):0] I_BTE_O;
+wire [(2-1):0] I_BTE_O;
-output [ (32-1):0] D_DAT_O;
-wire [ (32-1):0] D_DAT_O;
-output [ (32-1):0] D_ADR_O;
-wire [ (32-1):0] D_ADR_O;
+output [(32-1):0] D_DAT_O;
+wire [(32-1):0] D_DAT_O;
+output [(32-1):0] D_ADR_O;
+wire [(32-1):0] D_ADR_O;
output D_CYC_O;
wire D_CYC_O;
-output [ (4-1):0] D_SEL_O;
-wire [ (4-1):0] D_SEL_O;
+output [(4-1):0] D_SEL_O;
+wire [(4-1):0] D_SEL_O;
output D_STB_O;
wire D_STB_O;
output D_WE_O;
wire D_WE_O;
-output [ (3-1):0] D_CTI_O;
-wire [ (3-1):0] D_CTI_O;
+output [(3-1):0] D_CTI_O;
+wire [(3-1):0] D_CTI_O;
output D_LOCK_O;
wire D_LOCK_O;
-output [ (2-1):0] D_BTE_O;
-wire [ (2-1):0] D_BTE_O;
-
+output [(2-1):0] D_BTE_O;
+wire [(2-1):0] D_BTE_O;
-
-reg valid_a;
+reg valid_a;
reg valid_f;
reg valid_d;
@@ -65259,7 +59483,7 @@ reg valid_m;
reg valid_w;
wire q_x;
-wire [ (32-1):0] immediate_d;
+wire [(32-1):0] immediate_d;
wire load_d;
reg load_x;
reg load_m;
@@ -65268,13 +59492,13 @@ wire store_q_x;
wire store_d;
reg store_x;
reg store_m;
-wire [ 1:0] size_d;
-reg [ 1:0] size_x;
+wire [1:0] size_d;
+reg [1:0] size_x;
wire branch_d;
wire branch_predict_d;
wire branch_predict_taken_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_d;
wire bi_unconditional;
wire bi_conditional;
reg branch_x;
@@ -65286,60 +59510,51 @@ reg branch_predict_taken_m;
wire branch_mispredict_taken_m;
wire branch_flushX_m;
wire branch_reg_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
-wire [ 0:0] d_result_sel_0_d;
-wire [ 1:0] d_result_sel_1_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset_d;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_x;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
+wire [0:0] d_result_sel_0_d;
+wire [1:0] d_result_sel_1_d;
wire x_result_sel_csr_d;
reg x_result_sel_csr_x;
-
+
-
-
+
-
-
-
+
wire x_result_sel_sext_d;
reg x_result_sel_sext_x;
-
wire x_result_sel_logic_d;
reg x_result_sel_logic_x;
-
+
-
wire x_result_sel_add_d;
reg x_result_sel_add_x;
wire m_result_sel_compare_d;
reg m_result_sel_compare_x;
reg m_result_sel_compare_m;
-
-
+
wire m_result_sel_shift_d;
reg m_result_sel_shift_x;
reg m_result_sel_shift_m;
-
wire w_result_sel_load_d;
reg w_result_sel_load_x;
reg w_result_sel_load_m;
reg w_result_sel_load_w;
-
-
+
wire w_result_sel_mul_d;
reg w_result_sel_mul_x;
reg w_result_sel_mul_m;
reg w_result_sel_mul_w;
-
wire x_bypass_enable_d;
reg x_bypass_enable_x;
@@ -65356,22 +59571,20 @@ wire write_enable_q_m;
reg write_enable_w;
wire write_enable_q_w;
wire read_enable_0_d;
-wire [ (5-1):0] read_idx_0_d;
+wire [(5-1):0] read_idx_0_d;
wire read_enable_1_d;
-wire [ (5-1):0] read_idx_1_d;
-wire [ (5-1):0] write_idx_d;
-reg [ (5-1):0] write_idx_x;
-reg [ (5-1):0] write_idx_m;
-reg [ (5-1):0] write_idx_w;
-wire [ (5-1):0] csr_d;
-reg [ (5-1):0] csr_x;
-wire [ (3-1):0] condition_d;
-reg [ (3-1):0] condition_x;
-
-
+wire [(5-1):0] read_idx_1_d;
+wire [(5-1):0] write_idx_d;
+reg [(5-1):0] write_idx_x;
+reg [(5-1):0] write_idx_m;
+reg [(5-1):0] write_idx_w;
+wire [(5-1):0] csr_d;
+reg [(5-1):0] csr_x;
+wire [(3-1):0] condition_d;
+reg [(3-1):0] condition_x;
+
wire break_d;
reg break_x;
-
wire scall_d;
reg scall_x;
@@ -65379,70 +59592,60 @@ wire eret_d;
reg eret_x;
wire eret_q_x;
reg eret_m;
-
+
-
-
-
+
wire bret_d;
reg bret_x;
wire bret_q_x;
reg bret_m;
-
-
-
+
wire csr_write_enable_d;
reg csr_write_enable_x;
wire csr_write_enable_q_x;
-
+
-
-
+
+reg [(32-1):0] d_result_0;
+reg [(32-1):0] d_result_1;
+reg [(32-1):0] x_result;
+reg [(32-1):0] m_result;
+reg [(32-1):0] w_result;
-reg [ (32-1):0] d_result_0;
-reg [ (32-1):0] d_result_1;
-reg [ (32-1):0] x_result;
-reg [ (32-1):0] m_result;
-reg [ (32-1):0] w_result;
-
-reg [ (32-1):0] operand_0_x;
-reg [ (32-1):0] operand_1_x;
-reg [ (32-1):0] store_operand_x;
-reg [ (32-1):0] operand_m;
-reg [ (32-1):0] operand_w;
-
+reg [(32-1):0] operand_0_x;
+reg [(32-1):0] operand_1_x;
+reg [(32-1):0] store_operand_x;
+reg [(32-1):0] operand_m;
+reg [(32-1):0] operand_w;
-
-reg [ (32-1):0] reg_data_live_0;
-reg [ (32-1):0] reg_data_live_1;
-reg use_buf;
-reg [ (32-1):0] reg_data_buf_0;
-reg [ (32-1):0] reg_data_buf_1;
-
-
+reg [(32-1):0] reg_data_live_0;
+reg [(32-1):0] reg_data_live_1;
+reg use_buf;
+reg [(32-1):0] reg_data_buf_0;
+reg [(32-1):0] reg_data_buf_1;
-
+
-wire [ (32-1):0] reg_data_0;
-wire [ (32-1):0] reg_data_1;
-reg [ (32-1):0] bypass_data_0;
-reg [ (32-1):0] bypass_data_1;
+wire [(32-1):0] reg_data_0;
+wire [(32-1):0] reg_data_1;
+reg [(32-1):0] bypass_data_0;
+reg [(32-1):0] bypass_data_1;
wire reg_write_enable_q_w;
reg interlock;
@@ -65457,64 +59660,54 @@ wire stall_m;
wire adder_op_d;
reg adder_op_x;
reg adder_op_x_n;
-wire [ (32-1):0] adder_result_x;
+wire [(32-1):0] adder_result_x;
wire adder_overflow_x;
wire adder_carry_n_x;
-wire [ 3:0] logic_op_d;
-reg [ 3:0] logic_op_x;
-wire [ (32-1):0] logic_result_x;
-
-
-
+wire [3:0] logic_op_d;
+reg [3:0] logic_op_x;
+wire [(32-1):0] logic_result_x;
-wire [ (32-1):0] sextb_result_x;
-wire [ (32-1):0] sexth_result_x;
-wire [ (32-1):0] sext_result_x;
+wire [(32-1):0] sextb_result_x;
+wire [(32-1):0] sexth_result_x;
+wire [(32-1):0] sext_result_x;
-
-
+
+
-
wire direction_d;
reg direction_x;
reg direction_m;
-wire [ (32-1):0] shifter_result_m;
-
+wire [(32-1):0] shifter_result_m;
-
+
-
-
+
-
-
-
-wire [ (32-1):0] multiplier_result_w;
+wire [(32-1):0] multiplier_result_w;
-
+
-
-
+
@@ -65523,55 +59716,45 @@ wire [ (32-1):0] multiplier_result_w;
-
-
+
-
-
-
-wire [ (32-1):0] interrupt_csr_read_data_x;
+wire [(32-1):0] interrupt_csr_read_data_x;
-wire [ (32-1):0] cfg;
-wire [ (32-1):0] cfg2;
-
+wire [(32-1):0] cfg;
+wire [(32-1):0] cfg2;
+
+reg [(32-1):0] csr_read_data_x;
-reg [ (32-1):0] csr_read_data_x;
-
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
-
-
-
-wire [ (32-1):0] instruction_f;
+wire [(32-1):0] instruction_f;
-wire [ (32-1):0] instruction_d;
-
-
+wire [(32-1):0] instruction_d;
+
wire iflush;
wire icache_stall_request;
wire icache_restart_request;
wire icache_refill_request;
wire icache_refilling;
-
-
+
@@ -65580,8 +59763,7 @@ wire icache_refilling;
-
-
+
@@ -65589,38 +59771,29 @@ wire icache_refilling;
-
-wire [ (32-1):0] load_data_w;
+wire [(32-1):0] load_data_w;
wire stall_wb_load;
-
-
-
-
-wire [ (32-1):0] jtx_csr_read_data;
-wire [ (32-1):0] jrx_csr_read_data;
+
+wire [(32-1):0] jtx_csr_read_data;
+wire [(32-1):0] jrx_csr_read_data;
-
-
+
wire jtag_csr_write_enable;
-wire [ (32-1):0] jtag_csr_write_data;
-wire [ (5-1):0] jtag_csr;
+wire [(32-1):0] jtag_csr_write_data;
+wire [(5-1):0] jtag_csr;
wire jtag_read_enable;
-wire [ 7:0] jtag_read_data;
+wire [7:0] jtag_read_data;
wire jtag_write_enable;
-wire [ 7:0] jtag_write_data;
-wire [ (32-1):0] jtag_address;
+wire [7:0] jtag_write_data;
+wire [(32-1):0] jtag_address;
wire jtag_access_complete;
-
-
-
-wire jtag_break;
+wire jtag_break;
-
@@ -65638,10 +59811,9 @@ wire cmp_overflow;
wire cmp_carry_n;
reg condition_met_x;
reg condition_met_m;
-
+
-
wire branch_taken_m;
wire kill_f;
@@ -65650,25 +59822,19 @@ wire kill_x;
wire kill_m;
wire kill_w;
-reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
-
-
-reg [ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;
+reg [(clogb2(32'h7fffffff-32'h0)-2)+2-1:8] eba;
+reg [(clogb2(32'h7fffffff-32'h0)-2)+2-1:8] deba;
-reg [ (3-1):0] eid_x;
-
+reg [(3-1):0] eid_x;
+
-
-
-
-
-
-wire dc_ss;
+
+wire dc_ss;
wire dc_re;
wire exception_x;
@@ -65681,46 +59847,35 @@ wire non_debug_exception_x;
reg non_debug_exception_m;
reg non_debug_exception_w;
wire non_debug_exception_q_w;
-
+
-
-
-
-
-
-wire reset_exception;
-
+wire reset_exception;
-
-wire interrupt_exception;
+wire interrupt_exception;
-
-
+
wire breakpoint_exception;
wire watchpoint_exception;
-
-
+
-
-
+
-
wire system_call_exception;
-
+
@@ -65728,10 +59883,7 @@ wire system_call_exception;
-
-
-
-
+
@@ -65787,7 +59939,6 @@ endfunction
-
lm32_instruction_unit_medium_icache_debug #(
.associativity (icache_associativity),
.sets (icache_sets),
@@ -65809,48 +59960,39 @@ lm32_instruction_unit_medium_icache_debug #(
.kill_f (kill_f),
.branch_predict_taken_d (branch_predict_taken_d),
.branch_predict_address_d (branch_predict_address_d),
-
+
-
.exception_m (exception_m),
.branch_taken_m (branch_taken_m),
.branch_mispredict_taken_m (branch_mispredict_taken_m),
.branch_target_m (branch_target_m),
-
-
- .iflush (iflush),
+ .iflush (iflush),
-
+
-
-
+
-
-
-
+
.i_dat_i (I_DAT_I),
.i_ack_i (I_ACK_I),
.i_err_i (I_ERR_I),
.i_rty_i (I_RTY_I),
-
-
-
+
.jtag_read_enable (jtag_read_enable),
.jtag_write_enable (jtag_write_enable),
.jtag_write_data (jtag_write_data),
.jtag_address (jtag_address),
-
@@ -65859,20 +60001,16 @@ lm32_instruction_unit_medium_icache_debug #(
.pc_x (pc_x),
.pc_m (pc_m),
.pc_w (pc_w),
-
-
+
.icache_stall_request (icache_stall_request),
.icache_restart_request (icache_restart_request),
.icache_refill_request (icache_refill_request),
.icache_refilling (icache_refilling),
-
-
+
-
-
-
+
.i_dat_o (I_DAT_O),
.i_adr_o (I_ADR_O),
@@ -65883,22 +60021,16 @@ lm32_instruction_unit_medium_icache_debug #(
.i_cti_o (I_CTI_O),
.i_lock_o (I_LOCK_O),
.i_bte_o (I_BTE_O),
-
-
-
+
.jtag_read_data (jtag_read_data),
.jtag_access_complete (jtag_access_complete),
-
-
+
-
-
-
- .instruction_f (instruction_f),
+ .instruction_f (instruction_f),
.instruction_d (instruction_d)
);
@@ -65911,36 +60043,27 @@ lm32_decoder_medium_icache_debug decoder (
.d_result_sel_0 (d_result_sel_0_d),
.d_result_sel_1 (d_result_sel_1_d),
.x_result_sel_csr (x_result_sel_csr_d),
-
+
-
-
+
-
-
-
- .x_result_sel_sext (x_result_sel_sext_d),
+ .x_result_sel_sext (x_result_sel_sext_d),
.x_result_sel_logic (x_result_sel_logic_d),
-
+
-
.x_result_sel_add (x_result_sel_add_d),
.m_result_sel_compare (m_result_sel_compare_d),
-
-
- .m_result_sel_shift (m_result_sel_shift_d),
+ .m_result_sel_shift (m_result_sel_shift_d),
.w_result_sel_load (w_result_sel_load_d),
-
-
- .w_result_sel_mul (w_result_sel_mul_d),
+ .w_result_sel_mul (w_result_sel_mul_d),
.x_bypass_enable (x_bypass_enable_d),
.m_bypass_enable (m_bypass_enable_d),
@@ -65958,46 +60081,36 @@ lm32_decoder_medium_icache_debug decoder (
.sign_extend (sign_extend_d),
.adder_op (adder_op_d),
.logic_op (logic_op_d),
-
-
- .direction (direction_d),
+ .direction (direction_d),
-
+
-
-
+
-
-
+
-
.branch (branch_d),
.bi_unconditional (bi_unconditional),
.bi_conditional (bi_conditional),
.branch_reg (branch_reg_d),
.condition (condition_d),
-
-
- .break_opcode (break_d),
+ .break_opcode (break_d),
.scall (scall_d),
.eret (eret_d),
-
-
- .bret (bret_d),
+ .bret (bret_d),
-
+
-
.csr_write_enable (csr_write_enable_d)
);
@@ -66031,14 +60144,12 @@ lm32_load_store_unit_medium_icache_debug #(
.store_q_m (store_q_m),
.sign_extend_x (sign_extend_x),
.size_x (size_x),
-
+
-
-
+
-
.d_dat_i (D_DAT_I),
.d_ack_i (D_ACK_I),
@@ -66046,20 +60157,18 @@ lm32_load_store_unit_medium_icache_debug #(
.d_rty_i (D_RTY_I),
-
+
-
-
+
-
.load_data_w (load_data_w),
.stall_wb_load (stall_wb_load),
@@ -66098,8 +60207,7 @@ lm32_logic_op logic_op (
.logic_result_x (logic_result_x)
);
-
-
+
lm32_shifter shifter (
@@ -66113,11 +60221,9 @@ lm32_shifter shifter (
.shifter_result_m (shifter_result_m)
);
-
-
-
+
lm32_multiplier multiplier (
@@ -66130,10 +60236,9 @@ lm32_multiplier multiplier (
.result (multiplier_result_w)
);
-
-
+
@@ -66162,11 +60267,9 @@ lm32_multiplier multiplier (
-
-
-
+
lm32_interrupt_medium_icache_debug interrupt_unit (
@@ -66176,19 +60279,15 @@ lm32_interrupt_medium_icache_debug interrupt_unit (
.interrupt (interrupt),
.stall_x (stall_x),
-
-
+
.non_debug_exception (non_debug_exception_q_w),
.debug_exception (debug_exception_q_w),
-
-
+
.eret_q_x (eret_q_x),
-
-
- .bret_q_x (bret_q_x),
+ .bret_q_x (bret_q_x),
.csr (csr_x),
.csr_write_data (operand_1_x),
@@ -66198,11 +60297,9 @@ lm32_interrupt_medium_icache_debug interrupt_unit (
.csr_read_data (interrupt_csr_read_data_x)
);
-
-
-
+
lm32_jtag_medium_icache_debug jtag (
@@ -66214,35 +60311,26 @@ lm32_jtag_medium_icache_debug jtag (
.jtag_reg_q (jtag_reg_q),
.jtag_reg_addr_q (jtag_reg_addr_q),
-
-
+
.csr (csr_x),
.csr_write_data (operand_1_x),
.csr_write_enable (csr_write_enable_q_x),
.stall_x (stall_x),
-
-
-
+
.jtag_read_data (jtag_read_data),
.jtag_access_complete (jtag_access_complete),
-
-
-
- .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
+ .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
-
-
+
.jtx_csr_read_data (jtx_csr_read_data),
.jrx_csr_read_data (jrx_csr_read_data),
-
-
-
+
.jtag_csr_write_enable (jtag_csr_write_enable),
.jtag_csr_write_data (jtag_csr_write_data),
.jtag_csr (jtag_csr),
@@ -66250,23 +60338,18 @@ lm32_jtag_medium_icache_debug jtag (
.jtag_write_enable (jtag_write_enable),
.jtag_write_data (jtag_write_data),
.jtag_address (jtag_address),
-
-
-
+
.jtag_break (jtag_break),
.jtag_reset (reset_exception),
-
.jtag_reg_d (jtag_reg_d),
.jtag_reg_addr_d (jtag_reg_addr_d)
);
-
-
-
+
lm32_debug_medium_icache_debug #(
.breakpoints (breakpoints),
@@ -66282,43 +60365,34 @@ lm32_debug_medium_icache_debug #(
.csr_write_enable_x (csr_write_enable_q_x),
.csr_write_data (operand_1_x),
.csr_x (csr_x),
-
-
+
.jtag_csr_write_enable (jtag_csr_write_enable),
.jtag_csr_write_data (jtag_csr_write_data),
.jtag_csr (jtag_csr),
-
-
-
+
.eret_q_x (eret_q_x),
.bret_q_x (bret_q_x),
.stall_x (stall_x),
.exception_x (exception_x),
.q_x (q_x),
-
+
-
-
-
-
- .dc_ss (dc_ss),
+ .dc_ss (dc_ss),
.dc_re (dc_re),
.bp_match (bp_match),
.wp_match (wp_match)
);
-
-
-
+
@@ -66379,8 +60453,8 @@ lm32_debug_medium_icache_debug #(
- always @(posedge clk_i )
- if (rst_i == 1'b1)
+ always @(posedge clk_i )
+ if (rst_i == 1'b1)
begin
regfile_raw_0 <= 1'b0;
regfile_raw_1 <= 1'b0;
@@ -66435,10 +60509,9 @@ lm32_debug_medium_icache_debug #(
.rdata_o (regfile_data_1)
);
-
-
+
@@ -66511,58 +60584,53 @@ lm32_debug_medium_icache_debug #(
-
-
-
+
assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
-
-
-
+
-
-assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == 1'b1);
-assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == 1'b1);
-assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == 1'b1);
-assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == 1'b1);
-assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == 1'b1);
-assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == 1'b1);
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == 1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == 1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == 1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == 1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == 1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == 1'b1);
always @(*)
begin
- if ( ( (x_bypass_enable_x == 1'b0)
- && ( ((read_enable_0_d == 1'b1) && (raw_x_0 == 1'b1))
- || ((read_enable_1_d == 1'b1) && (raw_x_1 == 1'b1))
+ if ( ( (x_bypass_enable_x == 1'b0)
+ && ( ((read_enable_0_d == 1'b1) && (raw_x_0 == 1'b1))
+ || ((read_enable_1_d == 1'b1) && (raw_x_1 == 1'b1))
)
)
- || ( (m_bypass_enable_m == 1'b0)
- && ( ((read_enable_0_d == 1'b1) && (raw_m_0 == 1'b1))
- || ((read_enable_1_d == 1'b1) && (raw_m_1 == 1'b1))
+ || ( (m_bypass_enable_m == 1'b0)
+ && ( ((read_enable_0_d == 1'b1) && (raw_m_0 == 1'b1))
+ || ((read_enable_1_d == 1'b1) && (raw_m_1 == 1'b1))
)
)
)
- interlock = 1'b1;
+ interlock = 1'b1;
else
- interlock = 1'b0;
+ interlock = 1'b0;
end
always @(*)
begin
- if (raw_x_0 == 1'b1)
+ if (raw_x_0 == 1'b1)
bypass_data_0 = x_result;
- else if (raw_m_0 == 1'b1)
+ else if (raw_m_0 == 1'b1)
bypass_data_0 = m_result;
- else if (raw_w_0 == 1'b1)
+ else if (raw_w_0 == 1'b1)
bypass_data_0 = w_result;
else
bypass_data_0 = reg_data_0;
@@ -66571,11 +60639,11 @@ end
always @(*)
begin
- if (raw_x_1 == 1'b1)
+ if (raw_x_1 == 1'b1)
bypass_data_1 = x_result;
- else if (raw_m_1 == 1'b1)
+ else if (raw_m_1 == 1'b1)
bypass_data_1 = m_result;
- else if (raw_w_1 == 1'b1)
+ else if (raw_w_1 == 1'b1)
bypass_data_1 = w_result;
else
bypass_data_1 = reg_data_1;
@@ -66603,51 +60671,47 @@ always @(*)
begin
d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
case (d_result_sel_1_d)
- 2'b00: d_result_1 = { 32{1'b0}};
- 2'b01: d_result_1 = bypass_data_1;
- 2'b10: d_result_1 = immediate_d;
- default: d_result_1 = { 32{1'bx}};
+ 2'b00: d_result_1 = {32{1'b0}};
+ 2'b01: d_result_1 = bypass_data_1;
+ 2'b10: d_result_1 = immediate_d;
+ default: d_result_1 = {32{1'bx}};
endcase
end
-
+
-
-
-
+
assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
-assign sext_result_x = size_x == 2'b00 ? sextb_result_x : sexth_result_x;
-
+assign sext_result_x = size_x == 2'b00 ? sextb_result_x : sexth_result_x;
-
+
-
assign cmp_zero = operand_0_x == operand_1_x;
-assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_negative = adder_result_x[32-1];
assign cmp_overflow = adder_overflow_x;
assign cmp_carry_n = adder_carry_n_x;
always @(*)
begin
case (condition_x)
- 3'b000: condition_met_x = 1'b1;
- 3'b110: condition_met_x = 1'b1;
- 3'b001: condition_met_x = cmp_zero;
- 3'b111: condition_met_x = !cmp_zero;
- 3'b010: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
- 3'b101: condition_met_x = cmp_carry_n && !cmp_zero;
- 3'b011: condition_met_x = cmp_negative == cmp_overflow;
- 3'b100: condition_met_x = cmp_carry_n;
+ 3'b000: condition_met_x = 1'b1;
+ 3'b110: condition_met_x = 1'b1;
+ 3'b001: condition_met_x = cmp_zero;
+ 3'b111: condition_met_x = !cmp_zero;
+ 3'b010: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+ 3'b101: condition_met_x = cmp_carry_n && !cmp_zero;
+ 3'b011: condition_met_x = cmp_negative == cmp_overflow;
+ 3'b100: condition_met_x = cmp_carry_n;
default: condition_met_x = 1'bx;
endcase
end
@@ -66657,34 +60721,27 @@ always @(*)
begin
x_result = x_result_sel_add_x ? adder_result_x
: x_result_sel_csr_x ? csr_read_data_x
-
-
- : x_result_sel_sext_x ? sext_result_x
+ : x_result_sel_sext_x ? sext_result_x
-
+
-
-
+
-
-
+
-
: logic_result_x;
end
always @(*)
begin
- m_result = m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
-
-
- : m_result_sel_shift_m ? shifter_result_m
+ m_result = m_result_sel_compare_m ? {{32-1{1'b0}}, condition_met_m}
+ : m_result_sel_shift_m ? shifter_result_m
: operand_m;
end
@@ -66693,15 +60750,13 @@ end
always @(*)
begin
w_result = w_result_sel_load_w ? load_data_w
-
-
- : w_result_sel_mul_w ? multiplier_result_w
+ : w_result_sel_mul_w ? multiplier_result_w
: operand_w;
end
-
+
@@ -66712,179 +60767,148 @@ end
-
-assign branch_taken_m = (stall_m == 1'b0)
- && ( ( (branch_m == 1'b1)
- && (valid_m == 1'b1)
- && ( ( (condition_met_m == 1'b1)
- && (branch_predict_taken_m == 1'b0)
+assign branch_taken_m = (stall_m == 1'b0)
+ && ( ( (branch_m == 1'b1)
+ && (valid_m == 1'b1)
+ && ( ( (condition_met_m == 1'b1)
+ && (branch_predict_taken_m == 1'b0)
)
- || ( (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1)
+ || ( (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1)
)
)
)
- || (exception_m == 1'b1)
+ || (exception_m == 1'b1)
);
-assign branch_mispredict_taken_m = (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1);
+assign branch_mispredict_taken_m = (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1);
-assign branch_flushX_m = (stall_m == 1'b0)
- && ( ( (branch_m == 1'b1)
- && (valid_m == 1'b1)
- && ( (condition_met_m == 1'b1)
- || ( (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1)
+assign branch_flushX_m = (stall_m == 1'b0)
+ && ( ( (branch_m == 1'b1)
+ && (valid_m == 1'b1)
+ && ( (condition_met_m == 1'b1)
+ || ( (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1)
)
)
)
- || (exception_m == 1'b1)
+ || (exception_m == 1'b1)
);
-assign kill_f = ( (valid_d == 1'b1)
- && (branch_predict_taken_d == 1'b1)
+assign kill_f = ( (valid_d == 1'b1)
+ && (branch_predict_taken_d == 1'b1)
)
- || (branch_taken_m == 1'b1)
-
+ || (branch_taken_m == 1'b1)
+
-
-
-
- || (icache_refill_request == 1'b1)
+ || (icache_refill_request == 1'b1)
-
+
-
;
-assign kill_d = (branch_taken_m == 1'b1)
-
+assign kill_d = (branch_taken_m == 1'b1)
+
-
-
-
- || (icache_refill_request == 1'b1)
+ || (icache_refill_request == 1'b1)
-
+
-
;
-assign kill_x = (branch_flushX_m == 1'b1)
-
+assign kill_x = (branch_flushX_m == 1'b1)
+
-
;
-assign kill_m = 1'b0
-
+assign kill_m = 1'b0
+
-
;
-assign kill_w = 1'b0
-
+assign kill_w = 1'b0
+
-
;
-
-
-assign breakpoint_exception = ( ( (break_x == 1'b1)
- || (bp_match == 1'b1)
+
+assign breakpoint_exception = ( ( (break_x == 1'b1)
+ || (bp_match == 1'b1)
)
- && (valid_x == 1'b1)
+ && (valid_x == 1'b1)
)
-
-
- || (jtag_break == 1'b1)
+ || (jtag_break == 1'b1)
;
-
-
-
-assign watchpoint_exception = wp_match == 1'b1;
+assign watchpoint_exception = wp_match == 1'b1;
-
+
-
-
+
-
-assign system_call_exception = ( (scall_x == 1'b1)
-
+assign system_call_exception = ( (scall_x == 1'b1)
+
-
);
-
-
-assign debug_exception_x = (breakpoint_exception == 1'b1)
- || (watchpoint_exception == 1'b1)
+
+assign debug_exception_x = (breakpoint_exception == 1'b1)
+ || (watchpoint_exception == 1'b1)
;
-assign non_debug_exception_x = (system_call_exception == 1'b1)
-
-
- || (reset_exception == 1'b1)
+assign non_debug_exception_x = (system_call_exception == 1'b1)
+ || (reset_exception == 1'b1)
-
+
-
-
+
-
-
-
- || ( (interrupt_exception == 1'b1)
-
-
- && (dc_ss == 1'b0)
+ || ( (interrupt_exception == 1'b1)
+
+ && (dc_ss == 1'b0)
-
+
-
)
-
;
-assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1);
-
+assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x == 1'b1);
+
@@ -66906,32 +60930,26 @@ assign exception_x = (debug_exception_x == 1'b1) || (non_debug_exception_x ==
-
always @(*)
begin
-
-
-
-
- if (reset_exception == 1'b1)
- eid_x = 3'h0;
- else
+
+ if (reset_exception == 1'b1)
+ eid_x = 3'h0;
+ else
-
+
-
- if (breakpoint_exception == 1'b1)
- eid_x = 3'd1;
+ if (breakpoint_exception == 1'b1)
+ eid_x = 3'd1;
else
-
-
+
@@ -66939,89 +60957,77 @@ begin
-
-
-
- if (watchpoint_exception == 1'b1)
- eid_x = 3'd3;
- else
+ if (watchpoint_exception == 1'b1)
+ eid_x = 3'd3;
+ else
-
+
-
-
-
- if ( (interrupt_exception == 1'b1)
-
-
- && (dc_ss == 1'b0)
+ if ( (interrupt_exception == 1'b1)
+
+ && (dc_ss == 1'b0)
)
- eid_x = 3'h6;
+ eid_x = 3'h6;
else
-
- eid_x = 3'h7;
+ eid_x = 3'h7;
end
-assign stall_a = (stall_f == 1'b1);
+assign stall_a = (stall_f == 1'b1);
-assign stall_f = (stall_d == 1'b1);
+assign stall_f = (stall_d == 1'b1);
-assign stall_d = (stall_x == 1'b1)
- || ( (interlock == 1'b1)
- && (kill_d == 1'b0)
+assign stall_d = (stall_x == 1'b1)
+ || ( (interlock == 1'b1)
+ && (kill_d == 1'b0)
)
- || ( ( (eret_d == 1'b1)
- || (scall_d == 1'b1)
-
+ || ( ( (eret_d == 1'b1)
+ || (scall_d == 1'b1)
+
-
)
- && ( (load_q_x == 1'b1)
- || (load_q_m == 1'b1)
- || (store_q_x == 1'b1)
- || (store_q_m == 1'b1)
- || (D_CYC_O == 1'b1)
+ && ( (load_q_x == 1'b1)
+ || (load_q_m == 1'b1)
+ || (store_q_x == 1'b1)
+ || (store_q_m == 1'b1)
+ || (D_CYC_O == 1'b1)
)
- && (kill_d == 1'b0)
+ && (kill_d == 1'b0)
)
-
-
- || ( ( (break_d == 1'b1)
- || (bret_d == 1'b1)
+
+ || ( ( (break_d == 1'b1)
+ || (bret_d == 1'b1)
)
- && ( (load_q_x == 1'b1)
- || (store_q_x == 1'b1)
- || (load_q_m == 1'b1)
- || (store_q_m == 1'b1)
- || (D_CYC_O == 1'b1)
+ && ( (load_q_x == 1'b1)
+ || (store_q_x == 1'b1)
+ || (load_q_m == 1'b1)
+ || (store_q_m == 1'b1)
+ || (D_CYC_O == 1'b1)
)
- && (kill_d == 1'b0)
+ && (kill_d == 1'b0)
)
-
- || ( (csr_write_enable_d == 1'b1)
- && (load_q_x == 1'b1)
+ || ( (csr_write_enable_d == 1'b1)
+ && (load_q_x == 1'b1)
)
;
-assign stall_x = (stall_m == 1'b1)
-
+assign stall_x = (stall_m == 1'b1)
+
-
-
+
@@ -67030,16 +61036,14 @@ assign stall_x = (stall_m == 1'b1)
-
;
-assign stall_m = (stall_wb_load == 1'b1)
-
+assign stall_m = (stall_wb_load == 1'b1)
+
-
- || ( (D_CYC_O == 1'b1)
- && ( (store_m == 1'b1)
+ || ( (D_CYC_O == 1'b1)
+ && ( (store_m == 1'b1)
@@ -67053,234 +61057,182 @@ assign stall_m = (stall_wb_load == 1'b1)
-
-
- || ((store_x == 1'b1) && (interrupt_exception == 1'b1))
+ || ((store_x == 1'b1) && (interrupt_exception == 1'b1))
- || (load_m == 1'b1)
- || (load_x == 1'b1)
+ || (load_m == 1'b1)
+ || (load_x == 1'b1)
)
)
-
-
+
-
-
-
- || (icache_stall_request == 1'b1)
- || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1)))
+ || (icache_stall_request == 1'b1)
+ || ((I_CYC_O == 1'b1) && ((branch_m == 1'b1) || (exception_m == 1'b1)))
+
-
-
+
-
;
-
+
-
-
+
-
-
+
-
-
+
-
-assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
-assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
-assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
-
-
-assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1);
+assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
+assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
+assign bret_q_x = (bret_x == 1'b1) && (q_x == 1'b1);
-assign load_q_x = (load_x == 1'b1)
- && (q_x == 1'b1)
-
-
- && (bp_match == 1'b0)
+assign load_q_x = (load_x == 1'b1)
+ && (q_x == 1'b1)
+ && (bp_match == 1'b0)
;
-assign store_q_x = (store_x == 1'b1)
- && (q_x == 1'b1)
-
-
- && (bp_match == 1'b0)
+assign store_q_x = (store_x == 1'b1)
+ && (q_x == 1'b1)
+ && (bp_match == 1'b0)
;
-
+
-
-assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
-assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
-assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
-
-assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1));
-assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1));
+assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
+assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
+assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
+assign debug_exception_q_w = ((debug_exception_w == 1'b1) && (valid_w == 1'b1));
+assign non_debug_exception_q_w = ((non_debug_exception_w == 1'b1) && (valid_w == 1'b1));
+
-assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
-assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
-assign write_enable_q_w = (write_enable_w == 1'b1) && (valid_w == 1'b1);
+assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
+assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
+assign write_enable_q_w = (write_enable_w == 1'b1) && (valid_w == 1'b1);
-assign reg_write_enable_q_w = (write_enable_w == 1'b1) && (kill_w == 1'b0) && (valid_w == 1'b1);
+assign reg_write_enable_q_w = (write_enable_w == 1'b1) && (kill_w == 1'b0) && (valid_w == 1'b1);
assign cfg = {
- 6'h02,
+ 6'h02,
watchpoints[3:0],
breakpoints[3:0],
interrupts[5:0],
-
-
- 1'b1,
-
-
+ 1'b1,
-
-
- 1'b0,
+
-
+ 1'b0,
- 1'b1,
-
-
+ 1'b1,
-
+
- 1'b1,
+ 1'b1,
+
+
+ 1'b1,
-
+
- 1'b1,
+ 1'b0,
-
+
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
+ 1'b1,
-
-
- 1'b0,
+ 1'b1,
-
-
- 1'b1,
-
-
-
-
- 1'b1,
+ 1'b0,
-
-
-
- 1'b0,
-
+ 1'b1
-
-
- 1'b1
-
-
};
assign cfg2 = {
30'b0,
-
+
+ 1'b0,
- 1'b0,
-
-
-
- 1'b0
-
+ 1'b0
};
-
-
-assign iflush = ( (csr_write_enable_d == 1'b1)
- && (csr_d == 5'h3)
- && (stall_d == 1'b0)
- && (kill_d == 1'b0)
- && (valid_d == 1'b1))
-
-
+
+assign iflush = ( (csr_write_enable_d == 1'b1)
+ && (csr_d == 5'h3)
+ && (stall_d == 1'b0)
+ && (kill_d == 1'b0)
+ && (valid_d == 1'b1))
- ||
- ( (jtag_csr_write_enable == 1'b1)
- && (jtag_csr == 5'h3))
+ ||
+ ( (jtag_csr_write_enable == 1'b1)
+ && (jtag_csr == 5'h3))
;
-
@@ -67290,43 +61242,35 @@ assign iflush = ( (csr_write_enable_d == 1'b1)
-
-assign csr_d = read_idx_0_d[ (5-1):0];
+assign csr_d = read_idx_0_d[(5-1):0];
always @(*)
begin
case (csr_x)
-
-
- 5'h0,
- 5'h1,
- 5'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 5'h0,
+ 5'h1,
+ 5'h2: csr_read_data_x = interrupt_csr_read_data_x;
-
+
-
- 5'h6: csr_read_data_x = cfg;
- 5'h7: csr_read_data_x = {eba, 8'h00};
-
-
- 5'h9: csr_read_data_x = {deba, 8'h00};
+ 5'h6: csr_read_data_x = cfg;
+ 5'h7: csr_read_data_x = {eba, 8'h00};
+ 5'h9: csr_read_data_x = {deba, 8'h00};
-
-
- 5'he: csr_read_data_x = jtx_csr_read_data;
- 5'hf: csr_read_data_x = jrx_csr_read_data;
+ 5'he: csr_read_data_x = jtx_csr_read_data;
+ 5'hf: csr_read_data_x = jrx_csr_read_data;
- 5'ha: csr_read_data_x = cfg2;
+ 5'ha: csr_read_data_x = cfg2;
- default: csr_read_data_x = { 32{1'bx}};
+ default: csr_read_data_x = {32{1'bx}};
endcase
end
@@ -67335,47 +61279,41 @@ end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- eba <= eba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if (rst_i == 1'b1)
+ eba <= eba_reset[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0))
- eba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
-
- if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7))
- eba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h7) && (stall_x == 1'b0))
+ eba <= operand_1_x[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h7))
+ eba <= jtag_csr_write_data[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- deba <= deba_reset[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if (rst_i == 1'b1)
+ deba <= deba_reset[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0))
- deba <= operand_1_x[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
-
-
- if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9))
- deba <= jtag_csr_write_data[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 5'h9) && (stall_x == 1'b0))
+ deba <= operand_1_x[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
+ if ((jtag_csr_write_enable == 1'b1) && (jtag_csr == 5'h9))
+ deba <= jtag_csr_write_data[(clogb2(32'h7fffffff-32'h0)-2)+2-1:8];
end
end
-
-
+
@@ -67385,8 +61323,7 @@ end
-
-
+
@@ -67403,13 +61340,11 @@ end
-
-
-
-
+
+
@@ -67423,20 +61358,18 @@ end
-
always @(*)
begin
- if (icache_refill_request == 1'b1)
- valid_a = 1'b0;
- else if (icache_restart_request == 1'b1)
- valid_a = 1'b1;
+ if (icache_refill_request == 1'b1)
+ valid_a = 1'b0;
+ else if (icache_restart_request == 1'b1)
+ valid_a = 1'b1;
else
valid_a = !icache_refilling;
end
-
-
+
@@ -67450,253 +61383,208 @@ end
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- valid_f <= 1'b0;
- valid_d <= 1'b0;
- valid_x <= 1'b0;
- valid_m <= 1'b0;
- valid_w <= 1'b0;
+ valid_f <= 1'b0;
+ valid_d <= 1'b0;
+ valid_x <= 1'b0;
+ valid_m <= 1'b0;
+ valid_w <= 1'b0;
end
else
begin
- if ((kill_f == 1'b1) || (stall_a == 1'b0))
-
-
- valid_f <= valid_a;
+ if ((kill_f == 1'b1) || (stall_a == 1'b0))
-
+ valid_f <= valid_a;
+
- else if (stall_f == 1'b0)
- valid_f <= 1'b0;
+ else if (stall_f == 1'b0)
+ valid_f <= 1'b0;
- if (kill_d == 1'b1)
- valid_d <= 1'b0;
- else if (stall_f == 1'b0)
+ if (kill_d == 1'b1)
+ valid_d <= 1'b0;
+ else if (stall_f == 1'b0)
valid_d <= valid_f & !kill_f;
- else if (stall_d == 1'b0)
- valid_d <= 1'b0;
+ else if (stall_d == 1'b0)
+ valid_d <= 1'b0;
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
valid_x <= valid_d & !kill_d;
- else if (kill_x == 1'b1)
- valid_x <= 1'b0;
- else if (stall_x == 1'b0)
- valid_x <= 1'b0;
-
- if (kill_m == 1'b1)
- valid_m <= 1'b0;
- else if (stall_x == 1'b0)
+ else if (kill_x == 1'b1)
+ valid_x <= 1'b0;
+ else if (stall_x == 1'b0)
+ valid_x <= 1'b0;
+
+ if (kill_m == 1'b1)
+ valid_m <= 1'b0;
+ else if (stall_x == 1'b0)
valid_m <= valid_x & !kill_x;
- else if (stall_m == 1'b0)
- valid_m <= 1'b0;
+ else if (stall_m == 1'b0)
+ valid_m <= 1'b0;
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
valid_w <= valid_m & !kill_m;
else
- valid_w <= 1'b0;
+ valid_w <= 1'b0;
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
-
+
-
- operand_0_x <= { 32{1'b0}};
- operand_1_x <= { 32{1'b0}};
- store_operand_x <= { 32{1'b0}};
- branch_target_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- x_result_sel_csr_x <= 1'b0;
-
+ operand_0_x <= {32{1'b0}};
+ operand_1_x <= {32{1'b0}};
+ store_operand_x <= {32{1'b0}};
+ branch_target_x <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ x_result_sel_csr_x <= 1'b0;
+
-
-
+
-
-
-
- x_result_sel_sext_x <= 1'b0;
+ x_result_sel_sext_x <= 1'b0;
- x_result_sel_logic_x <= 1'b0;
-
+ x_result_sel_logic_x <= 1'b0;
+
-
- x_result_sel_add_x <= 1'b0;
- m_result_sel_compare_x <= 1'b0;
-
-
- m_result_sel_shift_x <= 1'b0;
+ x_result_sel_add_x <= 1'b0;
+ m_result_sel_compare_x <= 1'b0;
+ m_result_sel_shift_x <= 1'b0;
- w_result_sel_load_x <= 1'b0;
-
-
- w_result_sel_mul_x <= 1'b0;
+ w_result_sel_load_x <= 1'b0;
+ w_result_sel_mul_x <= 1'b0;
- x_bypass_enable_x <= 1'b0;
- m_bypass_enable_x <= 1'b0;
- write_enable_x <= 1'b0;
- write_idx_x <= { 5{1'b0}};
- csr_x <= { 5{1'b0}};
- load_x <= 1'b0;
- store_x <= 1'b0;
- size_x <= { 2{1'b0}};
- sign_extend_x <= 1'b0;
- adder_op_x <= 1'b0;
- adder_op_x_n <= 1'b0;
+ x_bypass_enable_x <= 1'b0;
+ m_bypass_enable_x <= 1'b0;
+ write_enable_x <= 1'b0;
+ write_idx_x <= {5{1'b0}};
+ csr_x <= {5{1'b0}};
+ load_x <= 1'b0;
+ store_x <= 1'b0;
+ size_x <= {2{1'b0}};
+ sign_extend_x <= 1'b0;
+ adder_op_x <= 1'b0;
+ adder_op_x_n <= 1'b0;
logic_op_x <= 4'h0;
-
-
- direction_x <= 1'b0;
+ direction_x <= 1'b0;
-
+
-
- branch_x <= 1'b0;
- branch_predict_x <= 1'b0;
- branch_predict_taken_x <= 1'b0;
- condition_x <= 3'b000;
-
-
- break_x <= 1'b0;
+ branch_x <= 1'b0;
+ branch_predict_x <= 1'b0;
+ branch_predict_taken_x <= 1'b0;
+ condition_x <= 3'b000;
+ break_x <= 1'b0;
- scall_x <= 1'b0;
- eret_x <= 1'b0;
-
-
- bret_x <= 1'b0;
+ scall_x <= 1'b0;
+ eret_x <= 1'b0;
+ bret_x <= 1'b0;
-
+
-
- csr_write_enable_x <= 1'b0;
- operand_m <= { 32{1'b0}};
- branch_target_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- m_result_sel_compare_m <= 1'b0;
-
-
- m_result_sel_shift_m <= 1'b0;
+ csr_write_enable_x <= 1'b0;
+ operand_m <= {32{1'b0}};
+ branch_target_m <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ m_result_sel_compare_m <= 1'b0;
+ m_result_sel_shift_m <= 1'b0;
- w_result_sel_load_m <= 1'b0;
-
-
- w_result_sel_mul_m <= 1'b0;
+ w_result_sel_load_m <= 1'b0;
+ w_result_sel_mul_m <= 1'b0;
- m_bypass_enable_m <= 1'b0;
- branch_m <= 1'b0;
- branch_predict_m <= 1'b0;
- branch_predict_taken_m <= 1'b0;
- exception_m <= 1'b0;
- load_m <= 1'b0;
- store_m <= 1'b0;
-
-
- direction_m <= 1'b0;
+ m_bypass_enable_m <= 1'b0;
+ branch_m <= 1'b0;
+ branch_predict_m <= 1'b0;
+ branch_predict_taken_m <= 1'b0;
+ exception_m <= 1'b0;
+ load_m <= 1'b0;
+ store_m <= 1'b0;
+ direction_m <= 1'b0;
- write_enable_m <= 1'b0;
- write_idx_m <= { 5{1'b0}};
- condition_met_m <= 1'b0;
-
+ write_enable_m <= 1'b0;
+ write_idx_m <= {5{1'b0}};
+ condition_met_m <= 1'b0;
+
-
-
-
- debug_exception_m <= 1'b0;
- non_debug_exception_m <= 1'b0;
+ debug_exception_m <= 1'b0;
+ non_debug_exception_m <= 1'b0;
- operand_w <= { 32{1'b0}};
- w_result_sel_load_w <= 1'b0;
-
-
- w_result_sel_mul_w <= 1'b0;
+ operand_w <= {32{1'b0}};
+ w_result_sel_load_w <= 1'b0;
+ w_result_sel_mul_w <= 1'b0;
- write_idx_w <= { 5{1'b0}};
- write_enable_w <= 1'b0;
-
-
- debug_exception_w <= 1'b0;
- non_debug_exception_w <= 1'b0;
+ write_idx_w <= {5{1'b0}};
+ write_enable_w <= 1'b0;
-
-
+ debug_exception_w <= 1'b0;
+ non_debug_exception_w <= 1'b0;
-
+
+
end
else
begin
- if (stall_x == 1'b0)
+ if (stall_x == 1'b0)
begin
-
+
-
operand_0_x <= d_result_0;
operand_1_x <= d_result_1;
store_operand_x <= bypass_data_1;
- branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;
+ branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] : branch_target_d;
x_result_sel_csr_x <= x_result_sel_csr_d;
-
+
-
-
+
-
-
-
- x_result_sel_sext_x <= x_result_sel_sext_d;
+ x_result_sel_sext_x <= x_result_sel_sext_d;
x_result_sel_logic_x <= x_result_sel_logic_d;
-
+
-
x_result_sel_add_x <= x_result_sel_add_d;
m_result_sel_compare_x <= m_result_sel_compare_d;
-
-
- m_result_sel_shift_x <= m_result_sel_shift_d;
+ m_result_sel_shift_x <= m_result_sel_shift_d;
w_result_sel_load_x <= w_result_sel_load_d;
-
-
- w_result_sel_mul_x <= w_result_sel_mul_d;
+ w_result_sel_mul_x <= w_result_sel_mul_d;
x_bypass_enable_x <= x_bypass_enable_d;
m_bypass_enable_x <= m_bypass_enable_d;
@@ -67712,191 +61600,155 @@ begin
adder_op_x <= adder_op_d;
adder_op_x_n <= ~adder_op_d;
logic_op_x <= logic_op_d;
-
-
- direction_x <= direction_d;
+ direction_x <= direction_d;
-
+
-
condition_x <= condition_d;
csr_write_enable_x <= csr_write_enable_d;
-
-
- break_x <= break_d;
+ break_x <= break_d;
scall_x <= scall_d;
-
+
-
eret_x <= eret_d;
-
-
- bret_x <= bret_d;
+ bret_x <= bret_d;
write_enable_x <= write_enable_d;
end
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
operand_m <= x_result;
m_result_sel_compare_m <= m_result_sel_compare_x;
-
-
- m_result_sel_shift_m <= m_result_sel_shift_x;
+ m_result_sel_shift_m <= m_result_sel_shift_x;
- if (exception_x == 1'b1)
+ if (exception_x == 1'b1)
begin
- w_result_sel_load_m <= 1'b0;
-
-
- w_result_sel_mul_m <= 1'b0;
+ w_result_sel_load_m <= 1'b0;
+ w_result_sel_mul_m <= 1'b0;
end
else
begin
w_result_sel_load_m <= w_result_sel_load_x;
-
-
- w_result_sel_mul_m <= w_result_sel_mul_x;
+ w_result_sel_mul_m <= w_result_sel_mul_x;
end
m_bypass_enable_m <= m_bypass_enable_x;
-
-
- direction_m <= direction_x;
+ direction_m <= direction_x;
load_m <= load_x;
store_m <= store_x;
-
+
-
branch_m <= branch_x;
branch_predict_m <= branch_predict_x;
branch_predict_taken_m <= branch_predict_taken_x;
-
-
-
+
- if (non_debug_exception_x == 1'b1)
- write_idx_m <= 5'd30;
- else if (debug_exception_x == 1'b1)
- write_idx_m <= 5'd31;
+ if (non_debug_exception_x == 1'b1)
+ write_idx_m <= 5'd30;
+ else if (debug_exception_x == 1'b1)
+ write_idx_m <= 5'd31;
else
write_idx_m <= write_idx_x;
-
+
-
condition_met_m <= condition_met_x;
-
-
- if (exception_x == 1'b1)
- if ((dc_re == 1'b1)
- || ((debug_exception_x == 1'b1)
- && (non_debug_exception_x == 1'b0)))
+
+ if (exception_x == 1'b1)
+ if ((dc_re == 1'b1)
+ || ((debug_exception_x == 1'b1)
+ && (non_debug_exception_x == 1'b0)))
branch_target_m <= {deba, eid_x, {3{1'b0}}};
else
branch_target_m <= {eba, eid_x, {3{1'b0}}};
else
branch_target_m <= branch_target_x;
-
-
+
-
+
-
-
+
-
eret_m <= eret_q_x;
-
-
- bret_m <= bret_q_x;
+ bret_m <= bret_q_x;
- write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
-
-
+ write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
+
debug_exception_m <= debug_exception_x;
non_debug_exception_m <= non_debug_exception_x;
-
end
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
- if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
- exception_m <= 1'b1;
+ if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
+ exception_m <= 1'b1;
else
- exception_m <= 1'b0;
-
+ exception_m <= 1'b0;
+
-
end
-
+
-
- operand_w <= exception_m == 1'b1 ? {pc_m, 2'b00} : m_result;
-
+ operand_w <= exception_m == 1'b1 ? {pc_m, 2'b00} : m_result;
w_result_sel_load_w <= w_result_sel_load_m;
-
-
- w_result_sel_mul_w <= w_result_sel_mul_m;
+ w_result_sel_mul_w <= w_result_sel_mul_m;
write_idx_w <= write_idx_m;
-
+
-
write_enable_w <= write_enable_m;
-
-
+
debug_exception_w <= debug_exception_m;
non_debug_exception_w <= non_debug_exception_m;
-
-
+
-
+
@@ -67904,33 +61756,31 @@ begin
-
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- use_buf <= 1'b0;
- reg_data_buf_0 <= { 32{1'b0}};
- reg_data_buf_1 <= { 32{1'b0}};
+ use_buf <= 1'b0;
+ reg_data_buf_0 <= {32{1'b0}};
+ reg_data_buf_1 <= {32{1'b0}};
end
else
begin
- if (stall_d == 1'b0)
- use_buf <= 1'b0;
- else if (use_buf == 1'b0)
+ if (stall_d == 1'b0)
+ use_buf <= 1'b0;
+ else if (use_buf == 1'b0)
begin
reg_data_buf_0 <= reg_data_live_0;
reg_data_buf_1 <= reg_data_live_1;
- use_buf <= 1'b1;
+ use_buf <= 1'b1;
end
- if (reg_write_enable_q_w == 1'b1)
+ if (reg_write_enable_q_w == 1'b1)
begin
if (write_idx_w == read_idx_0_d)
reg_data_buf_0 <= w_result;
@@ -67939,13 +61789,11 @@ begin
end
end
end
-
-
-
+
@@ -67989,8 +61837,7 @@ end
-
-
+
@@ -68049,7 +61896,6 @@ end
-
@@ -68062,13 +61908,9 @@ end
initial
begin
-
-
- reg_0.ram[0] = { 32{1'b0}};
- reg_1.ram[0] = { 32{1'b0}};
-
+
end
@@ -68116,10 +61958,7 @@ endmodule
-
-
-
-
+
@@ -68149,9 +61988,9 @@ endmodule
-
+
@@ -68436,8 +62275,6 @@ endmodule
-
-
@@ -68464,14 +62301,12 @@ module lm32_load_store_unit_medium_icache_debug (
store_q_m,
sign_extend_x,
size_x,
-
+
-
-
+
-
d_dat_i,
d_ack_i,
@@ -68479,19 +62314,17 @@ module lm32_load_store_unit_medium_icache_debug (
d_rty_i,
-
+
-
-
+
-
load_data_w,
stall_wb_load,
@@ -68536,9 +62369,9 @@ input kill_x;
input kill_m;
input exception_m;
-input [ (32-1):0] store_operand_x;
-input [ (32-1):0] load_store_address_x;
-input [ (32-1):0] load_store_address_m;
+input [(32-1):0] store_operand_x;
+input [(32-1):0] load_store_address_x;
+input [(32-1):0] load_store_address_m;
input [1:0] load_store_address_w;
input load_x;
input store_x;
@@ -68547,19 +62380,17 @@ input store_q_x;
input load_q_m;
input store_q_m;
input sign_extend_x;
-input [ 1:0] size_x;
+input [1:0] size_x;
-
+
-
-
+
-
-input [ (32-1):0] d_dat_i;
+input [(32-1):0] d_dat_i;
input d_ack_i;
input d_err_i;
input d_rty_i;
@@ -68568,7 +62399,7 @@ input d_rty_i;
-
+
@@ -68579,8 +62410,7 @@ input d_rty_i;
-
-
+
@@ -68589,50 +62419,49 @@ input d_rty_i;
-
-output [ (32-1):0] load_data_w;
-reg [ (32-1):0] load_data_w;
+output [(32-1):0] load_data_w;
+reg [(32-1):0] load_data_w;
output stall_wb_load;
reg stall_wb_load;
-output [ (32-1):0] d_dat_o;
-reg [ (32-1):0] d_dat_o;
-output [ (32-1):0] d_adr_o;
-reg [ (32-1):0] d_adr_o;
+output [(32-1):0] d_dat_o;
+reg [(32-1):0] d_dat_o;
+output [(32-1):0] d_adr_o;
+reg [(32-1):0] d_adr_o;
output d_cyc_o;
reg d_cyc_o;
-output [ (4-1):0] d_sel_o;
-reg [ (4-1):0] d_sel_o;
+output [(4-1):0] d_sel_o;
+reg [(4-1):0] d_sel_o;
output d_stb_o;
reg d_stb_o;
output d_we_o;
reg d_we_o;
-output [ (3-1):0] d_cti_o;
-reg [ (3-1):0] d_cti_o;
+output [(3-1):0] d_cti_o;
+reg [(3-1):0] d_cti_o;
output d_lock_o;
reg d_lock_o;
-output [ (2-1):0] d_bte_o;
-wire [ (2-1):0] d_bte_o;
+output [(2-1):0] d_bte_o;
+wire [(2-1):0] d_bte_o;
-reg [ 1:0] size_m;
-reg [ 1:0] size_w;
+reg [1:0] size_m;
+reg [1:0] size_w;
reg sign_extend_m;
reg sign_extend_w;
-reg [ (32-1):0] store_data_x;
-reg [ (32-1):0] store_data_m;
-reg [ (4-1):0] byte_enable_x;
-reg [ (4-1):0] byte_enable_m;
-wire [ (32-1):0] data_m;
-reg [ (32-1):0] data_w;
+reg [(32-1):0] store_data_x;
+reg [(32-1):0] store_data_m;
+reg [(4-1):0] byte_enable_x;
+reg [(4-1):0] byte_enable_m;
+wire [(32-1):0] data_m;
+reg [(32-1):0] data_w;
-
+
@@ -68643,8 +62472,7 @@ reg [ (32-1):0] data_w;
-
-
+
@@ -68652,25 +62480,21 @@ reg [ (32-1):0] data_w;
-
wire wb_select_x;
-
+
-
reg wb_select_m;
-reg [ (32-1):0] wb_data_m;
+reg [(32-1):0] wb_data_m;
reg wb_load_complete;
-
-
-
+
@@ -68725,8 +62549,7 @@ endfunction
-
-
+
@@ -68810,8 +62633,7 @@ endfunction
-
-
+
@@ -68850,20 +62672,17 @@ endfunction
-
-
+
-
-
+
-
-
+
@@ -68873,32 +62692,28 @@ endfunction
-
- assign wb_select_x = 1'b1
-
+ assign wb_select_x = 1'b1
+
-
-
+
-
-
+
-
;
always @(*)
begin
case (size_x)
- 2'b00: store_data_x = {4{store_operand_x[7:0]}};
- 2'b11: store_data_x = {2{store_operand_x[15:0]}};
- 2'b10: store_data_x = store_operand_x;
- default: store_data_x = { 32{1'bx}};
+ 2'b00: store_data_x = {4{store_operand_x[7:0]}};
+ 2'b11: store_data_x = {2{store_operand_x[15:0]}};
+ 2'b10: store_data_x = store_operand_x;
+ default: store_data_x = {32{1'bx}};
endcase
end
@@ -68906,18 +62721,18 @@ end
always @(*)
begin
casez ({size_x, load_store_address_x[1:0]})
- { 2'b00, 2'b11}: byte_enable_x = 4'b0001;
- { 2'b00, 2'b10}: byte_enable_x = 4'b0010;
- { 2'b00, 2'b01}: byte_enable_x = 4'b0100;
- { 2'b00, 2'b00}: byte_enable_x = 4'b1000;
- { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
- { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
- { 2'b10, 2'b??}: byte_enable_x = 4'b1111;
+ {2'b00, 2'b11}: byte_enable_x = 4'b0001;
+ {2'b00, 2'b10}: byte_enable_x = 4'b0010;
+ {2'b00, 2'b01}: byte_enable_x = 4'b0100;
+ {2'b00, 2'b00}: byte_enable_x = 4'b1000;
+ {2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+ {2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+ {2'b10, 2'b??}: byte_enable_x = 4'b1111;
default: byte_enable_x = 4'bxxxx;
endcase
end
-
+
@@ -68925,8 +62740,7 @@ end
-
-
+
@@ -68934,8 +62748,7 @@ end
-
-
+
@@ -68955,9 +62768,8 @@ end
-
-
+
@@ -68992,8 +62804,7 @@ end
-
-
+
@@ -69008,20 +62819,15 @@ end
-
-
+
-
assign data_m = wb_data_m;
-
-
-
@@ -69029,21 +62835,21 @@ end
always @(*)
begin
casez ({size_w, load_store_address_w[1:0]})
- { 2'b00, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
- { 2'b00, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
- { 2'b00, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
- { 2'b00, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
- { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
- { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
- { 2'b10, 2'b??}: load_data_w = data_w;
- default: load_data_w = { 32{1'bx}};
+ {2'b00, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+ {2'b00, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+ {2'b00, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+ {2'b00, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+ {2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+ {2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+ {2'b10, 2'b??}: load_data_w = data_w;
+ default: load_data_w = {32{1'bx}};
endcase
end
-assign d_bte_o = 2'b00;
+assign d_bte_o = 2'b00;
-
+
@@ -69077,74 +62883,69 @@ assign d_bte_o = 2'b00;
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- d_cyc_o <= 1'b0;
- d_stb_o <= 1'b0;
- d_dat_o <= { 32{1'b0}};
- d_adr_o <= { 32{1'b0}};
- d_sel_o <= { 4{ 1'b0}};
- d_we_o <= 1'b0;
- d_cti_o <= 3'b111;
- d_lock_o <= 1'b0;
- wb_data_m <= { 32{1'b0}};
- wb_load_complete <= 1'b0;
- stall_wb_load <= 1'b0;
-
+ d_cyc_o <= 1'b0;
+ d_stb_o <= 1'b0;
+ d_dat_o <= {32{1'b0}};
+ d_adr_o <= {32{1'b0}};
+ d_sel_o <= {4{1'b0}};
+ d_we_o <= 1'b0;
+ d_cti_o <= 3'b111;
+ d_lock_o <= 1'b0;
+ wb_data_m <= {32{1'b0}};
+ wb_load_complete <= 1'b0;
+ stall_wb_load <= 1'b0;
+
-
end
else
begin
-
+
-
- if (d_cyc_o == 1'b1)
+ if (d_cyc_o == 1'b1)
begin
- if ((d_ack_i == 1'b1) || (d_err_i == 1'b1))
+ if ((d_ack_i == 1'b1) || (d_err_i == 1'b1))
begin
-
+
-
begin
- d_cyc_o <= 1'b0;
- d_stb_o <= 1'b0;
- d_lock_o <= 1'b0;
+ d_cyc_o <= 1'b0;
+ d_stb_o <= 1'b0;
+ d_lock_o <= 1'b0;
end
-
+
-
wb_data_m <= d_dat_i;
wb_load_complete <= !d_we_o;
end
- if (d_err_i == 1'b1)
+ if (d_err_i == 1'b1)
$display ("Data bus error. Address: %x", d_adr_o);
end
else
begin
-
+
@@ -69157,115 +62958,106 @@ begin
-
- if ( (store_q_m == 1'b1)
- && (stall_m == 1'b0)
-
+ if ( (store_q_m == 1'b1)
+ && (stall_m == 1'b0)
+
-
-
+
-
)
begin
d_dat_o <= store_data_m;
d_adr_o <= load_store_address_m;
- d_cyc_o <= 1'b1;
+ d_cyc_o <= 1'b1;
d_sel_o <= byte_enable_m;
- d_stb_o <= 1'b1;
- d_we_o <= 1'b1;
- d_cti_o <= 3'b111;
+ d_stb_o <= 1'b1;
+ d_we_o <= 1'b1;
+ d_cti_o <= 3'b111;
end
- else if ( (load_q_m == 1'b1)
- && (wb_select_m == 1'b1)
- && (wb_load_complete == 1'b0)
+ else if ( (load_q_m == 1'b1)
+ && (wb_select_m == 1'b1)
+ && (wb_load_complete == 1'b0)
)
begin
- stall_wb_load <= 1'b0;
+ stall_wb_load <= 1'b0;
d_adr_o <= load_store_address_m;
- d_cyc_o <= 1'b1;
+ d_cyc_o <= 1'b1;
d_sel_o <= byte_enable_m;
- d_stb_o <= 1'b1;
- d_we_o <= 1'b0;
- d_cti_o <= 3'b111;
+ d_stb_o <= 1'b1;
+ d_we_o <= 1'b0;
+ d_cti_o <= 3'b111;
end
end
- if (stall_m == 1'b0)
- wb_load_complete <= 1'b0;
+ if (stall_m == 1'b0)
+ wb_load_complete <= 1'b0;
- if ((load_q_x == 1'b1) && (wb_select_x == 1'b1) && (stall_x == 1'b0))
- stall_wb_load <= 1'b1;
+ if ((load_q_x == 1'b1) && (wb_select_x == 1'b1) && (stall_x == 1'b0))
+ stall_wb_load <= 1'b1;
- if ((kill_m == 1'b1) || (exception_m == 1'b1))
- stall_wb_load <= 1'b0;
+ if ((kill_m == 1'b1) || (exception_m == 1'b1))
+ stall_wb_load <= 1'b0;
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- sign_extend_m <= 1'b0;
+ sign_extend_m <= 1'b0;
size_m <= 2'b00;
- byte_enable_m <= 1'b0;
- store_data_m <= { 32{1'b0}};
-
+ byte_enable_m <= 1'b0;
+ store_data_m <= {32{1'b0}};
+
-
-
+
-
-
+
-
- wb_select_m <= 1'b0;
+ wb_select_m <= 1'b0;
end
else
begin
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
sign_extend_m <= sign_extend_x;
size_m <= size_x;
byte_enable_m <= byte_enable_x;
store_data_m <= store_data_x;
-
+
-
-
+
-
-
+
-
wb_select_m <= wb_select_x;
end
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
size_w <= 2'b00;
- data_w <= { 32{1'b0}};
- sign_extend_w <= 1'b0;
+ data_w <= {32{1'b0}};
+ sign_extend_w <= 1'b0;
end
else
begin
@@ -69284,11 +63076,11 @@ end
always @(posedge clk_i)
begin
- if (((load_q_m == 1'b1) || (store_q_m == 1'b1)) && (stall_m == 1'b0))
+ if (((load_q_m == 1'b1) || (store_q_m == 1'b1)) && (stall_m == 1'b0))
begin
- if ((size_m === 2'b11) && (load_store_address_m[0] !== 1'b0))
+ if ((size_m === 2'b11) && (load_store_address_m[0] !== 1'b0))
$display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
- if ((size_m === 2'b10) && (load_store_address_m[1:0] !== 2'b00))
+ if ((size_m === 2'b10) && (load_store_address_m[1:0] !== 2'b00))
$display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
end
end
@@ -69330,9 +63122,7 @@ endmodule
-
-
-
+
@@ -69363,9 +63153,8 @@ endmodule
-
-
+
@@ -69650,104 +63439,55 @@ endmodule
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -69760,36 +63500,27 @@ module lm32_decoder_medium_icache_debug (
d_result_sel_0,
d_result_sel_1,
x_result_sel_csr,
-
+
-
-
+
-
-
-
- x_result_sel_sext,
+ x_result_sel_sext,
x_result_sel_logic,
-
+
-
x_result_sel_add,
m_result_sel_compare,
-
-
- m_result_sel_shift,
+ m_result_sel_shift,
w_result_sel_load,
-
-
- w_result_sel_mul,
+ w_result_sel_mul,
x_bypass_enable,
m_bypass_enable,
@@ -69807,46 +63538,36 @@ module lm32_decoder_medium_icache_debug (
sign_extend,
adder_op,
logic_op,
-
-
- direction,
+ direction,
-
+
-
-
+
-
-
+
-
branch,
branch_reg,
condition,
bi_conditional,
bi_unconditional,
-
-
- break_opcode,
+ break_opcode,
scall,
eret,
-
-
- bret,
+ bret,
-
+
-
csr_write_enable
);
@@ -69854,58 +63575,49 @@ module lm32_decoder_medium_icache_debug (
-input [ (32-1):0] instruction;
+input [(32-1):0] instruction;
-output [ 0:0] d_result_sel_0;
-reg [ 0:0] d_result_sel_0;
-output [ 1:0] d_result_sel_1;
-reg [ 1:0] d_result_sel_1;
+output [0:0] d_result_sel_0;
+reg [0:0] d_result_sel_0;
+output [1:0] d_result_sel_1;
+reg [1:0] d_result_sel_1;
output x_result_sel_csr;
reg x_result_sel_csr;
-
+
-
-
+
-
-
-
+
output x_result_sel_sext;
reg x_result_sel_sext;
-
output x_result_sel_logic;
reg x_result_sel_logic;
-
+
-
output x_result_sel_add;
reg x_result_sel_add;
output m_result_sel_compare;
reg m_result_sel_compare;
-
-
+
output m_result_sel_shift;
reg m_result_sel_shift;
-
output w_result_sel_load;
reg w_result_sel_load;
-
-
+
output w_result_sel_mul;
reg w_result_sel_mul;
-
output x_bypass_enable;
wire x_bypass_enable;
@@ -69913,88 +63625,78 @@ output m_bypass_enable;
wire m_bypass_enable;
output read_enable_0;
wire read_enable_0;
-output [ (5-1):0] read_idx_0;
-wire [ (5-1):0] read_idx_0;
+output [(5-1):0] read_idx_0;
+wire [(5-1):0] read_idx_0;
output read_enable_1;
wire read_enable_1;
-output [ (5-1):0] read_idx_1;
-wire [ (5-1):0] read_idx_1;
+output [(5-1):0] read_idx_1;
+wire [(5-1):0] read_idx_1;
output write_enable;
wire write_enable;
-output [ (5-1):0] write_idx;
-wire [ (5-1):0] write_idx;
-output [ (32-1):0] immediate;
-wire [ (32-1):0] immediate;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+output [(5-1):0] write_idx;
+wire [(5-1):0] write_idx;
+output [(32-1):0] immediate;
+wire [(32-1):0] immediate;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_offset;
output load;
wire load;
output store;
wire store;
-output [ 1:0] size;
-wire [ 1:0] size;
+output [1:0] size;
+wire [1:0] size;
output sign_extend;
wire sign_extend;
output adder_op;
wire adder_op;
-output [ 3:0] logic_op;
-wire [ 3:0] logic_op;
-
-
+output [3:0] logic_op;
+wire [3:0] logic_op;
+
output direction;
wire direction;
-
-
+
-
-
+
-
-
+
-
output branch;
wire branch;
output branch_reg;
wire branch_reg;
-output [ (3-1):0] condition;
-wire [ (3-1):0] condition;
+output [(3-1):0] condition;
+wire [(3-1):0] condition;
output bi_conditional;
wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
-
-
+
output break_opcode;
wire break_opcode;
-
output scall;
wire scall;
output eret;
wire eret;
-
-
+
output bret;
wire bret;
-
-
+
-
output csr_write_enable;
wire csr_write_enable;
@@ -70002,10 +63704,10 @@ wire csr_write_enable;
-wire [ (32-1):0] extended_immediate;
-wire [ (32-1):0] high_immediate;
-wire [ (32-1):0] call_immediate;
-wire [ (32-1):0] branch_immediate;
+wire [(32-1):0] extended_immediate;
+wire [(32-1):0] high_immediate;
+wire [(32-1):0] call_immediate;
+wire [(32-1):0] branch_immediate;
wire sign_extend_immediate;
wire select_high_immediate;
wire select_call_immediate;
@@ -70014,9 +63716,7 @@ wire select_call_immediate;
-
-
-
+
@@ -70072,70 +63772,61 @@ endfunction
-
-assign op_add = instruction[ 30:26] == 5'b01101;
-assign op_and = instruction[ 30:26] == 5'b01000;
-assign op_andhi = instruction[ 31:26] == 6'b011000;
-assign op_b = instruction[ 31:26] == 6'b110000;
-assign op_bi = instruction[ 31:26] == 6'b111000;
-assign op_be = instruction[ 31:26] == 6'b010001;
-assign op_bg = instruction[ 31:26] == 6'b010010;
-assign op_bge = instruction[ 31:26] == 6'b010011;
-assign op_bgeu = instruction[ 31:26] == 6'b010100;
-assign op_bgu = instruction[ 31:26] == 6'b010101;
-assign op_bne = instruction[ 31:26] == 6'b010111;
-assign op_call = instruction[ 31:26] == 6'b110110;
-assign op_calli = instruction[ 31:26] == 6'b111110;
-assign op_cmpe = instruction[ 30:26] == 5'b11001;
-assign op_cmpg = instruction[ 30:26] == 5'b11010;
-assign op_cmpge = instruction[ 30:26] == 5'b11011;
-assign op_cmpgeu = instruction[ 30:26] == 5'b11100;
-assign op_cmpgu = instruction[ 30:26] == 5'b11101;
-assign op_cmpne = instruction[ 30:26] == 5'b11111;
-
+assign op_add = instruction[30:26] == 5'b01101;
+assign op_and = instruction[30:26] == 5'b01000;
+assign op_andhi = instruction[31:26] == 6'b011000;
+assign op_b = instruction[31:26] == 6'b110000;
+assign op_bi = instruction[31:26] == 6'b111000;
+assign op_be = instruction[31:26] == 6'b010001;
+assign op_bg = instruction[31:26] == 6'b010010;
+assign op_bge = instruction[31:26] == 6'b010011;
+assign op_bgeu = instruction[31:26] == 6'b010100;
+assign op_bgu = instruction[31:26] == 6'b010101;
+assign op_bne = instruction[31:26] == 6'b010111;
+assign op_call = instruction[31:26] == 6'b110110;
+assign op_calli = instruction[31:26] == 6'b111110;
+assign op_cmpe = instruction[30:26] == 5'b11001;
+assign op_cmpg = instruction[30:26] == 5'b11010;
+assign op_cmpge = instruction[30:26] == 5'b11011;
+assign op_cmpgeu = instruction[30:26] == 5'b11100;
+assign op_cmpgu = instruction[30:26] == 5'b11101;
+assign op_cmpne = instruction[30:26] == 5'b11111;
+
-
-assign op_lb = instruction[ 31:26] == 6'b000100;
-assign op_lbu = instruction[ 31:26] == 6'b010000;
-assign op_lh = instruction[ 31:26] == 6'b000111;
-assign op_lhu = instruction[ 31:26] == 6'b001011;
-assign op_lw = instruction[ 31:26] == 6'b001010;
-
+assign op_lb = instruction[31:26] == 6'b000100;
+assign op_lbu = instruction[31:26] == 6'b010000;
+assign op_lh = instruction[31:26] == 6'b000111;
+assign op_lhu = instruction[31:26] == 6'b001011;
+assign op_lw = instruction[31:26] == 6'b001010;
+
-
-
-
-assign op_mul = instruction[ 30:26] == 5'b00010;
+assign op_mul = instruction[30:26] == 5'b00010;
-assign op_nor = instruction[ 30:26] == 5'b00001;
-assign op_or = instruction[ 30:26] == 5'b01110;
-assign op_orhi = instruction[ 31:26] == 6'b011110;
-assign op_raise = instruction[ 31:26] == 6'b101011;
-assign op_rcsr = instruction[ 31:26] == 6'b100100;
-assign op_sb = instruction[ 31:26] == 6'b001100;
-
-
-assign op_sextb = instruction[ 31:26] == 6'b101100;
-assign op_sexth = instruction[ 31:26] == 6'b110111;
+assign op_nor = instruction[30:26] == 5'b00001;
+assign op_or = instruction[30:26] == 5'b01110;
+assign op_orhi = instruction[31:26] == 6'b011110;
+assign op_raise = instruction[31:26] == 6'b101011;
+assign op_rcsr = instruction[31:26] == 6'b100100;
+assign op_sb = instruction[31:26] == 6'b001100;
+assign op_sextb = instruction[31:26] == 6'b101100;
+assign op_sexth = instruction[31:26] == 6'b110111;
-assign op_sh = instruction[ 31:26] == 6'b000011;
-
-
-assign op_sl = instruction[ 30:26] == 5'b01111;
+assign op_sh = instruction[31:26] == 6'b000011;
+assign op_sl = instruction[30:26] == 5'b01111;
-assign op_sr = instruction[ 30:26] == 5'b00101;
-assign op_sru = instruction[ 30:26] == 5'b00000;
-assign op_sub = instruction[ 31:26] == 6'b110010;
-assign op_sw = instruction[ 31:26] == 6'b010110;
-assign op_user = instruction[ 31:26] == 6'b110011;
-assign op_wcsr = instruction[ 31:26] == 6'b110100;
-assign op_xnor = instruction[ 30:26] == 5'b01001;
-assign op_xor = instruction[ 30:26] == 5'b00110;
+assign op_sr = instruction[30:26] == 5'b00101;
+assign op_sru = instruction[30:26] == 5'b00000;
+assign op_sub = instruction[31:26] == 6'b110010;
+assign op_sw = instruction[31:26] == 6'b010110;
+assign op_user = instruction[31:26] == 6'b110011;
+assign op_wcsr = instruction[31:26] == 6'b110100;
+assign op_xnor = instruction[30:26] == 5'b01001;
+assign op_xor = instruction[30:26] == 5'b00110;
assign arith = op_add | op_sub;
@@ -70145,35 +63836,26 @@ assign bi_conditional = op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne;
assign bi_unconditional = op_bi;
assign bra = op_b | bi_unconditional | bi_conditional;
assign call = op_call | op_calli;
-
-
-assign shift = op_sl | op_sr | op_sru;
+assign shift = op_sl | op_sr | op_sru;
-
+
-
-
+
-
-
-
-assign sext = op_sextb | op_sexth;
+assign sext = op_sextb | op_sexth;
-
-
-assign multiply = op_mul;
+assign multiply = op_mul;
-
+
-
assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
assign store = op_sb | op_sh | op_sw;
@@ -70182,39 +63864,34 @@ always @(*)
begin
if (call)
- d_result_sel_0 = 1'b1;
+ d_result_sel_0 = 1'b1;
else
- d_result_sel_0 = 1'b0;
+ d_result_sel_0 = 1'b0;
if (call)
- d_result_sel_1 = 2'b00;
+ d_result_sel_1 = 2'b00;
else if ((instruction[31] == 1'b0) && !bra)
- d_result_sel_1 = 2'b10;
+ d_result_sel_1 = 2'b10;
else
- d_result_sel_1 = 2'b01;
+ d_result_sel_1 = 2'b01;
- x_result_sel_csr = 1'b0;
-
+ x_result_sel_csr = 1'b0;
+
-
-
+
-
-
-
- x_result_sel_sext = 1'b0;
+ x_result_sel_sext = 1'b0;
- x_result_sel_logic = 1'b0;
-
+ x_result_sel_logic = 1'b0;
+
-
- x_result_sel_add = 1'b0;
+ x_result_sel_add = 1'b0;
if (op_rcsr)
- x_result_sel_csr = 1'b1;
-
+ x_result_sel_csr = 1'b1;
+
@@ -70228,84 +63905,66 @@ begin
-
-
+
-
-
-
- else if (sext)
- x_result_sel_sext = 1'b1;
+ else if (sext)
+ x_result_sel_sext = 1'b1;
else if (logical)
- x_result_sel_logic = 1'b1;
-
+ x_result_sel_logic = 1'b1;
+
-
else
- x_result_sel_add = 1'b1;
+ x_result_sel_add = 1'b1;
m_result_sel_compare = cmp;
-
-
- m_result_sel_shift = shift;
+ m_result_sel_shift = shift;
w_result_sel_load = load;
-
-
- w_result_sel_mul = op_mul;
+ w_result_sel_mul = op_mul;
end
assign x_bypass_enable = arith
| logical
-
+
-
-
+
-
-
+
-
-
+
-
-
-
- | sext
+ | sext
-
+
-
| op_rcsr
;
assign m_bypass_enable = x_bypass_enable
-
-
- | shift
+ | shift
| cmp
;
@@ -70331,34 +63990,27 @@ assign sign_extend = instruction[28];
assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
assign logic_op = instruction[29:26];
-
-
+
assign direction = instruction[29];
-
assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
-
-
-assign break_opcode = op_raise & ~instruction[2];
+assign break_opcode = op_raise & ~instruction[2];
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
-
-
-assign bret = op_b & (instruction[25:21] == 5'd31);
+assign bret = op_b & (instruction[25:21] == 5'd31);
-
+
-
assign csr_write_enable = op_wcsr;
@@ -70372,11 +64024,11 @@ assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, inst
assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
-assign immediate = select_high_immediate == 1'b1
+assign immediate = select_high_immediate == 1'b1
? high_immediate
: extended_immediate;
-assign branch_offset = select_call_immediate == 1'b1
+assign branch_offset = select_call_immediate == 1'b1
? call_immediate
: branch_immediate;
@@ -70417,10 +64069,7 @@ endmodule
-
-
-
-
+
@@ -70450,9 +64099,9 @@ endmodule
-
+
@@ -70736,48 +64385,28 @@ endmodule
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
-
+
+
+
+
+
+
+
+
+
@@ -70795,10 +64424,9 @@ module lm32_icache_medium_icache_debug (
refill_ready,
refill_data,
iflush,
-
+
-
valid_d,
branch_predict_taken_d,
@@ -70827,7 +64455,7 @@ localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
localparam addr_set_lsb = (addr_offset_msb+1);
localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
localparam addr_tag_lsb = (addr_set_msb+1);
-localparam addr_tag_msb = clogb2( 32'h7fffffff- 32'h0)-1;
+localparam addr_tag_msb = clogb2(32'h7fffffff-32'h0)-1;
localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
@@ -70843,18 +64471,17 @@ input stall_f;
input valid_d;
input branch_predict_taken_d;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_a;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] address_f;
input read_enable_f;
input refill_ready;
-input [ (32-1):0] refill_data;
+input [(32-1):0] refill_data;
input iflush;
-
+
-
@@ -70866,12 +64493,12 @@ output restart_request;
reg restart_request;
output refill_request;
wire refill_request;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] refill_address;
output refilling;
reg refilling;
-output [ (32-1):0] inst;
-wire [ (32-1):0] inst;
+output [(32-1):0] inst;
+wire [(32-1):0] inst;
@@ -70879,27 +64506,27 @@ wire [ (32-1):0] inst;
wire enable;
wire [0:associativity-1] way_mem_we;
-wire [ (32-1):0] way_data[0:associativity-1];
-wire [ ((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
+wire [(32-1):0] way_data[0:associativity-1];
+wire [((addr_tag_width+1)-1):1] way_tag[0:associativity-1];
wire [0:associativity-1] way_valid;
wire [0:associativity-1] way_match;
wire miss;
-wire [ (addr_set_width-1):0] tmem_read_address;
-wire [ (addr_set_width-1):0] tmem_write_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
-wire [ ((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
-wire [ ((addr_tag_width+1)-1):0] tmem_write_data;
+wire [(addr_set_width-1):0] tmem_read_address;
+wire [(addr_set_width-1):0] tmem_write_address;
+wire [((addr_offset_width+addr_set_width)-1):0] dmem_read_address;
+wire [((addr_offset_width+addr_set_width)-1):0] dmem_write_address;
+wire [((addr_tag_width+1)-1):0] tmem_write_data;
-reg [ 3:0] state;
+reg [3:0] state;
wire flushing;
wire check;
wire refill;
reg [associativity-1:0] refill_way_select;
-reg [ addr_offset_msb:addr_offset_lsb] refill_offset;
+reg [addr_offset_msb:addr_offset_lsb] refill_offset;
wire last_refill;
-reg [ (addr_set_width-1):0] flush_set;
+reg [(addr_set_width-1):0] flush_set;
genvar i;
@@ -70907,9 +64534,7 @@ genvar i;
-
-
-
+
@@ -70964,7 +64589,6 @@ endfunction
-
generate
for (i = 0; i < associativity; i = i + 1)
begin : memories
@@ -70973,7 +64597,7 @@ endfunction
#(
.data_width (32),
- .address_width ( (addr_offset_width+addr_set_width))
+ .address_width ((addr_offset_width+addr_set_width))
)
way_0_data_ram
@@ -70985,7 +64609,7 @@ endfunction
.read_address (dmem_read_address),
.enable_read (enable),
.write_address (dmem_write_address),
- .enable_write ( 1'b1),
+ .enable_write (1'b1),
.write_enable (way_mem_we[i]),
.write_data (refill_data),
@@ -70995,8 +64619,8 @@ endfunction
lm32_ram
#(
- .data_width ( (addr_tag_width+1)),
- .address_width ( addr_set_width)
+ .data_width ((addr_tag_width+1)),
+ .address_width (addr_set_width)
)
way_0_tag_ram
@@ -71008,7 +64632,7 @@ endfunction
.read_address (tmem_read_address),
.enable_read (enable),
.write_address (tmem_write_address),
- .enable_write ( 1'b1),
+ .enable_write (1'b1),
.write_enable (way_mem_we[i] | flushing),
.write_data (tmem_write_data),
@@ -71026,7 +64650,7 @@ endgenerate
generate
for (i = 0; i < associativity; i = i + 1)
begin : match
-assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[ addr_tag_msb:addr_tag_lsb], 1'b1});
+assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[addr_tag_msb:addr_tag_lsb], 1'b1});
end
endgenerate
@@ -71045,55 +64669,55 @@ endgenerate
generate
if (bytes_per_line > 4)
-assign dmem_write_address = {refill_address[ addr_set_msb:addr_set_lsb], refill_offset};
+assign dmem_write_address = {refill_address[addr_set_msb:addr_set_lsb], refill_offset};
else
-assign dmem_write_address = refill_address[ addr_set_msb:addr_set_lsb];
+assign dmem_write_address = refill_address[addr_set_msb:addr_set_lsb];
endgenerate
-assign dmem_read_address = address_a[ addr_set_msb:addr_offset_lsb];
+assign dmem_read_address = address_a[addr_set_msb:addr_offset_lsb];
-assign tmem_read_address = address_a[ addr_set_msb:addr_set_lsb];
+assign tmem_read_address = address_a[addr_set_msb:addr_set_lsb];
assign tmem_write_address = flushing
? flush_set
- : refill_address[ addr_set_msb:addr_set_lsb];
+ : refill_address[addr_set_msb:addr_set_lsb];
generate
if (bytes_per_line > 4)
assign last_refill = refill_offset == {addr_offset_width{1'b1}};
else
-assign last_refill = 1'b1;
+assign last_refill = 1'b1;
endgenerate
-assign enable = (stall_a == 1'b0);
+assign enable = (stall_a == 1'b0);
generate
if (associativity == 1)
begin : we_1
-assign way_mem_we[0] = (refill_ready == 1'b1);
+assign way_mem_we[0] = (refill_ready == 1'b1);
end
else
begin : we_2
-assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1);
-assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1);
+assign way_mem_we[0] = (refill_ready == 1'b1) && (refill_way_select[0] == 1'b1);
+assign way_mem_we[1] = (refill_ready == 1'b1) && (refill_way_select[1] == 1'b1);
end
endgenerate
-assign tmem_write_data[ 0] = last_refill & !flushing;
-assign tmem_write_data[ ((addr_tag_width+1)-1):1] = refill_address[ addr_tag_msb:addr_tag_lsb];
+assign tmem_write_data[0] = last_refill & !flushing;
+assign tmem_write_data[((addr_tag_width+1)-1):1] = refill_address[addr_tag_msb:addr_tag_lsb];
assign flushing = |state[1:0];
assign check = state[2];
assign refill = state[3];
-assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d);
-assign stall_request = (check == 1'b0);
-assign refill_request = (refill == 1'b1);
+assign miss = (~(|way_match)) && (read_enable_f == 1'b1) && (stall_f == 1'b0) && !(valid_d && branch_predict_taken_d);
+assign stall_request = (check == 1'b0);
+assign refill_request = (refill == 1'b1);
@@ -71103,13 +64727,13 @@ assign refill_request = (refill == 1'b1);
generate
if (associativity >= 2)
begin : way_select
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
else
begin
- if (miss == 1'b1)
+ if (miss == 1'b1)
refill_way_select <= {refill_way_select[0], refill_way_select[1]};
end
end
@@ -71117,77 +64741,76 @@ end
endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- refilling <= 1'b0;
+ if (rst_i == 1'b1)
+ refilling <= 1'b0;
else
refilling <= refill;
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- state <= 4'b0001;
- flush_set <= { addr_set_width{1'b1}};
- refill_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
- restart_request <= 1'b0;
+ state <= 4'b0001;
+ flush_set <= {addr_set_width{1'b1}};
+ refill_address <= {(clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+ restart_request <= 1'b0;
end
else
begin
case (state)
- 4'b0001:
+ 4'b0001:
begin
- if (flush_set == { addr_set_width{1'b0}})
- state <= 4'b0100;
+ if (flush_set == {addr_set_width{1'b0}})
+ state <= 4'b0100;
flush_set <= flush_set - 1'b1;
end
- 4'b0010:
+ 4'b0010:
begin
- if (flush_set == { addr_set_width{1'b0}})
-
+ if (flush_set == {addr_set_width{1'b0}})
+
-
- state <= 4'b0100;
+ state <= 4'b0100;
flush_set <= flush_set - 1'b1;
end
- 4'b0100:
+ 4'b0100:
begin
- if (stall_a == 1'b0)
- restart_request <= 1'b0;
- if (iflush == 1'b1)
+ if (stall_a == 1'b0)
+ restart_request <= 1'b0;
+ if (iflush == 1'b1)
begin
refill_address <= address_f;
- state <= 4'b0010;
+ state <= 4'b0010;
end
- else if (miss == 1'b1)
+ else if (miss == 1'b1)
begin
refill_address <= address_f;
- state <= 4'b1000;
+ state <= 4'b1000;
end
end
- 4'b1000:
+ 4'b1000:
begin
- if (refill_ready == 1'b1)
+ if (refill_ready == 1'b1)
begin
- if (last_refill == 1'b1)
+ if (last_refill == 1'b1)
begin
- restart_request <= 1'b1;
- state <= 4'b0100;
+ restart_request <= 1'b1;
+ state <= 4'b0100;
end
end
end
@@ -71200,27 +64823,27 @@ generate
if (bytes_per_line > 4)
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
else
begin
case (state)
- 4'b0100:
+ 4'b0100:
begin
- if (iflush == 1'b1)
+ if (iflush == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
- else if (miss == 1'b1)
+ else if (miss == 1'b1)
refill_offset <= {addr_offset_width{1'b0}};
end
- 4'b1000:
+ 4'b1000:
begin
- if (refill_ready == 1'b1)
+ if (refill_ready == 1'b1)
refill_offset <= refill_offset + 1'b1;
end
@@ -71232,7 +64855,6 @@ endgenerate
endmodule
-
@@ -71265,10 +64887,7 @@ endmodule
-
-
-
-
+
@@ -71298,9 +64917,9 @@ endmodule
-
+
@@ -71584,9 +65203,7 @@ endmodule
-
-
-
+
@@ -72091,10 +65708,7 @@ endmodule
-
-
-
-
+
@@ -72125,9 +65739,8 @@ endmodule
-
-
+
@@ -72411,24 +66024,15 @@ endmodule
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
@@ -72445,31 +66049,24 @@ module lm32_debug_medium_icache_debug (
csr_write_enable_x,
csr_write_data,
csr_x,
-
-
+
jtag_csr_write_enable,
jtag_csr_write_data,
jtag_csr,
-
-
-
+
eret_q_x,
bret_q_x,
stall_x,
exception_x,
q_x,
-
+
-
-
-
-
- dc_ss,
+ dc_ss,
dc_re,
bp_match,
@@ -72490,43 +66087,36 @@ parameter watchpoints = 0;
input clk_i;
input rst_i;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
input load_x;
input store_x;
-input [ (32-1):0] load_store_address_x;
+input [(32-1):0] load_store_address_x;
input csr_write_enable_x;
-input [ (32-1):0] csr_write_data;
-input [ (5-1):0] csr_x;
-
-
-input jtag_csr_write_enable;
-input [ (32-1):0] jtag_csr_write_data;
-input [ (5-1):0] jtag_csr;
+input [(32-1):0] csr_write_data;
+input [(5-1):0] csr_x;
+input jtag_csr_write_enable;
+input [(32-1):0] jtag_csr_write_data;
+input [(5-1):0] jtag_csr;
-
-
+
input eret_q_x;
input bret_q_x;
input stall_x;
input exception_x;
input q_x;
-
-
-
-
+
-
+
output dc_ss;
reg dc_ss;
-
output dc_re;
reg dc_re;
@@ -72543,33 +66133,29 @@ genvar i;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] bp_a[0:breakpoints-1];
reg bp_e[0:breakpoints-1];
wire [0:breakpoints-1]bp_match_n;
-reg [ 1:0] wpc_c[0:watchpoints-1];
-reg [ (32-1):0] wp[0:watchpoints-1];
+reg [1:0] wpc_c[0:watchpoints-1];
+reg [(32-1):0] wp[0:watchpoints-1];
wire [0:watchpoints]wp_match_n;
wire debug_csr_write_enable;
-wire [ (32-1):0] debug_csr_write_data;
-wire [ (5-1):0] debug_csr;
+wire [(32-1):0] debug_csr_write_data;
+wire [(5-1):0] debug_csr;
-
+
+reg [2:0] state;
-reg [ 2:0] state;
-
-
-
-
-
+
@@ -72625,27 +66211,24 @@ endfunction
-
generate
for (i = 0; i < breakpoints; i = i + 1)
begin : bp_comb
-assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == 1'b1));
+assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == 1'b1));
end
endgenerate
generate
-
-
+
if (breakpoints > 0)
-assign bp_match = (|bp_match_n) || (state == 3'b011);
+assign bp_match = (|bp_match_n) || (state == 3'b011);
else
-assign bp_match = state == 3'b011;
-
+assign bp_match = state == 3'b011;
+
-
endgenerate
@@ -72659,16 +66242,15 @@ generate
if (watchpoints > 0)
assign wp_match = |wp_match_n;
else
-assign wp_match = 1'b0;
+assign wp_match = 1'b0;
endgenerate
-
-
+
+
+assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1);
+assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data;
+assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
-assign debug_csr_write_enable = (csr_write_enable_x == 1'b1) || (jtag_csr_write_enable == 1'b1);
-assign debug_csr_write_data = jtag_csr_write_enable == 1'b1 ? jtag_csr_write_data : csr_write_data;
-assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
-
@@ -72679,22 +66261,21 @@ assign debug_csr = jtag_csr_write_enable == 1'b1 ? jtag_csr : csr_x;
-
generate
for (i = 0; i < breakpoints; i = i + 1)
begin : bp_seq
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- bp_a[i] <= { (clogb2(32'h7fffffff-32'h0)-2){1'bx}};
- bp_e[i] <= 1'b0;
+ bp_a[i] <= {(clogb2(32'h7fffffff-32'h0)-2){1'bx}};
+ bp_e[i] <= 1'b0;
end
else
begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i))
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h10 + i))
begin
- bp_a[i] <= debug_csr_write_data[ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
+ bp_a[i] <= debug_csr_write_data[((clogb2(32'h7fffffff-32'h0)-2)+2-1):2];
bp_e[i] <= debug_csr_write_data[0];
end
end
@@ -72706,20 +66287,20 @@ endgenerate
generate
for (i = 0; i < watchpoints; i = i + 1)
begin : wp_seq
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- wp[i] <= { 32{1'bx}};
- wpc_c[i] <= 2'b00;
+ wp[i] <= {32{1'bx}};
+ wpc_c[i] <= 2'b00;
end
else
begin
- if (debug_csr_write_enable == 1'b1)
+ if (debug_csr_write_enable == 1'b1)
begin
- if (debug_csr == 5'h8)
+ if (debug_csr == 5'h8)
wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
- if (debug_csr == 5'h18 + i)
+ if (debug_csr == 5'h18 + i)
wp[i] <= debug_csr_write_data;
end
end
@@ -72728,92 +66309,84 @@ end
endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- dc_re <= 1'b0;
+ if (rst_i == 1'b1)
+ dc_re <= 1'b0;
else
begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
dc_re <= debug_csr_write_data[1];
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- state <= 3'b000;
- dc_ss <= 1'b0;
+ state <= 3'b000;
+ dc_ss <= 1'b0;
end
else
begin
- if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
+ if ((debug_csr_write_enable == 1'b1) && (debug_csr == 5'h8))
begin
dc_ss <= debug_csr_write_data[0];
- if (debug_csr_write_data[0] == 1'b0)
- state <= 3'b000;
+ if (debug_csr_write_data[0] == 1'b0)
+ state <= 3'b000;
else
- state <= 3'b001;
+ state <= 3'b001;
end
case (state)
- 3'b001:
+ 3'b001:
begin
- if ( ( (eret_q_x == 1'b1)
- || (bret_q_x == 1'b1)
+ if ( ( (eret_q_x == 1'b1)
+ || (bret_q_x == 1'b1)
)
- && (stall_x == 1'b0)
+ && (stall_x == 1'b0)
)
- state <= 3'b010;
+ state <= 3'b010;
end
- 3'b010:
+ 3'b010:
begin
- if ((q_x == 1'b1) && (stall_x == 1'b0))
- state <= 3'b011;
+ if ((q_x == 1'b1) && (stall_x == 1'b0))
+ state <= 3'b011;
end
- 3'b011:
+ 3'b011:
begin
-
+
-
- if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
+ if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
begin
- dc_ss <= 1'b0;
- state <= 3'b100;
+ dc_ss <= 1'b0;
+ state <= 3'b100;
end
end
- 3'b100:
+ 3'b100:
begin
-
+
-
- state <= 3'b000;
+ state <= 3'b000;
end
endcase
end
end
-
endmodule
-
-
-
-
@@ -72858,10 +66431,10 @@ endmodule
-
+
@@ -72891,9 +66464,9 @@ endmodule
-
+
@@ -73178,8 +66751,6 @@ endmodule
-
-
@@ -73198,48 +66769,39 @@ module lm32_instruction_unit_medium_icache_debug (
kill_f,
branch_predict_taken_d,
branch_predict_address_d,
-
+
-
exception_m,
branch_taken_m,
branch_mispredict_taken_m,
branch_target_m,
-
-
- iflush,
+ iflush,
-
+
-
-
+
-
-
-
+
i_dat_i,
i_ack_i,
i_err_i,
i_rty_i,
-
-
-
+
jtag_read_enable,
jtag_write_enable,
jtag_write_data,
jtag_address,
-
@@ -73248,20 +66810,16 @@ module lm32_instruction_unit_medium_icache_debug (
pc_x,
pc_m,
pc_w,
-
-
+
icache_stall_request,
icache_restart_request,
icache_refill_request,
icache_refilling,
-
-
+
-
-
-
+
i_dat_o,
i_adr_o,
@@ -73272,22 +66830,16 @@ module lm32_instruction_unit_medium_icache_debug (
i_cti_o,
i_lock_o,
i_bte_o,
-
-
-
+
jtag_read_data,
jtag_access_complete,
-
-
+
-
-
-
- instruction_f,
+ instruction_f,
instruction_d
);
@@ -73324,72 +66876,62 @@ input valid_d;
input kill_f;
input branch_predict_taken_d;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_predict_address_d;
-
+
-
input exception_m;
input branch_taken_m;
input branch_mispredict_taken_m;
-input [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
-
-
+input [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] branch_target_m;
-input iflush;
+input iflush;
-
+
-
-
+
-
-
-
-input [ (32-1):0] i_dat_i;
+
+input [(32-1):0] i_dat_i;
input i_ack_i;
input i_err_i;
input i_rty_i;
-
-
-
+
input jtag_read_enable;
input jtag_write_enable;
-input [ 7:0] jtag_write_data;
-input [ (32-1):0] jtag_address;
-
+input [7:0] jtag_write_data;
+input [(32-1):0] jtag_address;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
-output [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
-
-
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_f;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_d;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_x;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_m;
+output [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_w;
+
output icache_stall_request;
wire icache_stall_request;
output icache_restart_request;
@@ -73398,138 +66940,111 @@ output icache_refill_request;
wire icache_refill_request;
output icache_refilling;
wire icache_refilling;
-
-
+
-
-
-
-output [ (32-1):0] i_dat_o;
-
-
-reg [ (32-1):0] i_dat_o;
-
+output [(32-1):0] i_dat_o;
+
+reg [(32-1):0] i_dat_o;
+
-output [ (32-1):0] i_adr_o;
-reg [ (32-1):0] i_adr_o;
+output [(32-1):0] i_adr_o;
+reg [(32-1):0] i_adr_o;
output i_cyc_o;
reg i_cyc_o;
-output [ (4-1):0] i_sel_o;
-
-
-reg [ (4-1):0] i_sel_o;
+output [(4-1):0] i_sel_o;
-
+reg [(4-1):0] i_sel_o;
+
output i_stb_o;
reg i_stb_o;
output i_we_o;
-
-
-reg i_we_o;
-
+reg i_we_o;
+
-output [ (3-1):0] i_cti_o;
-reg [ (3-1):0] i_cti_o;
+output [(3-1):0] i_cti_o;
+reg [(3-1):0] i_cti_o;
output i_lock_o;
reg i_lock_o;
-output [ (2-1):0] i_bte_o;
-wire [ (2-1):0] i_bte_o;
-
-
+output [(2-1):0] i_bte_o;
+wire [(2-1):0] i_bte_o;
-
-output [ 7:0] jtag_read_data;
-reg [ 7:0] jtag_read_data;
+
+output [7:0] jtag_read_data;
+reg [7:0] jtag_read_data;
output jtag_access_complete;
wire jtag_access_complete;
-
-
+
-
-
-
-output [ (32-1):0] instruction_f;
-wire [ (32-1):0] instruction_f;
+output [(32-1):0] instruction_f;
+wire [(32-1):0] instruction_f;
-output [ (32-1):0] instruction_d;
-reg [ (32-1):0] instruction_d;
+output [(32-1):0] instruction_d;
+reg [(32-1):0] instruction_d;
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] pc_a;
-
-
-reg [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;
+reg [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] restart_address;
-
-
+
wire icache_read_enable_f;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] icache_refill_address;
reg icache_refill_ready;
-reg [ (32-1):0] icache_refill_data;
-wire [ (32-1):0] icache_data_f;
-wire [ (3-1):0] first_cycle_type;
-wire [ (3-1):0] next_cycle_type;
+reg [(32-1):0] icache_refill_data;
+wire [(32-1):0] icache_data_f;
+wire [(3-1):0] first_cycle_type;
+wire [(3-1):0] next_cycle_type;
wire last_word;
-wire [ ((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;
-
+wire [((clogb2(32'h7fffffff-32'h0)-2)+2-1):2] first_address;
+
-
-
+
-
-
-
-
+
-
+
-
-
-
-reg jtag_access;
+reg jtag_access;
-
-
-
+
@@ -73585,8 +67100,7 @@ endfunction
-
-
+
@@ -73632,11 +67146,9 @@ endfunction
-
-
-
+
lm32_icache_medium_icache_debug #(
.associativity (associativity),
@@ -73666,81 +67178,68 @@ lm32_icache_medium_icache_debug #(
.refilling (icache_refilling),
.inst (icache_data_f)
);
-
-
-
+
-assign icache_read_enable_f = (valid_f == 1'b1)
- && (kill_f == 1'b0)
-
+assign icache_read_enable_f = (valid_f == 1'b1)
+ && (kill_f == 1'b0)
+
-
-
+
-
;
-
always @(*)
begin
-
+
-
- if (branch_taken_m == 1'b1)
- if ((branch_mispredict_taken_m == 1'b1) && (exception_m == 1'b0))
+ if (branch_taken_m == 1'b1)
+ if ((branch_mispredict_taken_m == 1'b1) && (exception_m == 1'b0))
pc_a = pc_x;
else
pc_a = branch_target_m;
-
+
-
else
- if ( (valid_d == 1'b1) && (branch_predict_taken_d == 1'b1) )
+ if ( (valid_d == 1'b1) && (branch_predict_taken_d == 1'b1) )
pc_a = branch_predict_address_d;
else
-
-
- if (icache_restart_request == 1'b1)
+
+ if (icache_restart_request == 1'b1)
pc_a = restart_address;
else
-
pc_a = pc_f + 1'b1;
end
-
+
-
-
-
-
+
+
-
assign instruction_f = icache_data_f;
-
-
+
@@ -73753,50 +67252,43 @@ assign instruction_f = icache_data_f;
-
-
-
-
-
+
+
-
-assign i_bte_o = 2'b00;
-
+assign i_bte_o = 2'b00;
-
-
+
generate
case (bytes_per_line)
4:
begin
-assign first_cycle_type = 3'b111;
-assign next_cycle_type = 3'b111;
-assign last_word = 1'b1;
+assign first_cycle_type = 3'b111;
+assign next_cycle_type = 3'b111;
+assign last_word = 1'b1;
assign first_address = icache_refill_address;
end
8:
begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = 3'b111;
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = 3'b111;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
-assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+assign first_address = {icache_refill_address[(clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
end
16:
begin
-assign first_cycle_type = 3'b010;
-assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
+assign first_cycle_type = 3'b010;
+assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? 3'b111 : 3'b010;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
-assign first_address = {icache_refill_address[ (clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
+assign first_address = {icache_refill_address[(clogb2(32'h7fffffff-32'h0)-2)+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
end
endcase
endgenerate
-
@@ -73804,40 +67296,39 @@ endgenerate
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- pc_f <= ( 32'h00000000-4)/4;
- pc_d <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_x <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_m <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
- pc_w <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_f <= (32'h00000000-4)/4;
+ pc_d <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_x <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_m <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ pc_w <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
end
else
begin
- if (stall_f == 1'b0)
+ if (stall_f == 1'b0)
pc_f <= pc_a;
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
pc_d <= pc_f;
- if (stall_x == 1'b0)
+ if (stall_x == 1'b0)
pc_x <= pc_d;
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
pc_m <= pc_x;
pc_w <= pc_m;
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- restart_address <= { (clogb2(32'h7fffffff-32'h0)-2){1'b0}};
+ if (rst_i == 1'b1)
+ restart_address <= {(clogb2(32'h7fffffff-32'h0)-2){1'b0}};
else
begin
-
+
@@ -73849,22 +67340,17 @@ begin
-
-
-
- if (icache_refill_request == 1'b1)
+
+ if (icache_refill_request == 1'b1)
restart_address <= icache_refill_address;
-
-
end
end
-
-
+
@@ -73877,121 +67363,106 @@ end
-
-
-
-assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1);
+
+assign jtag_access_complete = (i_cyc_o == 1'b1) && ((i_ack_i == 1'b1) || (i_err_i == 1'b1)) && (jtag_access == 1'b1);
always @(*)
begin
case (jtag_address[1:0])
- 2'b00: jtag_read_data = i_dat_i[ 31:24];
- 2'b01: jtag_read_data = i_dat_i[ 23:16];
- 2'b10: jtag_read_data = i_dat_i[ 15:8];
- 2'b11: jtag_read_data = i_dat_i[ 7:0];
+ 2'b00: jtag_read_data = i_dat_i[31:24];
+ 2'b01: jtag_read_data = i_dat_i[23:16];
+ 2'b10: jtag_read_data = i_dat_i[15:8];
+ 2'b11: jtag_read_data = i_dat_i[7:0];
endcase
end
-
-
-
+
-
-
-always @(posedge clk_i )
+
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_adr_o <= { 32{1'b0}};
- i_cti_o <= 3'b111;
- i_lock_o <= 1'b0;
- icache_refill_data <= { 32{1'b0}};
- icache_refill_ready <= 1'b0;
-
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_adr_o <= {32{1'b0}};
+ i_cti_o <= 3'b111;
+ i_lock_o <= 1'b0;
+ icache_refill_data <= {32{1'b0}};
+ icache_refill_ready <= 1'b0;
+
-
-
-
- i_we_o <= 1'b0;
- i_sel_o <= 4'b1111;
- jtag_access <= 1'b0;
+ i_we_o <= 1'b0;
+ i_sel_o <= 4'b1111;
+ jtag_access <= 1'b0;
end
else
begin
- icache_refill_ready <= 1'b0;
+ icache_refill_ready <= 1'b0;
- if (i_cyc_o == 1'b1)
+ if (i_cyc_o == 1'b1)
begin
- if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
+ if ((i_ack_i == 1'b1) || (i_err_i == 1'b1))
begin
-
-
- if (jtag_access == 1'b1)
+
+ if (jtag_access == 1'b1)
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_we_o <= 1'b0;
- jtag_access <= 1'b0;
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_we_o <= 1'b0;
+ jtag_access <= 1'b0;
end
else
-
begin
- if (last_word == 1'b1)
+ if (last_word == 1'b1)
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_lock_o <= 1'b0;
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_lock_o <= 1'b0;
end
i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
i_cti_o <= next_cycle_type;
- icache_refill_ready <= 1'b1;
+ icache_refill_ready <= 1'b1;
icache_refill_data <= i_dat_i;
end
end
-
+
-
end
else
begin
- if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
+ if ((icache_refill_request == 1'b1) && (icache_refill_ready == 1'b0))
begin
-
-
+
i_sel_o <= 4'b1111;
-
i_adr_o <= {first_address, 2'b00};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
i_cti_o <= first_cycle_type;
-
+
-
end
-
-
+
else
begin
- if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1))
+ if ((jtag_read_enable == 1'b1) || (jtag_write_enable == 1'b1))
begin
case (jtag_address[1:0])
2'b00: i_sel_o <= 4'b1000;
@@ -74001,16 +67472,15 @@ begin
endcase
i_adr_o <= jtag_address;
i_dat_o <= {4{jtag_write_data}};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
i_we_o <= jtag_write_enable;
- i_cti_o <= 3'b111;
- jtag_access <= 1'b1;
+ i_cti_o <= 3'b111;
+ jtag_access <= 1'b1;
end
end
-
-
+
@@ -74020,11 +67490,10 @@ begin
-
end
end
end
-
+
@@ -74098,30 +67567,26 @@ end
-
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- instruction_d <= { 32{1'b0}};
-
+ instruction_d <= {32{1'b0}};
+
-
end
else
begin
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
begin
instruction_d <= instruction_f;
-
+
-
end
end
end
@@ -74155,10 +67620,7 @@ endmodule
-
-
-
-
+
@@ -74188,9 +67650,9 @@ endmodule
-
+
@@ -74474,57 +67936,33 @@ endmodule
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
-
+
+
+
+
+
+
+
+
+
+
@@ -74538,34 +67976,25 @@ module lm32_jtag_medium_icache_debug (
jtag_update,
jtag_reg_q,
jtag_reg_addr_q,
-
-
+
csr,
csr_write_enable,
csr_write_data,
stall_x,
-
-
-
+
jtag_read_data,
jtag_access_complete,
-
-
-
- exception_q_w,
+ exception_q_w,
-
-
+
jtx_csr_read_data,
jrx_csr_read_data,
-
-
-
+
jtag_csr_write_enable,
jtag_csr_write_data,
jtag_csr,
@@ -74573,13 +68002,10 @@ module lm32_jtag_medium_icache_debug (
jtag_write_enable,
jtag_write_data,
jtag_address,
-
-
-
+
jtag_break,
jtag_reset,
-
jtag_reg_d,
jtag_reg_addr_d
@@ -74594,69 +68020,57 @@ input rst_i;
input jtag_clk;
input jtag_update;
-input [ 7:0] jtag_reg_q;
+input [7:0] jtag_reg_q;
input [2:0] jtag_reg_addr_q;
-
-
-input [ (5-1):0] csr;
+
+input [(5-1):0] csr;
input csr_write_enable;
-input [ (32-1):0] csr_write_data;
+input [(32-1):0] csr_write_data;
input stall_x;
-
-
-
-input [ 7:0] jtag_read_data;
-input jtag_access_complete;
+input [7:0] jtag_read_data;
+input jtag_access_complete;
-
-
-input exception_q_w;
+input exception_q_w;
-
-
-output [ (32-1):0] jtx_csr_read_data;
-wire [ (32-1):0] jtx_csr_read_data;
-output [ (32-1):0] jrx_csr_read_data;
-wire [ (32-1):0] jrx_csr_read_data;
+output [(32-1):0] jtx_csr_read_data;
+wire [(32-1):0] jtx_csr_read_data;
+output [(32-1):0] jrx_csr_read_data;
+wire [(32-1):0] jrx_csr_read_data;
-
-
+
output jtag_csr_write_enable;
reg jtag_csr_write_enable;
-output [ (32-1):0] jtag_csr_write_data;
-wire [ (32-1):0] jtag_csr_write_data;
-output [ (5-1):0] jtag_csr;
-wire [ (5-1):0] jtag_csr;
+output [(32-1):0] jtag_csr_write_data;
+wire [(32-1):0] jtag_csr_write_data;
+output [(5-1):0] jtag_csr;
+wire [(5-1):0] jtag_csr;
output jtag_read_enable;
reg jtag_read_enable;
output jtag_write_enable;
reg jtag_write_enable;
-output [ 7:0] jtag_write_data;
-wire [ 7:0] jtag_write_data;
-output [ (32-1):0] jtag_address;
-wire [ (32-1):0] jtag_address;
-
-
-
+output [7:0] jtag_write_data;
+wire [7:0] jtag_write_data;
+output [(32-1):0] jtag_address;
+wire [(32-1):0] jtag_address;
+
output jtag_break;
reg jtag_break;
output jtag_reset;
reg jtag_reset;
-
-output [ 7:0] jtag_reg_d;
-reg [ 7:0] jtag_reg_d;
+output [7:0] jtag_reg_d;
+reg [7:0] jtag_reg_d;
output [2:0] jtag_reg_addr_d;
wire [2:0] jtag_reg_addr_d;
@@ -74671,66 +68085,54 @@ reg rx_update_r_r_r;
-wire [ 7:0] rx_byte;
+wire [7:0] rx_byte;
wire [2:0] rx_addr;
-
-
-reg [ 7:0] uart_tx_byte;
+
+reg [7:0] uart_tx_byte;
reg uart_tx_valid;
-reg [ 7:0] uart_rx_byte;
+reg [7:0] uart_rx_byte;
reg uart_rx_valid;
-
-reg [ 3:0] command;
-
-
-reg [ 7:0] jtag_byte_0;
-reg [ 7:0] jtag_byte_1;
-reg [ 7:0] jtag_byte_2;
-reg [ 7:0] jtag_byte_3;
-reg [ 7:0] jtag_byte_4;
-reg processing;
+reg [3:0] command;
+reg [7:0] jtag_byte_0;
+reg [7:0] jtag_byte_1;
+reg [7:0] jtag_byte_2;
+reg [7:0] jtag_byte_3;
+reg [7:0] jtag_byte_4;
+reg processing;
-reg [ 3:0] state;
-
+reg [3:0] state;
-
+
assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
-assign jtag_csr = jtag_byte_4[ (5-1):0];
+assign jtag_csr = jtag_byte_4[(5-1):0];
assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
assign jtag_write_data = jtag_byte_4;
-
-
-
+
assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
-
-
-
-
+
-assign jtag_reg_addr_d[2] = processing;
-
+assign jtag_reg_addr_d[2] = processing;
+
-
-
-assign jtx_csr_read_data = {{ 32-9{1'b0}}, uart_tx_valid, 8'h00};
-assign jrx_csr_read_data = {{ 32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
-
+
+assign jtx_csr_read_data = {{32-9{1'b0}}, uart_tx_valid, 8'h00};
+assign jrx_csr_read_data = {{32-9{1'b0}}, uart_rx_valid, uart_rx_byte};
@@ -74742,9 +68144,9 @@ assign rx_addr = jtag_reg_addr_q;
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
rx_update <= 1'b0;
rx_update_r <= 1'b0;
@@ -74761,232 +68163,210 @@ begin
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- state <= 4'h0;
+ state <= 4'h0;
command <= 4'b0000;
jtag_reg_d <= 8'h00;
-
-
- processing <= 1'b0;
- jtag_csr_write_enable <= 1'b0;
- jtag_read_enable <= 1'b0;
- jtag_write_enable <= 1'b0;
+ processing <= 1'b0;
+ jtag_csr_write_enable <= 1'b0;
+ jtag_read_enable <= 1'b0;
+ jtag_write_enable <= 1'b0;
-
-
- jtag_break <= 1'b0;
- jtag_reset <= 1'b0;
+ jtag_break <= 1'b0;
+ jtag_reset <= 1'b0;
-
-
+
uart_tx_byte <= 8'h00;
- uart_tx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
uart_rx_byte <= 8'h00;
- uart_rx_valid <= 1'b0;
-
+ uart_rx_valid <= 1'b0;
end
else
begin
-
-
- if ((csr_write_enable == 1'b1) && (stall_x == 1'b0))
+
+ if ((csr_write_enable == 1'b1) && (stall_x == 1'b0))
begin
case (csr)
- 5'he:
+ 5'he:
begin
- uart_tx_byte <= csr_write_data[ 7:0];
- uart_tx_valid <= 1'b1;
+ uart_tx_byte <= csr_write_data[7:0];
+ uart_tx_valid <= 1'b1;
end
- 5'hf:
+ 5'hf:
begin
- uart_rx_valid <= 1'b0;
+ uart_rx_valid <= 1'b0;
end
endcase
end
-
-
-
+
- if (exception_q_w == 1'b1)
+ if (exception_q_w == 1'b1)
begin
- jtag_break <= 1'b0;
- jtag_reset <= 1'b0;
+ jtag_break <= 1'b0;
+ jtag_reset <= 1'b0;
end
-
case (state)
- 4'h0:
+ 4'h0:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
command <= rx_byte[7:4];
case (rx_addr)
-
-
- 3'b000:
+
+ 3'b000:
begin
case (rx_byte[7:4])
-
-
- 4'b0001:
- state <= 4'h1;
- 4'b0011:
+
+ 4'b0001:
+ state <= 4'h1;
+ 4'b0011:
begin
{jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
- state <= 4'h6;
+ state <= 4'h6;
end
- 4'b0010:
- state <= 4'h1;
- 4'b0100:
+ 4'b0010:
+ state <= 4'h1;
+ 4'b0100:
begin
{jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
state <= 5;
end
- 4'b0101:
- state <= 4'h1;
-
+ 4'b0101:
+ state <= 4'h1;
- 4'b0110:
+ 4'b0110:
begin
-
-
- uart_rx_valid <= 1'b0;
- uart_tx_valid <= 1'b0;
-
+
+ uart_rx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
- jtag_break <= 1'b1;
+ jtag_break <= 1'b1;
end
- 4'b0111:
+ 4'b0111:
begin
-
-
- uart_rx_valid <= 1'b0;
- uart_tx_valid <= 1'b0;
-
+
+ uart_rx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
- jtag_reset <= 1'b1;
+ jtag_reset <= 1'b1;
end
endcase
end
-
-
-
- 3'b001:
+
+ 3'b001:
begin
uart_rx_byte <= rx_byte;
- uart_rx_valid <= 1'b1;
+ uart_rx_valid <= 1'b1;
end
- 3'b010:
+ 3'b010:
begin
jtag_reg_d <= uart_tx_byte;
- uart_tx_valid <= 1'b0;
+ uart_tx_valid <= 1'b0;
end
-
default:
;
endcase
end
end
-
-
- 4'h1:
+
+ 4'h1:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
jtag_byte_0 <= rx_byte;
- state <= 4'h2;
+ state <= 4'h2;
end
end
- 4'h2:
+ 4'h2:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
jtag_byte_1 <= rx_byte;
- state <= 4'h3;
+ state <= 4'h3;
end
end
- 4'h3:
+ 4'h3:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
jtag_byte_2 <= rx_byte;
- state <= 4'h4;
+ state <= 4'h4;
end
end
- 4'h4:
+ 4'h4:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
jtag_byte_3 <= rx_byte;
- if (command == 4'b0001)
- state <= 4'h6;
+ if (command == 4'b0001)
+ state <= 4'h6;
else
- state <= 4'h5;
+ state <= 4'h5;
end
end
- 4'h5:
+ 4'h5:
begin
- if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
+ if ((~rx_update_r_r_r & rx_update_r_r) == 1'b1)
begin
jtag_byte_4 <= rx_byte;
- state <= 4'h6;
+ state <= 4'h6;
end
end
- 4'h6:
+ 4'h6:
begin
case (command)
- 4'b0001,
- 4'b0011:
+ 4'b0001,
+ 4'b0011:
begin
- jtag_read_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h7;
+ jtag_read_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h7;
end
- 4'b0010,
- 4'b0100:
+ 4'b0010,
+ 4'b0100:
begin
- jtag_write_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h7;
+ jtag_write_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h7;
end
- 4'b0101:
+ 4'b0101:
begin
- jtag_csr_write_enable <= 1'b1;
- processing <= 1'b1;
- state <= 4'h8;
+ jtag_csr_write_enable <= 1'b1;
+ processing <= 1'b1;
+ state <= 4'h8;
end
endcase
end
- 4'h7:
+ 4'h7:
begin
- if (jtag_access_complete == 1'b1)
+ if (jtag_access_complete == 1'b1)
begin
- jtag_read_enable <= 1'b0;
+ jtag_read_enable <= 1'b0;
jtag_reg_d <= jtag_read_data;
- jtag_write_enable <= 1'b0;
- processing <= 1'b0;
- state <= 4'h0;
+ jtag_write_enable <= 1'b0;
+ processing <= 1'b0;
+ state <= 4'h0;
end
end
- 4'h8:
+ 4'h8:
begin
- jtag_csr_write_enable <= 1'b0;
- processing <= 1'b0;
- state <= 4'h0;
+ jtag_csr_write_enable <= 1'b0;
+ processing <= 1'b0;
+ state <= 4'h0;
end
-
endcase
end
@@ -74994,8 +68374,6 @@ end
endmodule
-
-
@@ -75024,10 +68402,8 @@ endmodule
-
-
-
+
@@ -75057,9 +68433,9 @@ endmodule
-
+
@@ -75344,8 +68720,6 @@ endmodule
-
-
@@ -75357,19 +68731,15 @@ module lm32_interrupt_medium_icache_debug (
interrupt,
stall_x,
-
-
+
non_debug_exception,
debug_exception,
-
-
+
eret_q_x,
-
-
- bret_q_x,
+ bret_q_x,
csr,
csr_write_data,
@@ -75384,7 +68754,7 @@ module lm32_interrupt_medium_icache_debug (
-parameter interrupts = 32;
+parameter interrupts = 32;
@@ -75397,23 +68767,19 @@ input [interrupts-1:0] interrupt;
input stall_x;
-
-
+
input non_debug_exception;
input debug_exception;
-
-
+
input eret_q_x;
-
-
-input bret_q_x;
+input bret_q_x;
-input [ (5-1):0] csr;
-input [ (32-1):0] csr_write_data;
+input [(5-1):0] csr;
+input [(32-1):0] csr_write_data;
input csr_write_enable;
@@ -75423,8 +68789,8 @@ input csr_write_enable;
output interrupt_exception;
wire interrupt_exception;
-output [ (32-1):0] csr_read_data;
-reg [ (32-1):0] csr_read_data;
+output [(32-1):0] csr_read_data;
+reg [(32-1):0] csr_read_data;
@@ -75438,10 +68804,8 @@ wire [interrupts-1:0] interrupt_n_exception;
reg ie;
reg eie;
-
-
-reg bie;
+reg bie;
reg [interrupts-1:0] ip;
reg [interrupts-1:0] im;
@@ -75459,13 +68823,11 @@ assign interrupt_exception = (|interrupt_n_exception) & ie;
assign asserted = ip | interrupt;
-assign ie_csr_read_data = {{ 32-3{1'b0}},
-
-
- bie,
+assign ie_csr_read_data = {{32-3{1'b0}},
-
+ bie,
+
eie,
ie
@@ -75479,20 +68841,18 @@ generate
always @(*)
begin
case (csr)
- 5'h0: csr_read_data = {{ 32-3{1'b0}},
-
-
- bie,
+ 5'h0: csr_read_data = {{32-3{1'b0}},
-
+ bie,
+
eie,
ie
};
- 5'h2: csr_read_data = ip;
- 5'h1: csr_read_data = im;
- default: csr_read_data = { 32{1'bx}};
+ 5'h2: csr_read_data = ip;
+ 5'h1: csr_read_data = im;
+ default: csr_read_data = {32{1'bx}};
endcase
end
end
@@ -75502,19 +68862,17 @@ end
always @(*)
begin
case (csr)
- 5'h0: csr_read_data = {{ 32-3{1'b0}},
-
-
- bie,
+ 5'h0: csr_read_data = {{32-3{1'b0}},
-
+ bie,
+
eie,
ie
};
- 5'h2: csr_read_data = ip;
- default: csr_read_data = { 32{1'bx}};
+ 5'h2: csr_read_data = ip;
+ default: csr_read_data = {32{1'bx}};
endcase
end
end
@@ -75524,9 +68882,8 @@ endgenerate
-
-
- reg [ 10:0] eie_delay = 0;
+
+ reg [10:0] eie_delay = 0;
generate
@@ -75535,16 +68892,14 @@ generate
if (interrupts > 1)
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- ie <= 1'b0;
- eie <= 1'b0;
-
-
- bie <= 1'b0;
+ ie <= 1'b0;
+ eie <= 1'b0;
+ bie <= 1'b0;
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
@@ -75555,21 +68910,20 @@ always @(posedge clk_i )
begin
ip <= asserted;
-
-
- if (non_debug_exception == 1'b1)
+
+ if (non_debug_exception == 1'b1)
begin
eie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
- else if (debug_exception == 1'b1)
+ else if (debug_exception == 1'b1)
begin
bie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
-
+
@@ -75577,46 +68931,41 @@ always @(posedge clk_i )
-
- else if (stall_x == 1'b0)
+ else if (stall_x == 1'b0)
begin
if(eie_delay[0])
ie <= eie;
- eie_delay <= {1'b0, eie_delay[ 10:1]};
+ eie_delay <= {1'b0, eie_delay[10:1]};
- if (eret_q_x == 1'b1) begin
+ if (eret_q_x == 1'b1) begin
- eie_delay[ 10] <= 1'b1;
- eie_delay[ 10-1:0] <= 0;
+ eie_delay[10] <= 1'b1;
+ eie_delay[10-1:0] <= 0;
end
-
-
- else if (bret_q_x == 1'b1)
+
+ else if (bret_q_x == 1'b1)
ie <= bie;
-
- else if (csr_write_enable == 1'b1)
+ else if (csr_write_enable == 1'b1)
begin
- if (csr == 5'h0)
+ if (csr == 5'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
-
- bie <= csr_write_data[2];
+ bie <= csr_write_data[2];
end
- if (csr == 5'h1)
+ if (csr == 5'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 5'h2)
+ if (csr == 5'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -75626,16 +68975,14 @@ end
else
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- ie <= 1'b0;
- eie <= 1'b0;
-
-
- bie <= 1'b0;
+ ie <= 1'b0;
+ eie <= 1'b0;
+ bie <= 1'b0;
ip <= {interrupts{1'b0}};
eie_delay <= 0;
@@ -75644,21 +68991,20 @@ always @(posedge clk_i )
begin
ip <= asserted;
-
-
- if (non_debug_exception == 1'b1)
+
+ if (non_debug_exception == 1'b1)
begin
eie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
- else if (debug_exception == 1'b1)
+ else if (debug_exception == 1'b1)
begin
bie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
-
+
@@ -75666,42 +69012,37 @@ always @(posedge clk_i )
-
- else if (stall_x == 1'b0)
+ else if (stall_x == 1'b0)
begin
if(eie_delay[0])
ie <= eie;
- eie_delay <= {1'b0, eie_delay[ 10:1]};
+ eie_delay <= {1'b0, eie_delay[10:1]};
- if (eret_q_x == 1'b1) begin
+ if (eret_q_x == 1'b1) begin
- eie_delay[ 10] <= 1'b1;
- eie_delay[ 10-1:0] <= 0;
+ eie_delay[10] <= 1'b1;
+ eie_delay[10-1:0] <= 0;
end
-
-
- else if (bret_q_x == 1'b1)
+
+ else if (bret_q_x == 1'b1)
ie <= bie;
-
- else if (csr_write_enable == 1'b1)
+ else if (csr_write_enable == 1'b1)
begin
- if (csr == 5'h0)
+ if (csr == 5'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
-
- bie <= csr_write_data[2];
+ bie <= csr_write_data[2];
end
- if (csr == 5'h2)
+ if (csr == 5'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -75741,42 +69082,23 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -75785,15 +69107,8 @@ endmodule
-
-
-
-
-
-
-
-
+
@@ -75822,275 +69137,186 @@ endmodule
-
-
+
+
-
+
+
+
+
+
-
-
-
+
+
-
+
+
+
+
+
+
+
+
-
-
+
+
+
+
+
-
+
+
-
+
-
-
+
-
-
+
+
+
+
-
-
+
+
-
+
+
+
+
-
-
-
+
+
+
+
-
-
-
-
-
-
-
+
+
+
-
-
-
+
-
+
-
+
+
+
+
-
-
+
+
-
+
+
-
+
+
-
-
-
-
-
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
-
-
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
-
-
-
-
+
+
-
-
+
@@ -76099,156 +69325,100 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
-
-
+
+
+
+
-
-
-
+
+
+
-
-
+
+
+
+
-
-
+
+
+
+
-
-
+
+
+
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
@@ -76267,19 +69437,16 @@ module lm32_top_minimal (
interrupt,
-
+
-
-
-
+
I_DAT_I,
I_ACK_I,
I_ERR_I,
I_RTY_I,
-
D_DAT_I,
@@ -76287,15 +69454,13 @@ module lm32_top_minimal (
D_ERR_I,
D_RTY_I,
-
+
-
-
-
+
I_DAT_O,
I_ADR_O,
@@ -76306,7 +69471,6 @@ module lm32_top_minimal (
I_CTI_O,
I_LOCK_O,
I_BTE_O,
-
D_DAT_O,
@@ -76328,25 +69492,22 @@ input clk_i;
input rst_i;
-input [ (32-1):0] interrupt;
+input [(32-1):0] interrupt;
-
+
-
-
-
-input [ (32-1):0] I_DAT_I;
+
+input [(32-1):0] I_DAT_I;
input I_ACK_I;
input I_ERR_I;
input I_RTY_I;
-
-input [ (32-1):0] D_DAT_I;
+input [(32-1):0] D_DAT_I;
input D_ACK_I;
input D_ERR_I;
input D_RTY_I;
@@ -76355,7 +69516,7 @@ input D_RTY_I;
-
+
@@ -76366,54 +69527,51 @@ input D_RTY_I;
-
-
-
-output [ (32-1):0] I_DAT_O;
-wire [ (32-1):0] I_DAT_O;
-output [ (32-1):0] I_ADR_O;
-wire [ (32-1):0] I_ADR_O;
+
+output [(32-1):0] I_DAT_O;
+wire [(32-1):0] I_DAT_O;
+output [(32-1):0] I_ADR_O;
+wire [(32-1):0] I_ADR_O;
output I_CYC_O;
wire I_CYC_O;
-output [ (4-1):0] I_SEL_O;
-wire [ (4-1):0] I_SEL_O;
+output [(4-1):0] I_SEL_O;
+wire [(4-1):0] I_SEL_O;
output I_STB_O;
wire I_STB_O;
output I_WE_O;
wire I_WE_O;
-output [ (3-1):0] I_CTI_O;
-wire [ (3-1):0] I_CTI_O;
+output [(3-1):0] I_CTI_O;
+wire [(3-1):0] I_CTI_O;
output I_LOCK_O;
wire I_LOCK_O;
-output [ (2-1):0] I_BTE_O;
-wire [ (2-1):0] I_BTE_O;
-
+output [(2-1):0] I_BTE_O;
+wire [(2-1):0] I_BTE_O;
-output [ (32-1):0] D_DAT_O;
-wire [ (32-1):0] D_DAT_O;
-output [ (32-1):0] D_ADR_O;
-wire [ (32-1):0] D_ADR_O;
+output [(32-1):0] D_DAT_O;
+wire [(32-1):0] D_DAT_O;
+output [(32-1):0] D_ADR_O;
+wire [(32-1):0] D_ADR_O;
output D_CYC_O;
wire D_CYC_O;
-output [ (4-1):0] D_SEL_O;
-wire [ (4-1):0] D_SEL_O;
+output [(4-1):0] D_SEL_O;
+wire [(4-1):0] D_SEL_O;
output D_STB_O;
wire D_STB_O;
output D_WE_O;
wire D_WE_O;
-output [ (3-1):0] D_CTI_O;
-wire [ (3-1):0] D_CTI_O;
+output [(3-1):0] D_CTI_O;
+wire [(3-1):0] D_CTI_O;
output D_LOCK_O;
wire D_LOCK_O;
-output [ (2-1):0] D_BTE_O;
-wire [ (2-1):0] D_BTE_O;
+output [(2-1):0] D_BTE_O;
+wire [(2-1):0] D_BTE_O;
-
+
@@ -76425,8 +69583,7 @@ wire [ (2-1):0] D_BTE_O;
-
-
+
@@ -76442,10 +69599,7 @@ wire [ (2-1):0] D_BTE_O;
-
-
-
-
+
@@ -76498,45 +69652,37 @@ endfunction
-
lm32_cpu_minimal cpu (
.clk_i (clk_i),
-
+
-
.rst_i (rst_i),
-
-
- .interrupt (interrupt),
+ .interrupt (interrupt),
-
+
-
-
+
-
-
-
+
.I_DAT_I (I_DAT_I),
.I_ACK_I (I_ACK_I),
.I_ERR_I (I_ERR_I),
.I_RTY_I (I_RTY_I),
-
.D_DAT_I (D_DAT_I),
@@ -76544,7 +69690,7 @@ lm32_cpu_minimal cpu (
.D_ERR_I (D_ERR_I),
.D_RTY_I (D_RTY_I),
-
+
@@ -76554,21 +69700,17 @@ lm32_cpu_minimal cpu (
-
-
+
-
-
+
-
-
-
+
.I_DAT_O (I_DAT_O),
.I_ADR_O (I_ADR_O),
@@ -76579,8 +69721,7 @@ lm32_cpu_minimal cpu (
.I_CTI_O (I_CTI_O),
.I_LOCK_O (I_LOCK_O),
.I_BTE_O (I_BTE_O),
-
-
+
.D_DAT_O (D_DAT_O),
.D_ADR_O (D_ADR_O),
@@ -76593,7 +69734,7 @@ lm32_cpu_minimal cpu (
.D_BTE_O (D_BTE_O)
);
-
+
@@ -76606,7 +69747,6 @@ lm32_cpu_minimal cpu (
-
endmodule
@@ -76638,10 +69778,7 @@ endmodule
-
-
-
-
+
@@ -76671,9 +69808,9 @@ endmodule
-
+
@@ -76955,24 +70092,15 @@ endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
@@ -76984,29 +70112,25 @@ module lm32_mc_arithmetic_minimal (
rst_i,
stall_d,
kill_x,
-
+
-
-
+
-
-
+
-
operand_0_d,
operand_1_d,
result_x,
-
+
-
stall_request_x
);
@@ -77018,35 +70142,31 @@ input clk_i;
input rst_i;
input stall_d;
input kill_x;
-
+
-
-
+
-
-
+
-
-input [ (32-1):0] operand_0_d;
-input [ (32-1):0] operand_1_d;
+input [(32-1):0] operand_0_d;
+input [(32-1):0] operand_1_d;
-output [ (32-1):0] result_x;
-reg [ (32-1):0] result_x;
-
+output [(32-1):0] result_x;
+reg [(32-1):0] result_x;
+
-
output stall_request_x;
wire stall_request_x;
@@ -77054,18 +70174,17 @@ wire stall_request_x;
-reg [ (32-1):0] p;
-reg [ (32-1):0] a;
-reg [ (32-1):0] b;
-
+reg [(32-1):0] p;
+reg [(32-1):0] a;
+reg [(32-1):0] b;
+
-
-reg [ 2:0] state;
+reg [2:0] state;
reg [5:0] cycles;
-
+
@@ -77075,16 +70194,14 @@ reg [5:0] cycles;
+assign stall_request_x = state != 3'b000;
-assign stall_request_x = state != 3'b000;
-
-
+
-
-
+
@@ -77094,54 +70211,48 @@ assign stall_request_x = state != 3'b000;
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
cycles <= {6{1'b0}};
- p <= { 32{1'b0}};
- a <= { 32{1'b0}};
- b <= { 32{1'b0}};
-
+ p <= {32{1'b0}};
+ a <= {32{1'b0}};
+ b <= {32{1'b0}};
+
-
-
+
-
- result_x <= { 32{1'b0}};
- state <= 3'b000;
+ result_x <= {32{1'b0}};
+ state <= 3'b000;
end
else
begin
-
+
-
case (state)
- 3'b000:
+ 3'b000:
begin
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
begin
- cycles <= 32;
+ cycles <= 32;
p <= 32'b0;
a <= operand_0_d;
b <= operand_1_d;
-
+
-
-
+
-
-
+
@@ -77158,11 +70269,10 @@ begin
-
end
end
-
+
@@ -77205,9 +70315,8 @@ begin
-
-
+
@@ -77219,9 +70328,8 @@ begin
-
-
+
@@ -77238,7 +70346,6 @@ begin
-
endcase
end
@@ -77309,10 +70416,7 @@ endmodule
-
-
-
-
+
@@ -77342,9 +70446,9 @@ endmodule
-
+
@@ -77629,47 +70733,38 @@ endmodule
-
-
module lm32_cpu_minimal (
clk_i,
-
+
-
rst_i,
-
-
- interrupt,
+ interrupt,
-
+
-
-
+
-
-
-
+
I_DAT_I,
I_ACK_I,
I_ERR_I,
I_RTY_I,
-
D_DAT_I,
@@ -77677,7 +70772,7 @@ module lm32_cpu_minimal (
D_ERR_I,
D_RTY_I,
-
+
@@ -77687,21 +70782,17 @@ module lm32_cpu_minimal (
-
-
+
-
-
+
-
-
-
+
I_DAT_O,
I_ADR_O,
@@ -77712,7 +70803,6 @@ module lm32_cpu_minimal (
I_CTI_O,
I_LOCK_O,
I_BTE_O,
-
D_DAT_O,
@@ -77730,65 +70820,54 @@ module lm32_cpu_minimal (
-parameter eba_reset = 32'h00000000;
-
+parameter eba_reset = 32'h00000000;
+
-
-
+
-
parameter icache_associativity = 1;
parameter icache_sets = 512;
parameter icache_bytes_per_line = 16;
parameter icache_base_address = 0;
parameter icache_limit = 0;
-
-
+
-
parameter dcache_associativity = 1;
parameter dcache_sets = 512;
parameter dcache_bytes_per_line = 16;
parameter dcache_base_address = 0;
parameter dcache_limit = 0;
-
-
+
-
parameter watchpoints = 0;
-
-
+
-
parameter breakpoints = 0;
-
-
-
-parameter interrupts = 32;
-
+parameter interrupts = 32;
+
@@ -77796,42 +70875,35 @@ parameter interrupts = 32;
input clk_i;
-
+
-
input rst_i;
-
-
-input [ (32-1):0] interrupt;
+input [(32-1):0] interrupt;
-
+
-
-
+
-
-
-
-input [ (32-1):0] I_DAT_I;
+
+input [(32-1):0] I_DAT_I;
input I_ACK_I;
input I_ERR_I;
input I_RTY_I;
-
-input [ (32-1):0] D_DAT_I;
+input [(32-1):0] D_DAT_I;
input D_ACK_I;
input D_ERR_I;
input D_RTY_I;
@@ -77840,7 +70912,7 @@ input D_RTY_I;
-
+
@@ -77857,16 +70929,14 @@ input D_RTY_I;
-
-
+
-
-
+
@@ -77877,48 +70947,45 @@ input D_RTY_I;
-
-
-
-output [ (32-1):0] I_DAT_O;
-wire [ (32-1):0] I_DAT_O;
-output [ (32-1):0] I_ADR_O;
-wire [ (32-1):0] I_ADR_O;
+
+output [(32-1):0] I_DAT_O;
+wire [(32-1):0] I_DAT_O;
+output [(32-1):0] I_ADR_O;
+wire [(32-1):0] I_ADR_O;
output I_CYC_O;
wire I_CYC_O;
-output [ (4-1):0] I_SEL_O;
-wire [ (4-1):0] I_SEL_O;
+output [(4-1):0] I_SEL_O;
+wire [(4-1):0] I_SEL_O;
output I_STB_O;
wire I_STB_O;
output I_WE_O;
wire I_WE_O;
-output [ (3-1):0] I_CTI_O;
-wire [ (3-1):0] I_CTI_O;
+output [(3-1):0] I_CTI_O;
+wire [(3-1):0] I_CTI_O;
output I_LOCK_O;
wire I_LOCK_O;
-output [ (2-1):0] I_BTE_O;
-wire [ (2-1):0] I_BTE_O;
-
+output [(2-1):0] I_BTE_O;
+wire [(2-1):0] I_BTE_O;
-output [ (32-1):0] D_DAT_O;
-wire [ (32-1):0] D_DAT_O;
-output [ (32-1):0] D_ADR_O;
-wire [ (32-1):0] D_ADR_O;
+output [(32-1):0] D_DAT_O;
+wire [(32-1):0] D_DAT_O;
+output [(32-1):0] D_ADR_O;
+wire [(32-1):0] D_ADR_O;
output D_CYC_O;
wire D_CYC_O;
-output [ (4-1):0] D_SEL_O;
-wire [ (4-1):0] D_SEL_O;
+output [(4-1):0] D_SEL_O;
+wire [(4-1):0] D_SEL_O;
output D_STB_O;
wire D_STB_O;
output D_WE_O;
wire D_WE_O;
-output [ (3-1):0] D_CTI_O;
-wire [ (3-1):0] D_CTI_O;
+output [(3-1):0] D_CTI_O;
+wire [(3-1):0] D_CTI_O;
output D_LOCK_O;
wire D_LOCK_O;
-output [ (2-1):0] D_BTE_O;
-wire [ (2-1):0] D_BTE_O;
+output [(2-1):0] D_BTE_O;
+wire [(2-1):0] D_BTE_O;
@@ -77926,10 +70993,9 @@ wire [ (2-1):0] D_BTE_O;
-
+
-
reg valid_f;
reg valid_d;
reg valid_x;
@@ -77937,7 +71003,7 @@ reg valid_m;
reg valid_w;
wire q_x;
-wire [ (32-1):0] immediate_d;
+wire [(32-1):0] immediate_d;
wire load_d;
reg load_x;
reg load_m;
@@ -77946,13 +71012,13 @@ wire store_q_x;
wire store_d;
reg store_x;
reg store_m;
-wire [ 1:0] size_d;
-reg [ 1:0] size_x;
+wire [1:0] size_d;
+reg [1:0] size_x;
wire branch_d;
wire branch_predict_d;
wire branch_predict_taken_d;
-wire [ ((32-2)+2-1):2] branch_predict_address_d;
-wire [ ((32-2)+2-1):2] branch_target_d;
+wire [((32-2)+2-1):2] branch_predict_address_d;
+wire [((32-2)+2-1):2] branch_target_d;
wire bi_unconditional;
wire bi_conditional;
reg branch_x;
@@ -77964,59 +71030,52 @@ reg branch_predict_taken_m;
wire branch_mispredict_taken_m;
wire branch_flushX_m;
wire branch_reg_d;
-wire [ ((32-2)+2-1):2] branch_offset_d;
-reg [ ((32-2)+2-1):2] branch_target_x;
-reg [ ((32-2)+2-1):2] branch_target_m;
-wire [ 0:0] d_result_sel_0_d;
-wire [ 1:0] d_result_sel_1_d;
+wire [((32-2)+2-1):2] branch_offset_d;
+reg [((32-2)+2-1):2] branch_target_x;
+reg [((32-2)+2-1):2] branch_target_m;
+wire [0:0] d_result_sel_0_d;
+wire [1:0] d_result_sel_1_d;
wire x_result_sel_csr_d;
reg x_result_sel_csr_x;
-
+
-
-
-
+
wire x_result_sel_shift_d;
reg x_result_sel_shift_x;
-
-
+
-
wire x_result_sel_logic_d;
reg x_result_sel_logic_x;
-
+
-
wire x_result_sel_add_d;
reg x_result_sel_add_x;
wire m_result_sel_compare_d;
reg m_result_sel_compare_x;
reg m_result_sel_compare_m;
-
+
-
wire w_result_sel_load_d;
reg w_result_sel_load_x;
reg w_result_sel_load_m;
reg w_result_sel_load_w;
-
+
-
wire x_bypass_enable_d;
reg x_bypass_enable_x;
wire m_bypass_enable_d;
@@ -78032,33 +71091,31 @@ wire write_enable_q_m;
reg write_enable_w;
wire write_enable_q_w;
wire read_enable_0_d;
-wire [ (5-1):0] read_idx_0_d;
+wire [(5-1):0] read_idx_0_d;
wire read_enable_1_d;
-wire [ (5-1):0] read_idx_1_d;
-wire [ (5-1):0] write_idx_d;
-reg [ (5-1):0] write_idx_x;
-reg [ (5-1):0] write_idx_m;
-reg [ (5-1):0] write_idx_w;
-wire [ (3-1):0] csr_d;
-reg [ (3-1):0] csr_x;
-wire [ (3-1):0] condition_d;
-reg [ (3-1):0] condition_x;
-
+wire [(5-1):0] read_idx_1_d;
+wire [(5-1):0] write_idx_d;
+reg [(5-1):0] write_idx_x;
+reg [(5-1):0] write_idx_m;
+reg [(5-1):0] write_idx_w;
+wire [(3-1):0] csr_d;
+reg [(3-1):0] csr_x;
+wire [(3-1):0] condition_d;
+reg [(3-1):0] condition_x;
+
-
wire scall_d;
reg scall_x;
wire eret_d;
reg eret_x;
wire eret_q_x;
reg eret_m;
-
+
-
-
+
@@ -78067,55 +71124,48 @@ reg eret_m;
-
wire csr_write_enable_d;
reg csr_write_enable_x;
wire csr_write_enable_q_x;
-
+
-
-
+
+reg [(32-1):0] d_result_0;
+reg [(32-1):0] d_result_1;
+reg [(32-1):0] x_result;
+reg [(32-1):0] m_result;
+reg [(32-1):0] w_result;
-reg [ (32-1):0] d_result_0;
-reg [ (32-1):0] d_result_1;
-reg [ (32-1):0] x_result;
-reg [ (32-1):0] m_result;
-reg [ (32-1):0] w_result;
-
-reg [ (32-1):0] operand_0_x;
-reg [ (32-1):0] operand_1_x;
-reg [ (32-1):0] store_operand_x;
-reg [ (32-1):0] operand_m;
-reg [ (32-1):0] operand_w;
+reg [(32-1):0] operand_0_x;
+reg [(32-1):0] operand_1_x;
+reg [(32-1):0] store_operand_x;
+reg [(32-1):0] operand_m;
+reg [(32-1):0] operand_w;
-
-
-reg [ (32-1):0] reg_data_live_0;
-reg [ (32-1):0] reg_data_live_1;
-reg use_buf;
-reg [ (32-1):0] reg_data_buf_0;
-reg [ (32-1):0] reg_data_buf_1;
-
-
+reg [(32-1):0] reg_data_live_0;
+reg [(32-1):0] reg_data_live_1;
+reg use_buf;
+reg [(32-1):0] reg_data_buf_0;
+reg [(32-1):0] reg_data_buf_1;
-
+
-wire [ (32-1):0] reg_data_0;
-wire [ (32-1):0] reg_data_1;
-reg [ (32-1):0] bypass_data_0;
-reg [ (32-1):0] bypass_data_1;
+wire [(32-1):0] reg_data_0;
+wire [(32-1):0] reg_data_1;
+reg [(32-1):0] bypass_data_0;
+reg [(32-1):0] bypass_data_1;
wire reg_write_enable_q_w;
reg interlock;
@@ -78130,16 +71180,16 @@ wire stall_m;
wire adder_op_d;
reg adder_op_x;
reg adder_op_x_n;
-wire [ (32-1):0] adder_result_x;
+wire [(32-1):0] adder_result_x;
wire adder_overflow_x;
wire adder_carry_n_x;
-wire [ 3:0] logic_op_d;
-reg [ 3:0] logic_op_x;
-wire [ (32-1):0] logic_result_x;
+wire [3:0] logic_op_d;
+reg [3:0] logic_op_x;
+wire [(32-1):0] logic_result_x;
-
+
@@ -78147,8 +71197,7 @@ wire [ (32-1):0] logic_result_x;
-
-
+
@@ -78158,33 +71207,27 @@ wire [ (32-1):0] logic_result_x;
-
-
+
-
-
-
-wire [ (32-1):0] shifter_result_x;
+wire [(32-1):0] shifter_result_x;
-
+
-
-
+
-
-
+
@@ -78193,54 +71236,45 @@ wire [ (32-1):0] shifter_result_x;
-
-
+
-
-
-
-wire [ (32-1):0] interrupt_csr_read_data_x;
+wire [(32-1):0] interrupt_csr_read_data_x;
-wire [ (32-1):0] cfg;
-wire [ (32-1):0] cfg2;
-
+wire [(32-1):0] cfg;
+wire [(32-1):0] cfg2;
+
-
-reg [ (32-1):0] csr_read_data_x;
+reg [(32-1):0] csr_read_data_x;
-wire [ ((32-2)+2-1):2] pc_f;
-wire [ ((32-2)+2-1):2] pc_d;
-wire [ ((32-2)+2-1):2] pc_x;
-wire [ ((32-2)+2-1):2] pc_m;
-wire [ ((32-2)+2-1):2] pc_w;
-
+wire [((32-2)+2-1):2] pc_f;
+wire [((32-2)+2-1):2] pc_d;
+wire [((32-2)+2-1):2] pc_x;
+wire [((32-2)+2-1):2] pc_m;
+wire [((32-2)+2-1):2] pc_w;
+
-
-
-
-wire [ (32-1):0] instruction_f;
+wire [(32-1):0] instruction_f;
-wire [ (32-1):0] instruction_d;
-
+wire [(32-1):0] instruction_d;
+
-
-
+
@@ -78249,8 +71283,7 @@ wire [ (32-1):0] instruction_d;
-
-
+
@@ -78258,12 +71291,11 @@ wire [ (32-1):0] instruction_d;
-
-wire [ (32-1):0] load_data_w;
+wire [(32-1):0] load_data_w;
wire stall_wb_load;
-
+
@@ -78283,7 +71315,6 @@ wire stall_wb_load;
-
wire raw_x_0;
@@ -78300,10 +71331,9 @@ wire cmp_overflow;
wire cmp_carry_n;
reg condition_met_x;
reg condition_met_m;
-
+
-
wire branch_taken_m;
wire kill_f;
@@ -78312,19 +71342,17 @@ wire kill_x;
wire kill_m;
wire kill_w;
-reg [ (32-2)+2-1:8] eba;
-
+reg [(32-2)+2-1:8] eba;
+
-
-reg [ (3-1):0] eid_x;
-
+reg [(3-1):0] eid_x;
+
-
-
+
@@ -78339,43 +71367,35 @@ reg [ (3-1):0] eid_x;
-
wire exception_x;
reg exception_m;
reg exception_w;
wire exception_q_w;
-
-
+
-
-
-
-wire interrupt_exception;
+wire interrupt_exception;
-
+
-
-
+
-
-
+
-
wire system_call_exception;
-
+
@@ -78383,10 +71403,7 @@ wire system_call_exception;
-
-
-
-
+
@@ -78442,7 +71459,6 @@ endfunction
-
lm32_instruction_unit_minimal #(
.associativity (icache_associativity),
.sets (icache_sets),
@@ -78464,47 +71480,40 @@ lm32_instruction_unit_minimal #(
.kill_f (kill_f),
.branch_predict_taken_d (branch_predict_taken_d),
.branch_predict_address_d (branch_predict_address_d),
-
+
-
.exception_m (exception_m),
.branch_taken_m (branch_taken_m),
.branch_mispredict_taken_m (branch_mispredict_taken_m),
.branch_target_m (branch_target_m),
-
+
-
-
+
-
-
+
-
-
-
+
.i_dat_i (I_DAT_I),
.i_ack_i (I_ACK_I),
.i_err_i (I_ERR_I),
.i_rty_i (I_RTY_I),
-
-
+
-
.pc_f (pc_f),
@@ -78512,19 +71521,16 @@ lm32_instruction_unit_minimal #(
.pc_x (pc_x),
.pc_m (pc_m),
.pc_w (pc_w),
-
+
-
-
+
-
-
-
+
.i_dat_o (I_DAT_O),
.i_adr_o (I_ADR_O),
@@ -78535,21 +71541,16 @@ lm32_instruction_unit_minimal #(
.i_cti_o (I_CTI_O),
.i_lock_o (I_LOCK_O),
.i_bte_o (I_BTE_O),
-
-
+
-
-
+
-
-
-
- .instruction_f (instruction_f),
+ .instruction_f (instruction_f),
.instruction_d (instruction_d)
);
@@ -78562,35 +71563,28 @@ lm32_decoder_minimal decoder (
.d_result_sel_0 (d_result_sel_0_d),
.d_result_sel_1 (d_result_sel_1_d),
.x_result_sel_csr (x_result_sel_csr_d),
-
+
-
-
-
+
.x_result_sel_shift (x_result_sel_shift_d),
-
-
+
-
.x_result_sel_logic (x_result_sel_logic_d),
-
+
-
.x_result_sel_add (x_result_sel_add_d),
.m_result_sel_compare (m_result_sel_compare_d),
-
+
-
.w_result_sel_load (w_result_sel_load_d),
-
+
-
.x_bypass_enable (x_bypass_enable_d),
.m_bypass_enable (m_bypass_enable_d),
.read_enable_0 (read_enable_0_d),
@@ -78607,43 +71601,36 @@ lm32_decoder_minimal decoder (
.sign_extend (sign_extend_d),
.adder_op (adder_op_d),
.logic_op (logic_op_d),
-
+
-
-
+
-
-
+
-
-
+
-
.branch (branch_d),
.bi_unconditional (bi_unconditional),
.bi_conditional (bi_conditional),
.branch_reg (branch_reg_d),
.condition (condition_d),
-
+
-
.scall (scall_d),
.eret (eret_d),
-
+
-
-
+
-
.csr_write_enable (csr_write_enable_d)
);
@@ -78677,14 +71664,12 @@ lm32_load_store_unit_minimal #(
.store_q_m (store_q_m),
.sign_extend_x (sign_extend_x),
.size_x (size_x),
-
+
-
-
+
-
.d_dat_i (D_DAT_I),
.d_ack_i (D_ACK_I),
@@ -78692,20 +71677,18 @@ lm32_load_store_unit_minimal #(
.d_rty_i (D_RTY_I),
-
+
-
-
+
-
.load_data_w (load_data_w),
.stall_wb_load (stall_wb_load),
@@ -78744,7 +71727,7 @@ lm32_logic_op logic_op (
.logic_result_x (logic_result_x)
);
-
+
@@ -78760,8 +71743,7 @@ lm32_logic_op logic_op (
-
-
+
@@ -78776,8 +71758,7 @@ lm32_logic_op logic_op (
-
-
+
@@ -78806,11 +71787,9 @@ lm32_logic_op logic_op (
-
-
-
+
lm32_interrupt_minimal interrupt_unit (
@@ -78820,19 +71799,16 @@ lm32_interrupt_minimal interrupt_unit (
.interrupt (interrupt),
.stall_x (stall_x),
-
+
-
.exception (exception_q_w),
-
.eret_q_x (eret_q_x),
-
+
-
.csr (csr_x),
.csr_write_data (operand_1_x),
.csr_write_enable (csr_write_enable_q_x),
@@ -78841,10 +71817,9 @@ lm32_interrupt_minimal interrupt_unit (
.csr_read_data (interrupt_csr_read_data_x)
);
-
-
+
@@ -78894,8 +71869,7 @@ lm32_interrupt_minimal interrupt_unit (
-
-
+
@@ -78938,9 +71912,7 @@ lm32_interrupt_minimal interrupt_unit (
-
-
-
+
@@ -79001,8 +71973,8 @@ lm32_interrupt_minimal interrupt_unit (
- always @(posedge clk_i )
- if (rst_i == 1'b1)
+ always @(posedge clk_i )
+ if (rst_i == 1'b1)
begin
regfile_raw_0 <= 1'b0;
regfile_raw_1 <= 1'b0;
@@ -79057,10 +72029,9 @@ lm32_interrupt_minimal interrupt_unit (
.rdata_o (regfile_data_1)
);
-
-
+
@@ -79133,58 +72104,53 @@ lm32_interrupt_minimal interrupt_unit (
-
-
-
+
assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
-
-
-
+
-
-assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == 1'b1);
-assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == 1'b1);
-assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == 1'b1);
-assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == 1'b1);
-assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == 1'b1);
-assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == 1'b1);
+assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == 1'b1);
+assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == 1'b1);
+assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == 1'b1);
+assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == 1'b1);
+assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == 1'b1);
+assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == 1'b1);
always @(*)
begin
- if ( ( (x_bypass_enable_x == 1'b0)
- && ( ((read_enable_0_d == 1'b1) && (raw_x_0 == 1'b1))
- || ((read_enable_1_d == 1'b1) && (raw_x_1 == 1'b1))
+ if ( ( (x_bypass_enable_x == 1'b0)
+ && ( ((read_enable_0_d == 1'b1) && (raw_x_0 == 1'b1))
+ || ((read_enable_1_d == 1'b1) && (raw_x_1 == 1'b1))
)
)
- || ( (m_bypass_enable_m == 1'b0)
- && ( ((read_enable_0_d == 1'b1) && (raw_m_0 == 1'b1))
- || ((read_enable_1_d == 1'b1) && (raw_m_1 == 1'b1))
+ || ( (m_bypass_enable_m == 1'b0)
+ && ( ((read_enable_0_d == 1'b1) && (raw_m_0 == 1'b1))
+ || ((read_enable_1_d == 1'b1) && (raw_m_1 == 1'b1))
)
)
)
- interlock = 1'b1;
+ interlock = 1'b1;
else
- interlock = 1'b0;
+ interlock = 1'b0;
end
always @(*)
begin
- if (raw_x_0 == 1'b1)
+ if (raw_x_0 == 1'b1)
bypass_data_0 = x_result;
- else if (raw_m_0 == 1'b1)
+ else if (raw_m_0 == 1'b1)
bypass_data_0 = m_result;
- else if (raw_w_0 == 1'b1)
+ else if (raw_w_0 == 1'b1)
bypass_data_0 = w_result;
else
bypass_data_0 = reg_data_0;
@@ -79193,11 +72159,11 @@ end
always @(*)
begin
- if (raw_x_1 == 1'b1)
+ if (raw_x_1 == 1'b1)
bypass_data_1 = x_result;
- else if (raw_m_1 == 1'b1)
+ else if (raw_m_1 == 1'b1)
bypass_data_1 = m_result;
- else if (raw_w_1 == 1'b1)
+ else if (raw_w_1 == 1'b1)
bypass_data_1 = w_result;
else
bypass_data_1 = reg_data_1;
@@ -79225,51 +72191,47 @@ always @(*)
begin
d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
case (d_result_sel_1_d)
- 2'b00: d_result_1 = { 32{1'b0}};
- 2'b01: d_result_1 = bypass_data_1;
- 2'b10: d_result_1 = immediate_d;
- default: d_result_1 = { 32{1'bx}};
+ 2'b00: d_result_1 = {32{1'b0}};
+ 2'b01: d_result_1 = bypass_data_1;
+ 2'b10: d_result_1 = immediate_d;
+ default: d_result_1 = {32{1'bx}};
endcase
end
-
+
-
-
+
-
-
-
-
-assign shifter_result_x = {operand_0_x[ 32-1] & sign_extend_x, operand_0_x[ 32-1:1]};
+assign shifter_result_x = {operand_0_x[32-1] & sign_extend_x, operand_0_x[32-1:1]};
+
assign cmp_zero = operand_0_x == operand_1_x;
-assign cmp_negative = adder_result_x[ 32-1];
+assign cmp_negative = adder_result_x[32-1];
assign cmp_overflow = adder_overflow_x;
assign cmp_carry_n = adder_carry_n_x;
always @(*)
begin
case (condition_x)
- 3'b000: condition_met_x = 1'b1;
- 3'b110: condition_met_x = 1'b1;
- 3'b001: condition_met_x = cmp_zero;
- 3'b111: condition_met_x = !cmp_zero;
- 3'b010: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
- 3'b101: condition_met_x = cmp_carry_n && !cmp_zero;
- 3'b011: condition_met_x = cmp_negative == cmp_overflow;
- 3'b100: condition_met_x = cmp_carry_n;
+ 3'b000: condition_met_x = 1'b1;
+ 3'b110: condition_met_x = 1'b1;
+ 3'b001: condition_met_x = cmp_zero;
+ 3'b111: condition_met_x = !cmp_zero;
+ 3'b010: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
+ 3'b101: condition_met_x = cmp_carry_n && !cmp_zero;
+ 3'b011: condition_met_x = cmp_negative == cmp_overflow;
+ 3'b100: condition_met_x = cmp_carry_n;
default: condition_met_x = 1'bx;
endcase
end
@@ -79279,34 +72241,28 @@ always @(*)
begin
x_result = x_result_sel_add_x ? adder_result_x
: x_result_sel_csr_x ? csr_read_data_x
-
+
-
-
+
-
-
-
- : x_result_sel_shift_x ? shifter_result_x
+ : x_result_sel_shift_x ? shifter_result_x
-
+
-
: logic_result_x;
end
always @(*)
begin
- m_result = m_result_sel_compare_m ? {{ 32-1{1'b0}}, condition_met_m}
-
+ m_result = m_result_sel_compare_m ? {{32-1{1'b0}}, condition_met_m}
+
-
: operand_m;
end
@@ -79314,14 +72270,13 @@ end
always @(*)
begin
w_result = w_result_sel_load_w ? load_data_w
-
+
-
: operand_w;
end
-
+
@@ -79332,95 +72287,85 @@ end
-
-assign branch_taken_m = (stall_m == 1'b0)
- && ( ( (branch_m == 1'b1)
- && (valid_m == 1'b1)
- && ( ( (condition_met_m == 1'b1)
- && (branch_predict_taken_m == 1'b0)
+assign branch_taken_m = (stall_m == 1'b0)
+ && ( ( (branch_m == 1'b1)
+ && (valid_m == 1'b1)
+ && ( ( (condition_met_m == 1'b1)
+ && (branch_predict_taken_m == 1'b0)
)
- || ( (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1)
+ || ( (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1)
)
)
)
- || (exception_m == 1'b1)
+ || (exception_m == 1'b1)
);
-assign branch_mispredict_taken_m = (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1);
+assign branch_mispredict_taken_m = (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1);
-assign branch_flushX_m = (stall_m == 1'b0)
- && ( ( (branch_m == 1'b1)
- && (valid_m == 1'b1)
- && ( (condition_met_m == 1'b1)
- || ( (condition_met_m == 1'b0)
- && (branch_predict_m == 1'b1)
- && (branch_predict_taken_m == 1'b1)
+assign branch_flushX_m = (stall_m == 1'b0)
+ && ( ( (branch_m == 1'b1)
+ && (valid_m == 1'b1)
+ && ( (condition_met_m == 1'b1)
+ || ( (condition_met_m == 1'b0)
+ && (branch_predict_m == 1'b1)
+ && (branch_predict_taken_m == 1'b1)
)
)
)
- || (exception_m == 1'b1)
+ || (exception_m == 1'b1)
);
-assign kill_f = ( (valid_d == 1'b1)
- && (branch_predict_taken_d == 1'b1)
+assign kill_f = ( (valid_d == 1'b1)
+ && (branch_predict_taken_d == 1'b1)
)
- || (branch_taken_m == 1'b1)
-
+ || (branch_taken_m == 1'b1)
+
-
-
+
-
-
+
-
;
-assign kill_d = (branch_taken_m == 1'b1)
-
+assign kill_d = (branch_taken_m == 1'b1)
+
-
-
+
-
-
+
-
;
-assign kill_x = (branch_flushX_m == 1'b1)
-
+assign kill_x = (branch_flushX_m == 1'b1)
+
-
;
-assign kill_m = 1'b0
-
+assign kill_m = 1'b0
+
-
;
-assign kill_w = 1'b0
-
+assign kill_w = 1'b0
+
-
;
-
+
@@ -79432,33 +72377,28 @@ assign kill_w = 1'b0
-
-
+
-
-
+
-
-
+
-
-assign system_call_exception = ( (scall_x == 1'b1)
-
+assign system_call_exception = ( (scall_x == 1'b1)
+
-
);
-
+
@@ -79489,40 +72429,32 @@ assign system_call_exception = ( (scall_x == 1'b1)
-
-assign exception_x = (system_call_exception == 1'b1)
-
+assign exception_x = (system_call_exception == 1'b1)
+
-
-
+
-
-
-
- || ( (interrupt_exception == 1'b1)
-
+
+ || ( (interrupt_exception == 1'b1)
+
-
-
+
-
)
-
;
-
always @(*)
begin
-
+
@@ -79537,8 +72469,7 @@ begin
-
-
+
@@ -79546,60 +72477,53 @@ begin
-
-
+
-
-
+
-
-
-
- if ( (interrupt_exception == 1'b1)
-
+
+ if ( (interrupt_exception == 1'b1)
+
-
)
- eid_x = 3'h6;
+ eid_x = 3'h6;
else
-
- eid_x = 3'h7;
+ eid_x = 3'h7;
end
-assign stall_a = (stall_f == 1'b1);
+assign stall_a = (stall_f == 1'b1);
-assign stall_f = (stall_d == 1'b1);
+assign stall_f = (stall_d == 1'b1);
-assign stall_d = (stall_x == 1'b1)
- || ( (interlock == 1'b1)
- && (kill_d == 1'b0)
+assign stall_d = (stall_x == 1'b1)
+ || ( (interlock == 1'b1)
+ && (kill_d == 1'b0)
)
- || ( ( (eret_d == 1'b1)
- || (scall_d == 1'b1)
-
+ || ( ( (eret_d == 1'b1)
+ || (scall_d == 1'b1)
+
-
)
- && ( (load_q_x == 1'b1)
- || (load_q_m == 1'b1)
- || (store_q_x == 1'b1)
- || (store_q_m == 1'b1)
- || (D_CYC_O == 1'b1)
+ && ( (load_q_x == 1'b1)
+ || (load_q_m == 1'b1)
+ || (store_q_x == 1'b1)
+ || (store_q_m == 1'b1)
+ || (D_CYC_O == 1'b1)
)
- && (kill_d == 1'b0)
+ && (kill_d == 1'b0)
)
-
+
@@ -79611,21 +72535,19 @@ assign stall_d = (stall_x == 1'b1)
-
- || ( (csr_write_enable_d == 1'b1)
- && (load_q_x == 1'b1)
+ || ( (csr_write_enable_d == 1'b1)
+ && (load_q_x == 1'b1)
)
;
-assign stall_x = (stall_m == 1'b1)
-
+assign stall_x = (stall_m == 1'b1)
+
-
-
+
@@ -79634,16 +72556,14 @@ assign stall_x = (stall_m == 1'b1)
-
;
-assign stall_m = (stall_wb_load == 1'b1)
-
+assign stall_m = (stall_wb_load == 1'b1)
+
-
- || ( (D_CYC_O == 1'b1)
- && ( (store_m == 1'b1)
+ || ( (D_CYC_O == 1'b1)
+ && ( (store_m == 1'b1)
@@ -79657,215 +72577,168 @@ assign stall_m = (stall_wb_load == 1'b1)
-
-
- || ((store_x == 1'b1) && (interrupt_exception == 1'b1))
+ || ((store_x == 1'b1) && (interrupt_exception == 1'b1))
- || (load_m == 1'b1)
- || (load_x == 1'b1)
+ || (load_m == 1'b1)
+ || (load_x == 1'b1)
)
)
-
-
+
-
-
+
-
-
-
- || (I_CYC_O == 1'b1)
+ || (I_CYC_O == 1'b1)
-
-
+
-
;
-
+
-
-
+
-
-
+
-
-
+
-
-assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
-assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
-assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
-
+assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
+assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
+assign eret_q_x = (eret_x == 1'b1) && (q_x == 1'b1);
+
-
-assign load_q_x = (load_x == 1'b1)
- && (q_x == 1'b1)
-
+assign load_q_x = (load_x == 1'b1)
+ && (q_x == 1'b1)
+
-
;
-assign store_q_x = (store_x == 1'b1)
- && (q_x == 1'b1)
-
+assign store_q_x = (store_x == 1'b1)
+ && (q_x == 1'b1)
+
-
;
-
+
-
-assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
-assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
-assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
-
+assign q_m = (valid_m == 1'b1) && (kill_m == 1'b0) && (exception_m == 1'b0);
+assign load_q_m = (load_m == 1'b1) && (q_m == 1'b1);
+assign store_q_m = (store_m == 1'b1) && (q_m == 1'b1);
+
-
-assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1));
-
+assign exception_q_w = ((exception_w == 1'b1) && (valid_w == 1'b1));
-assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
-assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
-assign write_enable_q_w = (write_enable_w == 1'b1) && (valid_w == 1'b1);
+assign write_enable_q_x = (write_enable_x == 1'b1) && (valid_x == 1'b1) && (branch_flushX_m == 1'b0);
+assign write_enable_q_m = (write_enable_m == 1'b1) && (valid_m == 1'b1);
+assign write_enable_q_w = (write_enable_w == 1'b1) && (valid_w == 1'b1);
-assign reg_write_enable_q_w = (write_enable_w == 1'b1) && (kill_w == 1'b0) && (valid_w == 1'b1);
+assign reg_write_enable_q_w = (write_enable_w == 1'b1) && (kill_w == 1'b0) && (valid_w == 1'b1);
assign cfg = {
- 6'h02,
+ 6'h02,
watchpoints[3:0],
breakpoints[3:0],
interrupts[5:0],
-
+
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
+ 1'b0,
- 1'b0,
-
-
-
+
-
- 1'b0
-
+ 1'b0
};
assign cfg2 = {
30'b0,
-
+
+ 1'b0,
- 1'b0,
-
-
-
- 1'b0
-
+ 1'b0
};
-
+
@@ -79878,9 +72751,8 @@ assign cfg2 = {
-
-
+
@@ -79890,41 +72762,35 @@ assign cfg2 = {
-
-assign csr_d = read_idx_0_d[ (3-1):0];
+assign csr_d = read_idx_0_d[(3-1):0];
always @(*)
begin
case (csr_x)
-
-
- 3'h0,
- 3'h1,
- 3'h2: csr_read_data_x = interrupt_csr_read_data_x;
+ 3'h0,
+ 3'h1,
+ 3'h2: csr_read_data_x = interrupt_csr_read_data_x;
-
+
-
- 3'h6: csr_read_data_x = cfg;
- 3'h7: csr_read_data_x = {eba, 8'h00};
-
+ 3'h6: csr_read_data_x = cfg;
+ 3'h7: csr_read_data_x = {eba, 8'h00};
+
-
-
+
-
- 3'ha: csr_read_data_x = cfg2;
+ 3'ha: csr_read_data_x = cfg2;
- default: csr_read_data_x = { 32{1'bx}};
+ default: csr_read_data_x = {32{1'bx}};
endcase
end
@@ -79933,23 +72799,22 @@ end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
- eba <= eba_reset[ (32-2)+2-1:8];
+ if (rst_i == 1'b1)
+ eba <= eba_reset[(32-2)+2-1:8];
else
begin
- if ((csr_write_enable_q_x == 1'b1) && (csr_x == 3'h7) && (stall_x == 1'b0))
- eba <= operand_1_x[ (32-2)+2-1:8];
-
+ if ((csr_write_enable_q_x == 1'b1) && (csr_x == 3'h7) && (stall_x == 1'b0))
+ eba <= operand_1_x[(32-2)+2-1:8];
+
-
end
end
-
+
@@ -79968,8 +72833,7 @@ end
-
-
+
@@ -79979,8 +72843,7 @@ end
-
-
+
@@ -79997,11 +72860,10 @@ end
-
-
+
@@ -80028,8 +72890,7 @@ end
-
-
+
@@ -80040,245 +72901,211 @@ end
-
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- valid_f <= 1'b0;
- valid_d <= 1'b0;
- valid_x <= 1'b0;
- valid_m <= 1'b0;
- valid_w <= 1'b0;
+ valid_f <= 1'b0;
+ valid_d <= 1'b0;
+ valid_x <= 1'b0;
+ valid_m <= 1'b0;
+ valid_w <= 1'b0;
end
else
begin
- if ((kill_f == 1'b1) || (stall_a == 1'b0))
-
+ if ((kill_f == 1'b1) || (stall_a == 1'b0))
+
-
- valid_f <= 1'b1;
-
+ valid_f <= 1'b1;
- else if (stall_f == 1'b0)
- valid_f <= 1'b0;
+ else if (stall_f == 1'b0)
+ valid_f <= 1'b0;
- if (kill_d == 1'b1)
- valid_d <= 1'b0;
- else if (stall_f == 1'b0)
+ if (kill_d == 1'b1)
+ valid_d <= 1'b0;
+ else if (stall_f == 1'b0)
valid_d <= valid_f & !kill_f;
- else if (stall_d == 1'b0)
- valid_d <= 1'b0;
+ else if (stall_d == 1'b0)
+ valid_d <= 1'b0;
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
valid_x <= valid_d & !kill_d;
- else if (kill_x == 1'b1)
- valid_x <= 1'b0;
- else if (stall_x == 1'b0)
- valid_x <= 1'b0;
-
- if (kill_m == 1'b1)
- valid_m <= 1'b0;
- else if (stall_x == 1'b0)
+ else if (kill_x == 1'b1)
+ valid_x <= 1'b0;
+ else if (stall_x == 1'b0)
+ valid_x <= 1'b0;
+
+ if (kill_m == 1'b1)
+ valid_m <= 1'b0;
+ else if (stall_x == 1'b0)
valid_m <= valid_x & !kill_x;
- else if (stall_m == 1'b0)
- valid_m <= 1'b0;
+ else if (stall_m == 1'b0)
+ valid_m <= 1'b0;
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
valid_w <= valid_m & !kill_m;
else
- valid_w <= 1'b0;
+ valid_w <= 1'b0;
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
-
+
-
- operand_0_x <= { 32{1'b0}};
- operand_1_x <= { 32{1'b0}};
- store_operand_x <= { 32{1'b0}};
- branch_target_x <= { (32-2){1'b0}};
- x_result_sel_csr_x <= 1'b0;
-
+ operand_0_x <= {32{1'b0}};
+ operand_1_x <= {32{1'b0}};
+ store_operand_x <= {32{1'b0}};
+ branch_target_x <= {(32-2){1'b0}};
+ x_result_sel_csr_x <= 1'b0;
+
+
+ x_result_sel_shift_x <= 1'b0;
-
-
- x_result_sel_shift_x <= 1'b0;
-
-
-
- x_result_sel_logic_x <= 1'b0;
-
+ x_result_sel_logic_x <= 1'b0;
+
-
- x_result_sel_add_x <= 1'b0;
- m_result_sel_compare_x <= 1'b0;
-
+ x_result_sel_add_x <= 1'b0;
+ m_result_sel_compare_x <= 1'b0;
+
-
- w_result_sel_load_x <= 1'b0;
-
+ w_result_sel_load_x <= 1'b0;
+
-
- x_bypass_enable_x <= 1'b0;
- m_bypass_enable_x <= 1'b0;
- write_enable_x <= 1'b0;
- write_idx_x <= { 5{1'b0}};
- csr_x <= { 3{1'b0}};
- load_x <= 1'b0;
- store_x <= 1'b0;
- size_x <= { 2{1'b0}};
- sign_extend_x <= 1'b0;
- adder_op_x <= 1'b0;
- adder_op_x_n <= 1'b0;
+ x_bypass_enable_x <= 1'b0;
+ m_bypass_enable_x <= 1'b0;
+ write_enable_x <= 1'b0;
+ write_idx_x <= {5{1'b0}};
+ csr_x <= {3{1'b0}};
+ load_x <= 1'b0;
+ store_x <= 1'b0;
+ size_x <= {2{1'b0}};
+ sign_extend_x <= 1'b0;
+ adder_op_x <= 1'b0;
+ adder_op_x_n <= 1'b0;
logic_op_x <= 4'h0;
-
+
-
-
+
-
- branch_x <= 1'b0;
- branch_predict_x <= 1'b0;
- branch_predict_taken_x <= 1'b0;
- condition_x <= 3'b000;
-
+ branch_x <= 1'b0;
+ branch_predict_x <= 1'b0;
+ branch_predict_taken_x <= 1'b0;
+ condition_x <= 3'b000;
+
-
- scall_x <= 1'b0;
- eret_x <= 1'b0;
-
+ scall_x <= 1'b0;
+ eret_x <= 1'b0;
+
-
-
+
-
- csr_write_enable_x <= 1'b0;
- operand_m <= { 32{1'b0}};
- branch_target_m <= { (32-2){1'b0}};
- m_result_sel_compare_m <= 1'b0;
-
+ csr_write_enable_x <= 1'b0;
+ operand_m <= {32{1'b0}};
+ branch_target_m <= {(32-2){1'b0}};
+ m_result_sel_compare_m <= 1'b0;
+
-
- w_result_sel_load_m <= 1'b0;
-
+ w_result_sel_load_m <= 1'b0;
+
-
- m_bypass_enable_m <= 1'b0;
- branch_m <= 1'b0;
- branch_predict_m <= 1'b0;
- branch_predict_taken_m <= 1'b0;
- exception_m <= 1'b0;
- load_m <= 1'b0;
- store_m <= 1'b0;
-
+ m_bypass_enable_m <= 1'b0;
+ branch_m <= 1'b0;
+ branch_predict_m <= 1'b0;
+ branch_predict_taken_m <= 1'b0;
+ exception_m <= 1'b0;
+ load_m <= 1'b0;
+ store_m <= 1'b0;
+
-
- write_enable_m <= 1'b0;
- write_idx_m <= { 5{1'b0}};
- condition_met_m <= 1'b0;
-
+ write_enable_m <= 1'b0;
+ write_idx_m <= {5{1'b0}};
+ condition_met_m <= 1'b0;
+
-
-
+
-
- operand_w <= { 32{1'b0}};
- w_result_sel_load_w <= 1'b0;
-
+ operand_w <= {32{1'b0}};
+ w_result_sel_load_w <= 1'b0;
+
-
- write_idx_w <= { 5{1'b0}};
- write_enable_w <= 1'b0;
-
+ write_idx_w <= {5{1'b0}};
+ write_enable_w <= 1'b0;
+
+ exception_w <= 1'b0;
- exception_w <= 1'b0;
-
-
-
end
else
begin
- if (stall_x == 1'b0)
+ if (stall_x == 1'b0)
begin
-
+
-
operand_0_x <= d_result_0;
operand_1_x <= d_result_1;
store_operand_x <= bypass_data_1;
- branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((32-2)+2-1):2] : branch_target_d;
+ branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[((32-2)+2-1):2] : branch_target_d;
x_result_sel_csr_x <= x_result_sel_csr_d;
-
+
-
-
-
+
x_result_sel_shift_x <= x_result_sel_shift_d;
-
-
+
-
x_result_sel_logic_x <= x_result_sel_logic_d;
-
+
-
x_result_sel_add_x <= x_result_sel_add_d;
m_result_sel_compare_x <= m_result_sel_compare_d;
-
+
-
w_result_sel_load_x <= w_result_sel_load_d;
-
+
-
x_bypass_enable_x <= x_bypass_enable_d;
m_bypass_enable_x <= m_bypass_enable_d;
load_x <= load_d;
@@ -80293,76 +73120,65 @@ begin
adder_op_x <= adder_op_d;
adder_op_x_n <= ~adder_op_d;
logic_op_x <= logic_op_d;
-
+
-
-
+
-
condition_x <= condition_d;
csr_write_enable_x <= csr_write_enable_d;
-
+
-
scall_x <= scall_d;
-
+
-
eret_x <= eret_d;
-
+
-
write_enable_x <= write_enable_d;
end
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
operand_m <= x_result;
m_result_sel_compare_m <= m_result_sel_compare_x;
-
+
-
- if (exception_x == 1'b1)
+ if (exception_x == 1'b1)
begin
- w_result_sel_load_m <= 1'b0;
-
+ w_result_sel_load_m <= 1'b0;
+
-
end
else
begin
w_result_sel_load_m <= w_result_sel_load_x;
-
+
-
end
m_bypass_enable_m <= m_bypass_enable_x;
-
+
-
load_m <= load_x;
store_m <= store_x;
-
+
-
branch_m <= branch_x;
branch_predict_m <= branch_predict_x;
branch_predict_taken_m <= branch_predict_taken_x;
-
-
+
@@ -80375,15 +73191,13 @@ begin
-
- if (exception_x == 1'b1)
- write_idx_m <= 5'd30;
+ if (exception_x == 1'b1)
+ write_idx_m <= 5'd30;
else
write_idx_m <= write_idx_x;
-
condition_met_m <= condition_met_x;
-
+
@@ -80394,80 +73208,67 @@ begin
+ branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
- branch_target_m <= exception_x == 1'b1 ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
-
-
-
-
+
-
eret_m <= eret_q_x;
-
+
-
- write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
-
+ write_enable_m <= exception_x == 1'b1 ? 1'b1 : write_enable_x;
+
-
end
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
- if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
- exception_m <= 1'b1;
+ if ((exception_x == 1'b1) && (q_x == 1'b1) && (stall_x == 1'b0))
+ exception_m <= 1'b1;
else
- exception_m <= 1'b0;
-
+ exception_m <= 1'b0;
+
-
end
-
+
-
- operand_w <= exception_m == 1'b1 ? {pc_m, 2'b00} : m_result;
-
+ operand_w <= exception_m == 1'b1 ? {pc_m, 2'b00} : m_result;
w_result_sel_load_w <= w_result_sel_load_m;
-
+
-
write_idx_w <= write_idx_m;
-
+
-
write_enable_w <= write_enable_m;
-
+
-
exception_w <= exception_m;
-
-
+
@@ -80475,33 +73276,31 @@ begin
-
end
end
-
-
+
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- use_buf <= 1'b0;
- reg_data_buf_0 <= { 32{1'b0}};
- reg_data_buf_1 <= { 32{1'b0}};
+ use_buf <= 1'b0;
+ reg_data_buf_0 <= {32{1'b0}};
+ reg_data_buf_1 <= {32{1'b0}};
end
else
begin
- if (stall_d == 1'b0)
- use_buf <= 1'b0;
- else if (use_buf == 1'b0)
+ if (stall_d == 1'b0)
+ use_buf <= 1'b0;
+ else if (use_buf == 1'b0)
begin
reg_data_buf_0 <= reg_data_live_0;
reg_data_buf_1 <= reg_data_live_1;
- use_buf <= 1'b1;
+ use_buf <= 1'b1;
end
- if (reg_write_enable_q_w == 1'b1)
+ if (reg_write_enable_q_w == 1'b1)
begin
if (write_idx_w == read_idx_0_d)
reg_data_buf_0 <= w_result;
@@ -80510,13 +73309,11 @@ begin
end
end
end
-
-
-
+
@@ -80560,8 +73357,7 @@ end
-
-
+
@@ -80620,7 +73416,6 @@ end
-
@@ -80633,13 +73428,9 @@ end
initial
begin
-
-
- reg_0.ram[0] = { 32{1'b0}};
- reg_1.ram[0] = { 32{1'b0}};
-
+
end
@@ -80687,10 +73478,7 @@ endmodule
-
-
-
-
+
@@ -80720,9 +73508,9 @@ endmodule
-
+
@@ -81007,8 +73795,6 @@ endmodule
-
-
@@ -81035,14 +73821,12 @@ module lm32_load_store_unit_minimal (
store_q_m,
sign_extend_x,
size_x,
-
+
-
-
+
-
d_dat_i,
d_ack_i,
@@ -81050,19 +73834,17 @@ module lm32_load_store_unit_minimal (
d_rty_i,
-
+
-
-
+
-
load_data_w,
stall_wb_load,
@@ -81107,9 +73889,9 @@ input kill_x;
input kill_m;
input exception_m;
-input [ (32-1):0] store_operand_x;
-input [ (32-1):0] load_store_address_x;
-input [ (32-1):0] load_store_address_m;
+input [(32-1):0] store_operand_x;
+input [(32-1):0] load_store_address_x;
+input [(32-1):0] load_store_address_m;
input [1:0] load_store_address_w;
input load_x;
input store_x;
@@ -81118,19 +73900,17 @@ input store_q_x;
input load_q_m;
input store_q_m;
input sign_extend_x;
-input [ 1:0] size_x;
+input [1:0] size_x;
-
+
-
-
+
-
-input [ (32-1):0] d_dat_i;
+input [(32-1):0] d_dat_i;
input d_ack_i;
input d_err_i;
input d_rty_i;
@@ -81139,7 +73919,7 @@ input d_rty_i;
-
+
@@ -81150,8 +73930,7 @@ input d_rty_i;
-
-
+
@@ -81160,50 +73939,49 @@ input d_rty_i;
-
-output [ (32-1):0] load_data_w;
-reg [ (32-1):0] load_data_w;
+output [(32-1):0] load_data_w;
+reg [(32-1):0] load_data_w;
output stall_wb_load;
reg stall_wb_load;
-output [ (32-1):0] d_dat_o;
-reg [ (32-1):0] d_dat_o;
-output [ (32-1):0] d_adr_o;
-reg [ (32-1):0] d_adr_o;
+output [(32-1):0] d_dat_o;
+reg [(32-1):0] d_dat_o;
+output [(32-1):0] d_adr_o;
+reg [(32-1):0] d_adr_o;
output d_cyc_o;
reg d_cyc_o;
-output [ (4-1):0] d_sel_o;
-reg [ (4-1):0] d_sel_o;
+output [(4-1):0] d_sel_o;
+reg [(4-1):0] d_sel_o;
output d_stb_o;
reg d_stb_o;
output d_we_o;
reg d_we_o;
-output [ (3-1):0] d_cti_o;
-reg [ (3-1):0] d_cti_o;
+output [(3-1):0] d_cti_o;
+reg [(3-1):0] d_cti_o;
output d_lock_o;
reg d_lock_o;
-output [ (2-1):0] d_bte_o;
-wire [ (2-1):0] d_bte_o;
+output [(2-1):0] d_bte_o;
+wire [(2-1):0] d_bte_o;
-reg [ 1:0] size_m;
-reg [ 1:0] size_w;
+reg [1:0] size_m;
+reg [1:0] size_w;
reg sign_extend_m;
reg sign_extend_w;
-reg [ (32-1):0] store_data_x;
-reg [ (32-1):0] store_data_m;
-reg [ (4-1):0] byte_enable_x;
-reg [ (4-1):0] byte_enable_m;
-wire [ (32-1):0] data_m;
-reg [ (32-1):0] data_w;
+reg [(32-1):0] store_data_x;
+reg [(32-1):0] store_data_m;
+reg [(4-1):0] byte_enable_x;
+reg [(4-1):0] byte_enable_m;
+wire [(32-1):0] data_m;
+reg [(32-1):0] data_w;
-
+
@@ -81214,8 +73992,7 @@ reg [ (32-1):0] data_w;
-
-
+
@@ -81223,25 +74000,21 @@ reg [ (32-1):0] data_w;
-
wire wb_select_x;
-
+
-
reg wb_select_m;
-reg [ (32-1):0] wb_data_m;
+reg [(32-1):0] wb_data_m;
reg wb_load_complete;
-
-
-
+
@@ -81296,8 +74069,7 @@ endfunction
-
-
+
@@ -81381,8 +74153,7 @@ endfunction
-
-
+
@@ -81421,20 +74192,17 @@ endfunction
-
-
+
-
-
+
-
-
+
@@ -81444,32 +74212,28 @@ endfunction
-
- assign wb_select_x = 1'b1
-
+ assign wb_select_x = 1'b1
+
-
-
+
-
-
+
-
;
always @(*)
begin
case (size_x)
- 2'b00: store_data_x = {4{store_operand_x[7:0]}};
- 2'b11: store_data_x = {2{store_operand_x[15:0]}};
- 2'b10: store_data_x = store_operand_x;
- default: store_data_x = { 32{1'bx}};
+ 2'b00: store_data_x = {4{store_operand_x[7:0]}};
+ 2'b11: store_data_x = {2{store_operand_x[15:0]}};
+ 2'b10: store_data_x = store_operand_x;
+ default: store_data_x = {32{1'bx}};
endcase
end
@@ -81477,18 +74241,18 @@ end
always @(*)
begin
casez ({size_x, load_store_address_x[1:0]})
- { 2'b00, 2'b11}: byte_enable_x = 4'b0001;
- { 2'b00, 2'b10}: byte_enable_x = 4'b0010;
- { 2'b00, 2'b01}: byte_enable_x = 4'b0100;
- { 2'b00, 2'b00}: byte_enable_x = 4'b1000;
- { 2'b11, 2'b1?}: byte_enable_x = 4'b0011;
- { 2'b11, 2'b0?}: byte_enable_x = 4'b1100;
- { 2'b10, 2'b??}: byte_enable_x = 4'b1111;
+ {2'b00, 2'b11}: byte_enable_x = 4'b0001;
+ {2'b00, 2'b10}: byte_enable_x = 4'b0010;
+ {2'b00, 2'b01}: byte_enable_x = 4'b0100;
+ {2'b00, 2'b00}: byte_enable_x = 4'b1000;
+ {2'b11, 2'b1?}: byte_enable_x = 4'b0011;
+ {2'b11, 2'b0?}: byte_enable_x = 4'b1100;
+ {2'b10, 2'b??}: byte_enable_x = 4'b1111;
default: byte_enable_x = 4'bxxxx;
endcase
end
-
+
@@ -81496,8 +74260,7 @@ end
-
-
+
@@ -81505,8 +74268,7 @@ end
-
-
+
@@ -81526,9 +74288,8 @@ end
-
-
+
@@ -81563,8 +74324,7 @@ end
-
-
+
@@ -81579,20 +74339,15 @@ end
-
-
+
-
assign data_m = wb_data_m;
-
-
-
@@ -81600,21 +74355,21 @@ end
always @(*)
begin
casez ({size_w, load_store_address_w[1:0]})
- { 2'b00, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
- { 2'b00, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
- { 2'b00, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
- { 2'b00, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
- { 2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
- { 2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
- { 2'b10, 2'b??}: load_data_w = data_w;
- default: load_data_w = { 32{1'bx}};
+ {2'b00, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
+ {2'b00, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
+ {2'b00, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
+ {2'b00, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
+ {2'b11, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
+ {2'b11, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
+ {2'b10, 2'b??}: load_data_w = data_w;
+ default: load_data_w = {32{1'bx}};
endcase
end
-assign d_bte_o = 2'b00;
+assign d_bte_o = 2'b00;
-
+
@@ -81648,74 +74403,69 @@ assign d_bte_o = 2'b00;
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- d_cyc_o <= 1'b0;
- d_stb_o <= 1'b0;
- d_dat_o <= { 32{1'b0}};
- d_adr_o <= { 32{1'b0}};
- d_sel_o <= { 4{ 1'b0}};
- d_we_o <= 1'b0;
- d_cti_o <= 3'b111;
- d_lock_o <= 1'b0;
- wb_data_m <= { 32{1'b0}};
- wb_load_complete <= 1'b0;
- stall_wb_load <= 1'b0;
-
+ d_cyc_o <= 1'b0;
+ d_stb_o <= 1'b0;
+ d_dat_o <= {32{1'b0}};
+ d_adr_o <= {32{1'b0}};
+ d_sel_o <= {4{1'b0}};
+ d_we_o <= 1'b0;
+ d_cti_o <= 3'b111;
+ d_lock_o <= 1'b0;
+ wb_data_m <= {32{1'b0}};
+ wb_load_complete <= 1'b0;
+ stall_wb_load <= 1'b0;
+
-
end
else
begin
-
+
-
- if (d_cyc_o == 1'b1)
+ if (d_cyc_o == 1'b1)
begin
- if ((d_ack_i == 1'b1) || (d_err_i == 1'b1))
+ if ((d_ack_i == 1'b1) || (d_err_i == 1'b1))
begin
-
+
-
begin
- d_cyc_o <= 1'b0;
- d_stb_o <= 1'b0;
- d_lock_o <= 1'b0;
+ d_cyc_o <= 1'b0;
+ d_stb_o <= 1'b0;
+ d_lock_o <= 1'b0;
end
-
+
-
wb_data_m <= d_dat_i;
wb_load_complete <= !d_we_o;
end
- if (d_err_i == 1'b1)
+ if (d_err_i == 1'b1)
$display ("Data bus error. Address: %x", d_adr_o);
end
else
begin
-
+
@@ -81728,115 +74478,106 @@ begin
-
- if ( (store_q_m == 1'b1)
- && (stall_m == 1'b0)
-
+ if ( (store_q_m == 1'b1)
+ && (stall_m == 1'b0)
+
-
-
+
-
)
begin
d_dat_o <= store_data_m;
d_adr_o <= load_store_address_m;
- d_cyc_o <= 1'b1;
+ d_cyc_o <= 1'b1;
d_sel_o <= byte_enable_m;
- d_stb_o <= 1'b1;
- d_we_o <= 1'b1;
- d_cti_o <= 3'b111;
+ d_stb_o <= 1'b1;
+ d_we_o <= 1'b1;
+ d_cti_o <= 3'b111;
end
- else if ( (load_q_m == 1'b1)
- && (wb_select_m == 1'b1)
- && (wb_load_complete == 1'b0)
+ else if ( (load_q_m == 1'b1)
+ && (wb_select_m == 1'b1)
+ && (wb_load_complete == 1'b0)
)
begin
- stall_wb_load <= 1'b0;
+ stall_wb_load <= 1'b0;
d_adr_o <= load_store_address_m;
- d_cyc_o <= 1'b1;
+ d_cyc_o <= 1'b1;
d_sel_o <= byte_enable_m;
- d_stb_o <= 1'b1;
- d_we_o <= 1'b0;
- d_cti_o <= 3'b111;
+ d_stb_o <= 1'b1;
+ d_we_o <= 1'b0;
+ d_cti_o <= 3'b111;
end
end
- if (stall_m == 1'b0)
- wb_load_complete <= 1'b0;
+ if (stall_m == 1'b0)
+ wb_load_complete <= 1'b0;
- if ((load_q_x == 1'b1) && (wb_select_x == 1'b1) && (stall_x == 1'b0))
- stall_wb_load <= 1'b1;
+ if ((load_q_x == 1'b1) && (wb_select_x == 1'b1) && (stall_x == 1'b0))
+ stall_wb_load <= 1'b1;
- if ((kill_m == 1'b1) || (exception_m == 1'b1))
- stall_wb_load <= 1'b0;
+ if ((kill_m == 1'b1) || (exception_m == 1'b1))
+ stall_wb_load <= 1'b0;
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- sign_extend_m <= 1'b0;
+ sign_extend_m <= 1'b0;
size_m <= 2'b00;
- byte_enable_m <= 1'b0;
- store_data_m <= { 32{1'b0}};
-
+ byte_enable_m <= 1'b0;
+ store_data_m <= {32{1'b0}};
+
-
-
+
-
-
+
-
- wb_select_m <= 1'b0;
+ wb_select_m <= 1'b0;
end
else
begin
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
begin
sign_extend_m <= sign_extend_x;
size_m <= size_x;
byte_enable_m <= byte_enable_x;
store_data_m <= store_data_x;
-
+
-
-
+
-
-
+
-
wb_select_m <= wb_select_x;
end
end
end
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
size_w <= 2'b00;
- data_w <= { 32{1'b0}};
- sign_extend_w <= 1'b0;
+ data_w <= {32{1'b0}};
+ sign_extend_w <= 1'b0;
end
else
begin
@@ -81855,11 +74596,11 @@ end
always @(posedge clk_i)
begin
- if (((load_q_m == 1'b1) || (store_q_m == 1'b1)) && (stall_m == 1'b0))
+ if (((load_q_m == 1'b1) || (store_q_m == 1'b1)) && (stall_m == 1'b0))
begin
- if ((size_m === 2'b11) && (load_store_address_m[0] !== 1'b0))
+ if ((size_m === 2'b11) && (load_store_address_m[0] !== 1'b0))
$display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
- if ((size_m === 2'b10) && (load_store_address_m[1:0] !== 2'b00))
+ if ((size_m === 2'b10) && (load_store_address_m[1:0] !== 2'b00))
$display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
end
end
@@ -81901,10 +74642,7 @@ endmodule
-
-
-
-
+
@@ -81934,9 +74672,9 @@ endmodule
-
+
@@ -82221,104 +74959,55 @@ endmodule
+
+
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -82331,35 +75020,28 @@ module lm32_decoder_minimal (
d_result_sel_0,
d_result_sel_1,
x_result_sel_csr,
-
+
-
-
-
+
x_result_sel_shift,
-
-
+
-
x_result_sel_logic,
-
+
-
x_result_sel_add,
m_result_sel_compare,
-
+
-
w_result_sel_load,
-
+
-
x_bypass_enable,
m_bypass_enable,
read_enable_0,
@@ -82376,43 +75058,36 @@ module lm32_decoder_minimal (
sign_extend,
adder_op,
logic_op,
-
+
-
-
+
-
-
+
-
-
+
-
branch,
branch_reg,
condition,
bi_conditional,
bi_unconditional,
-
+
-
scall,
eret,
-
+
-
-
+
-
csr_write_enable
);
@@ -82420,142 +75095,128 @@ module lm32_decoder_minimal (
-input [ (32-1):0] instruction;
+input [(32-1):0] instruction;
-output [ 0:0] d_result_sel_0;
-reg [ 0:0] d_result_sel_0;
-output [ 1:0] d_result_sel_1;
-reg [ 1:0] d_result_sel_1;
+output [0:0] d_result_sel_0;
+reg [0:0] d_result_sel_0;
+output [1:0] d_result_sel_1;
+reg [1:0] d_result_sel_1;
output x_result_sel_csr;
reg x_result_sel_csr;
-
+
-
-
-
+
output x_result_sel_shift;
reg x_result_sel_shift;
-
-
+
-
output x_result_sel_logic;
reg x_result_sel_logic;
-
+
-
output x_result_sel_add;
reg x_result_sel_add;
output m_result_sel_compare;
reg m_result_sel_compare;
-
+
-
output w_result_sel_load;
reg w_result_sel_load;
-
+
-
output x_bypass_enable;
wire x_bypass_enable;
output m_bypass_enable;
wire m_bypass_enable;
output read_enable_0;
wire read_enable_0;
-output [ (5-1):0] read_idx_0;
-wire [ (5-1):0] read_idx_0;
+output [(5-1):0] read_idx_0;
+wire [(5-1):0] read_idx_0;
output read_enable_1;
wire read_enable_1;
-output [ (5-1):0] read_idx_1;
-wire [ (5-1):0] read_idx_1;
+output [(5-1):0] read_idx_1;
+wire [(5-1):0] read_idx_1;
output write_enable;
wire write_enable;
-output [ (5-1):0] write_idx;
-wire [ (5-1):0] write_idx;
-output [ (32-1):0] immediate;
-wire [ (32-1):0] immediate;
-output [ ((32-2)+2-1):2] branch_offset;
-wire [ ((32-2)+2-1):2] branch_offset;
+output [(5-1):0] write_idx;
+wire [(5-1):0] write_idx;
+output [(32-1):0] immediate;
+wire [(32-1):0] immediate;
+output [((32-2)+2-1):2] branch_offset;
+wire [((32-2)+2-1):2] branch_offset;
output load;
wire load;
output store;
wire store;
-output [ 1:0] size;
-wire [ 1:0] size;
+output [1:0] size;
+wire [1:0] size;
output sign_extend;
wire sign_extend;
output adder_op;
wire adder_op;
-output [ 3:0] logic_op;
-wire [ 3:0] logic_op;
-
+output [3:0] logic_op;
+wire [3:0] logic_op;
+
-
-
+
-
-
+
-
-
+
-
output branch;
wire branch;
output branch_reg;
wire branch_reg;
-output [ (3-1):0] condition;
-wire [ (3-1):0] condition;
+output [(3-1):0] condition;
+wire [(3-1):0] condition;
output bi_conditional;
wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
-
+
-
output scall;
wire scall;
output eret;
wire eret;
-
+
-
-
+
-
output csr_write_enable;
wire csr_write_enable;
@@ -82563,10 +75224,10 @@ wire csr_write_enable;
-wire [ (32-1):0] extended_immediate;
-wire [ (32-1):0] high_immediate;
-wire [ (32-1):0] call_immediate;
-wire [ (32-1):0] branch_immediate;
+wire [(32-1):0] extended_immediate;
+wire [(32-1):0] high_immediate;
+wire [(32-1):0] call_immediate;
+wire [(32-1):0] branch_immediate;
wire sign_extend_immediate;
wire select_high_immediate;
wire select_call_immediate;
@@ -82575,371 +75236,7 @@ wire select_call_immediate;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-function integer clogb2;
-input [31:0] value;
-begin
- for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
- value = value >> 1;
-end
-endfunction
-
-function integer clogb2_v1;
-input [31:0] value;
-reg [31:0] i;
-reg [31:0] temp;
-begin
- temp = 0;
- i = 0;
- for (i = 0; temp < value; i = i + 1)
- temp = 1<<i;
- clogb2_v1 = i-1;
-end
-endfunction
-
-
-
-
-
-
-
-
-
-assign op_add = instruction[ 30:26] == 5'b01101;
-assign op_and = instruction[ 30:26] == 5'b01000;
-assign op_andhi = instruction[ 31:26] == 6'b011000;
-assign op_b = instruction[ 31:26] == 6'b110000;
-assign op_bi = instruction[ 31:26] == 6'b111000;
-assign op_be = instruction[ 31:26] == 6'b010001;
-assign op_bg = instruction[ 31:26] == 6'b010010;
-assign op_bge = instruction[ 31:26] == 6'b010011;
-assign op_bgeu = instruction[ 31:26] == 6'b010100;
-assign op_bgu = instruction[ 31:26] == 6'b010101;
-assign op_bne = instruction[ 31:26] == 6'b010111;
-assign op_call = instruction[ 31:26] == 6'b110110;
-assign op_calli = instruction[ 31:26] == 6'b111110;
-assign op_cmpe = instruction[ 30:26] == 5'b11001;
-assign op_cmpg = instruction[ 30:26] == 5'b11010;
-assign op_cmpge = instruction[ 30:26] == 5'b11011;
-assign op_cmpgeu = instruction[ 30:26] == 5'b11100;
-assign op_cmpgu = instruction[ 30:26] == 5'b11101;
-assign op_cmpne = instruction[ 30:26] == 5'b11111;
-
-
-
-
-assign op_lb = instruction[ 31:26] == 6'b000100;
-assign op_lbu = instruction[ 31:26] == 6'b010000;
-assign op_lh = instruction[ 31:26] == 6'b000111;
-assign op_lhu = instruction[ 31:26] == 6'b001011;
-assign op_lw = instruction[ 31:26] == 6'b001010;
-
-
-
-
-
-
-
-
-assign op_nor = instruction[ 30:26] == 5'b00001;
-assign op_or = instruction[ 30:26] == 5'b01110;
-assign op_orhi = instruction[ 31:26] == 6'b011110;
-assign op_raise = instruction[ 31:26] == 6'b101011;
-assign op_rcsr = instruction[ 31:26] == 6'b100100;
-assign op_sb = instruction[ 31:26] == 6'b001100;
-
-
-
-
-
-assign op_sh = instruction[ 31:26] == 6'b000011;
-
-
-
-
-assign op_sr = instruction[ 30:26] == 5'b00101;
-assign op_sru = instruction[ 30:26] == 5'b00000;
-assign op_sub = instruction[ 31:26] == 6'b110010;
-assign op_sw = instruction[ 31:26] == 6'b010110;
-assign op_user = instruction[ 31:26] == 6'b110011;
-assign op_wcsr = instruction[ 31:26] == 6'b110100;
-assign op_xnor = instruction[ 30:26] == 5'b01001;
-assign op_xor = instruction[ 30:26] == 5'b00110;
-
-
-assign arith = op_add | op_sub;
-assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
-assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
-assign bi_conditional = op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne;
-assign bi_unconditional = op_bi;
-assign bra = op_b | bi_unconditional | bi_conditional;
-assign call = op_call | op_calli;
-
-
-
-
-
-
-assign shift = op_sr | op_sru;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
-assign store = op_sb | op_sh | op_sw;
-
-
-always @(*)
-begin
-
- if (call)
- d_result_sel_0 = 1'b1;
- else
- d_result_sel_0 = 1'b0;
- if (call)
- d_result_sel_1 = 2'b00;
- else if ((instruction[31] == 1'b0) && !bra)
- d_result_sel_1 = 2'b10;
- else
- d_result_sel_1 = 2'b01;
-
- x_result_sel_csr = 1'b0;
-
-
-
-
-
-
- x_result_sel_shift = 1'b0;
-
-
-
-
-
-
- x_result_sel_logic = 1'b0;
-
-
-
-
- x_result_sel_add = 1'b0;
- if (op_rcsr)
- x_result_sel_csr = 1'b1;
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- else if (shift)
- x_result_sel_shift = 1'b1;
-
-
-
-
-
-
-
- else if (logical)
- x_result_sel_logic = 1'b1;
-
-
-
-
-
- else
- x_result_sel_add = 1'b1;
-
-
-
- m_result_sel_compare = cmp;
-
-
-
-
-
-
- w_result_sel_load = load;
-
-
-
-
-end
-
-
-assign x_bypass_enable = arith
- | logical
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- | shift
-
-
-
-
-
-
-
-
-
- | op_rcsr
- ;
-
-assign m_bypass_enable = x_bypass_enable
-
-
-
-
- | cmp
- ;
-
-assign read_enable_0 = ~(op_bi | op_calli);
-assign read_idx_0 = instruction[25:21];
-
-assign read_enable_1 = ~(op_bi | op_calli | load);
-assign read_idx_1 = instruction[20:16];
-
-assign write_enable = ~(bra | op_raise | store | op_wcsr);
-assign write_idx = call
- ? 5'd29
- : instruction[31] == 1'b0
- ? instruction[20:16]
- : instruction[15:11];
-
-
-assign size = instruction[27:26];
-
-assign sign_extend = instruction[28];
-
-assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
-
-assign logic_op = instruction[29:26];
-
-
-
-
-
-
-assign branch = bra | call;
-assign branch_reg = op_call | op_b;
-assign condition = instruction[28:26];
-
-
-
-
-assign scall = op_raise & instruction[2];
-assign eret = op_b & (instruction[25:21] == 5'd30);
-
-
-
-
-
-
-
-
-
-
-assign csr_write_enable = op_wcsr;
-
-
-
-assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
-assign select_high_immediate = op_andhi | op_orhi;
-assign select_call_immediate = instruction[31];
-
-assign high_immediate = {instruction[15:0], 16'h0000};
-assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
-assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
-assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
-
-assign immediate = select_high_immediate == 1'b1
- ? high_immediate
- : extended_immediate;
-
-assign branch_offset = select_call_immediate == 1'b1
- ? call_immediate
- : branch_immediate;
-
-endmodule
-
-
-
-
-
-
-
-
-
@@ -82967,8 +75264,26 @@ endmodule
-
+function integer clogb2;
+input [31:0] value;
+begin
+ for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+ value = value >> 1;
+end
+endfunction
+function integer clogb2_v1;
+input [31:0] value;
+reg [31:0] i;
+reg [31:0] temp;
+begin
+ temp = 0;
+ i = 0;
+ for (i = 0; temp < value; i = i + 1)
+ temp = 1<<i;
+ clogb2_v1 = i-1;
+end
+endfunction
@@ -82977,32 +75292,336 @@ endmodule
+assign op_add = instruction[30:26] == 5'b01101;
+assign op_and = instruction[30:26] == 5'b01000;
+assign op_andhi = instruction[31:26] == 6'b011000;
+assign op_b = instruction[31:26] == 6'b110000;
+assign op_bi = instruction[31:26] == 6'b111000;
+assign op_be = instruction[31:26] == 6'b010001;
+assign op_bg = instruction[31:26] == 6'b010010;
+assign op_bge = instruction[31:26] == 6'b010011;
+assign op_bgeu = instruction[31:26] == 6'b010100;
+assign op_bgu = instruction[31:26] == 6'b010101;
+assign op_bne = instruction[31:26] == 6'b010111;
+assign op_call = instruction[31:26] == 6'b110110;
+assign op_calli = instruction[31:26] == 6'b111110;
+assign op_cmpe = instruction[30:26] == 5'b11001;
+assign op_cmpg = instruction[30:26] == 5'b11010;
+assign op_cmpge = instruction[30:26] == 5'b11011;
+assign op_cmpgeu = instruction[30:26] == 5'b11100;
+assign op_cmpgu = instruction[30:26] == 5'b11101;
+assign op_cmpne = instruction[30:26] == 5'b11111;
+
+
+assign op_lb = instruction[31:26] == 6'b000100;
+assign op_lbu = instruction[31:26] == 6'b010000;
+assign op_lh = instruction[31:26] == 6'b000111;
+assign op_lhu = instruction[31:26] == 6'b001011;
+assign op_lw = instruction[31:26] == 6'b001010;
+
+
+
+
+assign op_nor = instruction[30:26] == 5'b00001;
+assign op_or = instruction[30:26] == 5'b01110;
+assign op_orhi = instruction[31:26] == 6'b011110;
+assign op_raise = instruction[31:26] == 6'b101011;
+assign op_rcsr = instruction[31:26] == 6'b100100;
+assign op_sb = instruction[31:26] == 6'b001100;
+
+
+
+assign op_sh = instruction[31:26] == 6'b000011;
+
+
+assign op_sr = instruction[30:26] == 5'b00101;
+assign op_sru = instruction[30:26] == 5'b00000;
+assign op_sub = instruction[31:26] == 6'b110010;
+assign op_sw = instruction[31:26] == 6'b010110;
+assign op_user = instruction[31:26] == 6'b110011;
+assign op_wcsr = instruction[31:26] == 6'b110100;
+assign op_xnor = instruction[30:26] == 5'b01001;
+assign op_xor = instruction[30:26] == 5'b00110;
+assign arith = op_add | op_sub;
+assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
+assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
+assign bi_conditional = op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne;
+assign bi_unconditional = op_bi;
+assign bra = op_b | bi_unconditional | bi_conditional;
+assign call = op_call | op_calli;
+
+
+
+assign shift = op_sr | op_sru;
+
+
+
+
+
+
+
+
+
+
+assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
+assign store = op_sb | op_sh | op_sw;
+always @(*)
+begin
+
+ if (call)
+ d_result_sel_0 = 1'b1;
+ else
+ d_result_sel_0 = 1'b0;
+ if (call)
+ d_result_sel_1 = 2'b00;
+ else if ((instruction[31] == 1'b0) && !bra)
+ d_result_sel_1 = 2'b10;
+ else
+ d_result_sel_1 = 2'b01;
+
+ x_result_sel_csr = 1'b0;
+
+
+
+ x_result_sel_shift = 1'b0;
+
+
+ x_result_sel_logic = 1'b0;
+
+
+ x_result_sel_add = 1'b0;
+ if (op_rcsr)
+ x_result_sel_csr = 1'b1;
+
+
+
+
+
+
+
+
+
+
-
+
+ else if (shift)
+ x_result_sel_shift = 1'b1;
+
+
+
+
+
+ else if (logical)
+ x_result_sel_logic = 1'b1;
+
+
+
+
+ else
+ x_result_sel_add = 1'b1;
+
+
+
+ m_result_sel_compare = cmp;
+
+
+
+
+
+ w_result_sel_load = load;
+
+
+
+end
+
+
+assign x_bypass_enable = arith
+ | logical
+
+
+
+
+
+
+
+
+
+
+
+
+ | shift
+
+
+
+
+
+
+
+ | op_rcsr
+ ;
+
+assign m_bypass_enable = x_bypass_enable
+
+
+
+ | cmp
+ ;
+
+assign read_enable_0 = ~(op_bi | op_calli);
+assign read_idx_0 = instruction[25:21];
+
+assign read_enable_1 = ~(op_bi | op_calli | load);
+assign read_idx_1 = instruction[20:16];
+
+assign write_enable = ~(bra | op_raise | store | op_wcsr);
+assign write_idx = call
+ ? 5'd29
+ : instruction[31] == 1'b0
+ ? instruction[20:16]
+ : instruction[15:11];
+
+
+assign size = instruction[27:26];
+
+assign sign_extend = instruction[28];
+
+assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
+
+assign logic_op = instruction[29:26];
+
+
+
+
+assign branch = bra | call;
+assign branch_reg = op_call | op_b;
+assign condition = instruction[28:26];
+
+
+assign scall = op_raise & instruction[2];
+assign eret = op_b & (instruction[25:21] == 5'd30);
+
+
+
+
+
+
+
+
+assign csr_write_enable = op_wcsr;
+
+
+
+assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
+assign select_high_immediate = op_andhi | op_orhi;
+assign select_call_immediate = instruction[31];
+
+assign high_immediate = {instruction[15:0], 16'h0000};
+assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
+assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
+assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
+
+assign immediate = select_high_immediate == 1'b1
+ ? high_immediate
+ : extended_immediate;
+
+assign branch_offset = select_call_immediate == 1'b1
+ ? call_immediate
+ : branch_immediate;
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -83286,9 +75905,7 @@ endmodule
-
-
-
+
@@ -83740,11 +76357,8 @@ endmodule
-
-
-
-
+
@@ -83775,9 +76389,8 @@ endmodule
-
-
+
@@ -84061,9 +76674,7 @@ endmodule
-
-
-
+
@@ -84568,10 +77179,7 @@ endmodule
-
-
-
-
+
@@ -84602,9 +77210,8 @@ endmodule
-
-
+
@@ -84888,9 +77495,7 @@ endmodule
-
-
-
+
@@ -85251,10 +77856,7 @@ endmodule
-
-
-
-
+
@@ -85285,9 +77887,8 @@ endmodule
-
-
+
@@ -85572,8 +78173,6 @@ endmodule
-
-
@@ -85592,47 +78191,40 @@ module lm32_instruction_unit_minimal (
kill_f,
branch_predict_taken_d,
branch_predict_address_d,
-
+
-
exception_m,
branch_taken_m,
branch_mispredict_taken_m,
branch_target_m,
-
+
-
-
+
-
-
+
-
-
-
+
i_dat_i,
i_ack_i,
i_err_i,
i_rty_i,
-
-
+
-
pc_f,
@@ -85640,19 +78232,16 @@ module lm32_instruction_unit_minimal (
pc_x,
pc_m,
pc_w,
-
+
-
-
+
-
-
-
+
i_dat_o,
i_adr_o,
@@ -85663,21 +78252,16 @@ module lm32_instruction_unit_minimal (
i_cti_o,
i_lock_o,
i_bte_o,
-
-
+
-
-
+
-
-
-
- instruction_f,
+ instruction_f,
instruction_d
);
@@ -85714,46 +78298,40 @@ input valid_d;
input kill_f;
input branch_predict_taken_d;
-input [ ((32-2)+2-1):2] branch_predict_address_d;
+input [((32-2)+2-1):2] branch_predict_address_d;
-
+
-
input exception_m;
input branch_taken_m;
input branch_mispredict_taken_m;
-input [ ((32-2)+2-1):2] branch_target_m;
+input [((32-2)+2-1):2] branch_target_m;
-
+
-
-
+
-
-
+
-
-
-
-input [ (32-1):0] i_dat_i;
+
+input [(32-1):0] i_dat_i;
input i_ack_i;
input i_err_i;
input i_rty_i;
-
-
+
@@ -85763,20 +78341,19 @@ input i_rty_i;
-
-output [ ((32-2)+2-1):2] pc_f;
-reg [ ((32-2)+2-1):2] pc_f;
-output [ ((32-2)+2-1):2] pc_d;
-reg [ ((32-2)+2-1):2] pc_d;
-output [ ((32-2)+2-1):2] pc_x;
-reg [ ((32-2)+2-1):2] pc_x;
-output [ ((32-2)+2-1):2] pc_m;
-reg [ ((32-2)+2-1):2] pc_m;
-output [ ((32-2)+2-1):2] pc_w;
-reg [ ((32-2)+2-1):2] pc_w;
+output [((32-2)+2-1):2] pc_f;
+reg [((32-2)+2-1):2] pc_f;
+output [((32-2)+2-1):2] pc_d;
+reg [((32-2)+2-1):2] pc_d;
+output [((32-2)+2-1):2] pc_x;
+reg [((32-2)+2-1):2] pc_x;
+output [((32-2)+2-1):2] pc_m;
+reg [((32-2)+2-1):2] pc_m;
+output [((32-2)+2-1):2] pc_w;
+reg [((32-2)+2-1):2] pc_w;
-
+
@@ -85787,88 +78364,73 @@ reg [ ((32-2)+2-1):2] pc_w;
-
-
+
-
-
-
-output [ (32-1):0] i_dat_o;
-
+
+output [(32-1):0] i_dat_o;
+
+wire [(32-1):0] i_dat_o;
-wire [ (32-1):0] i_dat_o;
-
-
-output [ (32-1):0] i_adr_o;
-reg [ (32-1):0] i_adr_o;
+output [(32-1):0] i_adr_o;
+reg [(32-1):0] i_adr_o;
output i_cyc_o;
reg i_cyc_o;
-output [ (4-1):0] i_sel_o;
-
+output [(4-1):0] i_sel_o;
+
-
-wire [ (4-1):0] i_sel_o;
-
+wire [(4-1):0] i_sel_o;
output i_stb_o;
reg i_stb_o;
output i_we_o;
-
+
-
wire i_we_o;
-
-output [ (3-1):0] i_cti_o;
-reg [ (3-1):0] i_cti_o;
+output [(3-1):0] i_cti_o;
+reg [(3-1):0] i_cti_o;
output i_lock_o;
reg i_lock_o;
-output [ (2-1):0] i_bte_o;
-wire [ (2-1):0] i_bte_o;
-
+output [(2-1):0] i_bte_o;
+wire [(2-1):0] i_bte_o;
-
+
-
-
+
-
-
-
-output [ (32-1):0] instruction_f;
-wire [ (32-1):0] instruction_f;
+output [(32-1):0] instruction_f;
+wire [(32-1):0] instruction_f;
-output [ (32-1):0] instruction_d;
-reg [ (32-1):0] instruction_d;
+output [(32-1):0] instruction_d;
+reg [(32-1):0] instruction_d;
-reg [ ((32-2)+2-1):2] pc_a;
+reg [((32-2)+2-1):2] pc_a;
-
+
-
-
+
@@ -85879,32 +78441,24 @@ reg [ ((32-2)+2-1):2] pc_a;
-
-
-
-reg [ (32-1):0] wb_data_f;
+reg [(32-1):0] wb_data_f;
-
-
+
-
-
-
-
+
-
+
-
-
+
@@ -85912,10 +78466,7 @@ reg [ (32-1):0] wb_data_f;
-
-
-
-
+
@@ -85971,8 +78522,7 @@ endfunction
-
-
+
@@ -86018,10 +78568,9 @@ endfunction
-
-
+
@@ -86057,8 +78606,7 @@ endfunction
-
-
+
@@ -86070,86 +78618,73 @@ endfunction
-
always @(*)
begin
-
+
-
- if (branch_taken_m == 1'b1)
- if ((branch_mispredict_taken_m == 1'b1) && (exception_m == 1'b0))
+ if (branch_taken_m == 1'b1)
+ if ((branch_mispredict_taken_m == 1'b1) && (exception_m == 1'b0))
pc_a = pc_x;
else
pc_a = branch_target_m;
-
+
-
else
- if ( (valid_d == 1'b1) && (branch_predict_taken_d == 1'b1) )
+ if ( (valid_d == 1'b1) && (branch_predict_taken_d == 1'b1) )
pc_a = branch_predict_address_d;
else
-
+
-
pc_a = pc_f + 1'b1;
end
-
+
-
-
+
-
-
+
-
assign instruction_f = wb_data_f;
-
-
-
-
-
-
+
+
assign i_dat_o = 32'd0;
-assign i_we_o = 1'b0;
+assign i_we_o = 1'b0;
assign i_sel_o = 4'b1111;
-
-assign i_bte_o = 2'b00;
-
+assign i_bte_o = 2'b00;
-
+
@@ -86175,7 +78710,6 @@ assign i_bte_o = 2'b00;
-
@@ -86184,31 +78718,31 @@ assign i_bte_o = 2'b00;
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- pc_f <= ( 32'h00000000-4)/4;
- pc_d <= { (32-2){1'b0}};
- pc_x <= { (32-2){1'b0}};
- pc_m <= { (32-2){1'b0}};
- pc_w <= { (32-2){1'b0}};
+ pc_f <= (32'h00000000-4)/4;
+ pc_d <= {(32-2){1'b0}};
+ pc_x <= {(32-2){1'b0}};
+ pc_m <= {(32-2){1'b0}};
+ pc_w <= {(32-2){1'b0}};
end
else
begin
- if (stall_f == 1'b0)
+ if (stall_f == 1'b0)
pc_f <= pc_a;
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
pc_d <= pc_f;
- if (stall_x == 1'b0)
+ if (stall_x == 1'b0)
pc_x <= pc_d;
- if (stall_m == 1'b0)
+ if (stall_m == 1'b0)
pc_m <= pc_x;
pc_w <= pc_m;
end
end
-
+
@@ -86238,8 +78772,7 @@ end
-
-
+
@@ -86252,8 +78785,7 @@ end
-
-
+
@@ -86266,11 +78798,9 @@ end
+
-
-
-
-
+
@@ -86386,111 +78916,99 @@ end
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
- i_adr_o <= { 32{1'b0}};
- i_cti_o <= 3'b111;
- i_lock_o <= 1'b0;
- wb_data_f <= { 32{1'b0}};
-
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
+ i_adr_o <= {32{1'b0}};
+ i_cti_o <= 3'b111;
+ i_lock_o <= 1'b0;
+ wb_data_f <= {32{1'b0}};
+
-
end
else
begin
- if (i_cyc_o == 1'b1)
+ if (i_cyc_o == 1'b1)
begin
- if((i_ack_i == 1'b1) || (i_err_i == 1'b1))
+ if((i_ack_i == 1'b1) || (i_err_i == 1'b1))
begin
- i_cyc_o <= 1'b0;
- i_stb_o <= 1'b0;
+ i_cyc_o <= 1'b0;
+ i_stb_o <= 1'b0;
wb_data_f <= i_dat_i;
end
-
+
-
end
else
begin
- if ( (stall_a == 1'b0)
-
+ if ( (stall_a == 1'b0)
+
-
)
begin
-
+
-
i_adr_o <= {pc_a, 2'b00};
- i_cyc_o <= 1'b1;
- i_stb_o <= 1'b1;
-
+ i_cyc_o <= 1'b1;
+ i_stb_o <= 1'b1;
+
-
end
else
begin
- if ( (stall_a == 1'b0)
-
+ if ( (stall_a == 1'b0)
+
-
)
begin
-
+
-
end
end
end
end
end
-
-
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- instruction_d <= { 32{1'b0}};
-
+ instruction_d <= {32{1'b0}};
+
-
end
else
begin
- if (stall_d == 1'b0)
+ if (stall_d == 1'b0)
begin
instruction_d <= instruction_f;
-
+
-
end
end
end
@@ -86524,10 +79042,7 @@ endmodule
-
-
-
-
+
@@ -86557,9 +79072,9 @@ endmodule
-
+
@@ -86843,9 +79358,7 @@ endmodule
-
-
-
+
@@ -87312,11 +79825,7 @@ endmodule
-
-
-
-
-
+
@@ -87346,9 +79855,9 @@ endmodule
-
+
@@ -87633,8 +80142,6 @@ endmodule
-
-
@@ -87646,19 +80153,16 @@ module lm32_interrupt_minimal (
interrupt,
stall_x,
-
+
-
exception,
-
eret_q_x,
-
+
-
csr,
csr_write_data,
csr_write_enable,
@@ -87672,7 +80176,7 @@ module lm32_interrupt_minimal (
-parameter interrupts = 32;
+parameter interrupts = 32;
@@ -87685,22 +80189,19 @@ input [interrupts-1:0] interrupt;
input stall_x;
-
+
-
input exception;
-
input eret_q_x;
-
+
-
-input [ (3-1):0] csr;
-input [ (32-1):0] csr_write_data;
+input [(3-1):0] csr;
+input [(32-1):0] csr_write_data;
input csr_write_enable;
@@ -87710,8 +80211,8 @@ input csr_write_enable;
output interrupt_exception;
wire interrupt_exception;
-output [ (32-1):0] csr_read_data;
-reg [ (32-1):0] csr_read_data;
+output [(32-1):0] csr_read_data;
+reg [(32-1):0] csr_read_data;
@@ -87725,10 +80226,9 @@ wire [interrupts-1:0] interrupt_n_exception;
reg ie;
reg eie;
-
+
-
reg [interrupts-1:0] ip;
reg [interrupts-1:0] im;
@@ -87745,13 +80245,11 @@ assign interrupt_exception = (|interrupt_n_exception) & ie;
assign asserted = ip | interrupt;
-assign ie_csr_read_data = {{ 32-3{1'b0}},
-
+assign ie_csr_read_data = {{32-3{1'b0}},
+
-
1'b0,
-
eie,
ie
@@ -87765,20 +80263,18 @@ generate
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
-
+ 3'h0: csr_read_data = {{32-3{1'b0}},
+
-
1'b0,
-
eie,
ie
};
- 3'h2: csr_read_data = ip;
- 3'h1: csr_read_data = im;
- default: csr_read_data = { 32{1'bx}};
+ 3'h2: csr_read_data = ip;
+ 3'h1: csr_read_data = im;
+ default: csr_read_data = {32{1'bx}};
endcase
end
end
@@ -87788,19 +80284,17 @@ end
always @(*)
begin
case (csr)
- 3'h0: csr_read_data = {{ 32-3{1'b0}},
-
+ 3'h0: csr_read_data = {{32-3{1'b0}},
+
-
1'b0,
-
eie,
ie
};
- 3'h2: csr_read_data = ip;
- default: csr_read_data = { 32{1'bx}};
+ 3'h2: csr_read_data = ip;
+ default: csr_read_data = {32{1'bx}};
endcase
end
end
@@ -87810,9 +80304,8 @@ endgenerate
-
-
- reg [ 10:0] eie_delay = 0;
+
+ reg [10:0] eie_delay = 0;
generate
@@ -87821,16 +80314,15 @@ generate
if (interrupts > 1)
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- ie <= 1'b0;
- eie <= 1'b0;
-
+ ie <= 1'b0;
+ eie <= 1'b0;
+
-
im <= {interrupts{1'b0}};
ip <= {interrupts{1'b0}};
eie_delay <= 0;
@@ -87840,7 +80332,7 @@ always @(posedge clk_i )
begin
ip <= asserted;
-
+
@@ -87854,52 +80346,48 @@ always @(posedge clk_i )
-
- if (exception == 1'b1)
+ if (exception == 1'b1)
begin
eie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
-
- else if (stall_x == 1'b0)
+ else if (stall_x == 1'b0)
begin
if(eie_delay[0])
ie <= eie;
- eie_delay <= {1'b0, eie_delay[ 10:1]};
+ eie_delay <= {1'b0, eie_delay[10:1]};
- if (eret_q_x == 1'b1) begin
+ if (eret_q_x == 1'b1) begin
- eie_delay[ 10] <= 1'b1;
- eie_delay[ 10-1:0] <= 0;
+ eie_delay[10] <= 1'b1;
+ eie_delay[10-1:0] <= 0;
end
-
+
-
- else if (csr_write_enable == 1'b1)
+ else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 3'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
+
-
end
- if (csr == 3'h1)
+ if (csr == 3'h1)
im <= csr_write_data[interrupts-1:0];
- if (csr == 3'h2)
+ if (csr == 3'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end
@@ -87909,16 +80397,15 @@ end
else
begin
-always @(posedge clk_i )
+always @(posedge clk_i )
begin
- if (rst_i == 1'b1)
+ if (rst_i == 1'b1)
begin
- ie <= 1'b0;
- eie <= 1'b0;
-
+ ie <= 1'b0;
+ eie <= 1'b0;
+
-
ip <= {interrupts{1'b0}};
eie_delay <= 0;
end
@@ -87926,7 +80413,7 @@ always @(posedge clk_i )
begin
ip <= asserted;
-
+
@@ -87940,48 +80427,44 @@ always @(posedge clk_i )
-
- if (exception == 1'b1)
+ if (exception == 1'b1)
begin
eie <= ie;
- ie <= 1'b0;
+ ie <= 1'b0;
end
-
- else if (stall_x == 1'b0)
+ else if (stall_x == 1'b0)
begin
if(eie_delay[0])
ie <= eie;
- eie_delay <= {1'b0, eie_delay[ 10:1]};
+ eie_delay <= {1'b0, eie_delay[10:1]};
- if (eret_q_x == 1'b1) begin
+ if (eret_q_x == 1'b1) begin
- eie_delay[ 10] <= 1'b1;
- eie_delay[ 10-1:0] <= 0;
+ eie_delay[10] <= 1'b1;
+ eie_delay[10-1:0] <= 0;
end
-
+
-
- else if (csr_write_enable == 1'b1)
+ else if (csr_write_enable == 1'b1)
begin
- if (csr == 3'h0)
+ if (csr == 3'h0)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
-
+
-
end
- if (csr == 3'h2)
+ if (csr == 3'h2)
ip <= asserted & ~csr_write_data[interrupts-1:0];
end
end