From fa8df2bb3a49821d087d9ae3c8ea454eaa48ef0e Mon Sep 17 00:00:00 2001
From: Dimitris Lampridis <dimitris.lampridis@cern.ch>
Date: Mon, 9 Sep 2019 11:19:40 +0200
Subject: [PATCH] Clean-up non-ASCII characters and fix line feeds and
terminations in all affected files
---
doc/general-cores.in | 2 +-
modules/axi/axi4_pkg.vhd | 496 +++++++++---------
modules/common/gc_arbitrated_mux.vhd | 6 +-
.../common/gc_async_signals_input_stage.vhd | 4 +-
modules/common/gc_bicolor_led_ctrl.vhd | 4 +-
modules/common/gc_extend_pulse.vhd | 4 +-
modules/common/gc_reset.vhd | 4 +-
modules/common/gc_serial_dac.vhd | 6 +-
.../genrams/xilinx/generic_simple_dpram.vhd | 4 +-
.../wb_axi4lite_bridge/wb_axi4lite_bridge.vhd | 250 ++++-----
.../xwb_axi4lite_bridge.vhd | 382 +++++++-------
modules/wishbone/wb_irq/msidemo/crt0.S | 480 ++++++++---------
.../wb_lm32/platform/kintex7/jtag_tap.v | 90 ++--
.../platform/kintex7/lm32_multiplier.v | 240 ++++-----
.../wishbone/wb_simple_pwm/simple_pwm_wb.wb | 2 +-
modules/wishbone/wb_simple_timer/Manifest.py | 2 +-
modules/wishbone/wb_uart/uart_async_rx.vhd | 458 ++++++++--------
modules/wishbone/wbgen2/wbgen2_dpssram.vhd | 4 +-
modules/wishbone/wbgen2/wbgen2_eic.vhd | 4 +-
modules/wishbone/wbgen2/wbgen2_fifo_async.vhd | 4 +-
modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd | 4 +-
.../wb_xilinx_fpga_loader.vhd | 2 +-
.../wb_xilinx_fpga_loader/xloader_wb.wb | 2 +-
.../xwb_xilinx_fpga_loader.vhd | 2 +-
.../lm32_testsys/sw/target/lm32/crt0.S | 480 ++++++++---------
25 files changed, 1468 insertions(+), 1468 deletions(-)
diff --git a/doc/general-cores.in b/doc/general-cores.in
index 004e9865..fb3bc57a 100644
--- a/doc/general-cores.in
+++ b/doc/general-cores.in
@@ -42,7 +42,7 @@
@titlepage
@title @code{general-cores} VHDL library
@subtitle Programmer's manual
-@author CERN BE-CO-HT / Tomasz WÅ‚ostowski
+@author CERN BE-CO-HT / Tomasz Wlostowski
@end titlepage
@headings single
diff --git a/modules/axi/axi4_pkg.vhd b/modules/axi/axi4_pkg.vhd
index 8ec63f3d..0c217d85 100644
--- a/modules/axi/axi4_pkg.vhd
+++ b/modules/axi/axi4_pkg.vhd
@@ -1,248 +1,248 @@
--------------------------------------------------------------------------------
--- Title : AXI4Lite-to-WB bridge package
--- Project : General Cores
--------------------------------------------------------------------------------
--- File : axi4_pkg.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN
--- Platform : FPGA-generics
--- Standard : VHDL '93
--------------------------------------------------------------------------------
--- Copyright (c) 2017 CERN
---
--- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
--- to treat this file as licensed under the Apache License 2.0); you may not
--- use this file except in compliance with the License. You may obtain a copy
--- of the License at http://solderpad.org/licenses/SHL-0.51.
--- Unless required by applicable law or agreed to in writing, software,
--- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
--- or implied. See the License for the specific language governing permissions
--- and limitations under the License.
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-use work.wishbone_pkg.all;
-
-package axi4_pkg is
-
- -- AXI4-Full interface, master output ports, 32 bits
- type t_axi4_full_master_out_32 is record
- ARVALID : std_logic;
- AWVALID : std_logic;
- BREADY : std_logic;
- RREADY : std_logic;
- WLAST : std_logic;
- WVALID : std_logic;
- ARID : std_logic_vector (11 downto 0);
- AWID : std_logic_vector (11 downto 0);
- WID : std_logic_vector (11 downto 0);
- ARBURST : std_logic_vector (1 downto 0);
- ARLOCK : std_logic_vector (1 downto 0);
- ARSIZE : std_logic_vector (2 downto 0);
- AWBURST : std_logic_vector (1 downto 0);
- AWLOCK : std_logic_vector (1 downto 0);
- AWSIZE : std_logic_vector (2 downto 0);
- ARPROT : std_logic_vector (2 downto 0);
- AWPROT : std_logic_vector (2 downto 0);
- ARADDR : std_logic_vector (31 downto 0);
- AWADDR : std_logic_vector (31 downto 0);
- WDATA : std_logic_vector (31 downto 0);
- ARCACHE : std_logic_vector (3 downto 0);
- ARLEN : std_logic_vector (3 downto 0);
- ARQOS : std_logic_vector (3 downto 0);
- AWCACHE : std_logic_vector (3 downto 0);
- AWLEN : std_logic_vector (3 downto 0);
- AWQOS : std_logic_vector (3 downto 0);
- WSTRB : std_logic_vector (3 downto 0);
- end record;
-
- -- AXI4-Full interface, master input ports, 32 bits
- type t_axi4_full_master_in_32 is record
- ARREADY : std_logic;
- AWREADY : std_logic;
- BVALID : std_logic;
- RLAST : std_logic;
- RVALID : std_logic;
- WREADY : std_logic;
- BID : std_logic_vector (11 downto 0);
- RID : std_logic_vector (11 downto 0);
- BRESP : std_logic_vector (1 downto 0);
- RRESP : std_logic_vector (1 downto 0);
- RDATA : std_logic_vector (31 downto 0);
- end record;
-
- -- AXI4-Lite interface, master output ports, 32 bits
- type t_axi4_lite_master_out_32 is record
- ARVALID : std_logic;
- AWVALID : std_logic;
- BREADY : std_logic;
- RREADY : std_logic;
- WLAST : std_logic;
- WVALID : std_logic;
- ARADDR : std_logic_vector (31 downto 0);
- AWADDR : std_logic_vector (31 downto 0);
- WDATA : std_logic_vector (31 downto 0);
- WSTRB : std_logic_vector (3 downto 0);
- end record;
-
- -- AXI4-Lite interface, master input ports, 32 bits
- type t_axi4_lite_master_in_32 is record
- ARREADY : std_logic;
- AWREADY : std_logic;
- BVALID : std_logic;
- RLAST : std_logic;
- RVALID : std_logic;
- WREADY : std_logic;
- BRESP : std_logic_vector (1 downto 0);
- RRESP : std_logic_vector (1 downto 0);
- RDATA : std_logic_vector (31 downto 0);
- end record;
-
- constant c_axi4_lite_default_master_in_32 : t_axi4_lite_master_in_32 :=
- (
- AWREADY => '0',
- ARREADY => '0',
- BVALID => '0',
- RLAST => '0',
- RVALID => '0',
- WREADY => '0',
- BRESP => "00",
- RRESP => "00",
- RDATA => (others => '0')
- );
-
-
- constant c_axi4_lite_default_master_out_32 : t_axi4_lite_master_out_32 :=
- (
- ARVALID => '0',
- AWVALID => '0',
- BREADY => '0',
- RREADY => '0',
- WLAST => '0',
- WVALID => '0',
- ARADDR => (others => '0'),
- AWADDR => (others => '0'),
- WDATA => (others => '0'),
- WSTRB => (others => '0')
- );
-
-
-
- subtype t_axi4_lite_slave_in_32 is t_axi4_lite_master_out_32;
- subtype t_axi4_lite_slave_out_32 is t_axi4_lite_master_in_32;
-
- constant c_AXI4_RESP_OKAY : std_logic_vector(1 downto 0) := "00";
- constant c_AXI4_RESP_EXOKAY : std_logic_vector(1 downto 0) := "01";
- constant c_AXI4_RESP_SLVERR : std_logic_vector(1 downto 0) := "10";
- constant c_AXI4_RESP_DECERR : std_logic_vector(1 downto 0) := "11";
-
- function f_axi4_full_to_lite (
- f : t_axi4_full_master_out_32
- ) return t_axi4_lite_master_out_32;
-
- function f_axi4_lite_to_full (
- l : t_axi4_lite_master_in_32
- ) return t_axi4_full_master_in_32;
-
- component xwb_axi4lite_bridge is
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
- axi4_slave_i : in t_axi4_lite_slave_in_32;
- axi4_slave_o : out t_axi4_lite_slave_out_32;
- wb_master_o : out t_wishbone_master_out;
- wb_master_i : in t_wishbone_master_in);
- end component xwb_axi4lite_bridge;
-
- component wb_axi4lite_bridge is
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
-
- ARVALID : in std_logic;
- AWVALID : in std_logic;
- BREADY : in std_logic;
- RREADY : in std_logic;
- WLAST : in std_logic;
- WVALID : in std_logic;
- ARADDR : in std_logic_vector (31 downto 0);
- AWADDR : in std_logic_vector (31 downto 0);
- WDATA : in std_logic_vector (31 downto 0);
- WSTRB : in std_logic_vector (3 downto 0);
- ARREADY : out std_logic;
- AWREADY : out std_logic;
- BVALID : out std_logic;
- RLAST : out std_logic;
- RVALID : out std_logic;
- WREADY : out std_logic;
- BRESP : out std_logic_vector (1 downto 0);
- RRESP : out std_logic_vector (1 downto 0);
- RDATA : out std_logic_vector (31 downto 0);
-
- wb_adr : out std_logic_vector(c_wishbone_address_width-1 downto 0);
- wb_dat_m2s : out std_logic_vector(c_wishbone_data_width-1 downto 0);
- wb_sel : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
- wb_cyc : out std_logic;
- wb_stb : out std_logic;
- wb_we : out std_logic;
-
- wb_dat_s2m : in std_logic_vector(c_wishbone_data_width-1 downto 0);
- wb_err : in std_logic := '0';
- wb_rty : in std_logic := '0';
- wb_ack : in std_logic;
- wb_stall : in std_logic
- );
- end component;
-
-end package;
-
-package body axi4_pkg is
-
- function f_axi4_full_to_lite (
- f : t_axi4_full_master_out_32
- ) return t_axi4_lite_master_out_32 is
- variable l : t_axi4_lite_master_out_32;
- begin
-
- l.ARVALID := f.ARVALID;
- l.AWVALID := f.AWVALID;
- l.BREADY := f.BREADY;
- l.RREADY := f.RREADY;
- l.WLAST := f.WLAST;
- l.WVALID := f.WVALID;
- l.ARADDR := f.ARADDR;
- l.AWADDR := f.AWADDR;
- l.WDATA := f.WDATA;
- l.WSTRB := f.WSTRB;
-
- return l;
-
- end f_axi4_full_to_lite;
-
- function f_axi4_lite_to_full (
- l : t_axi4_lite_master_in_32
- ) return t_axi4_full_master_in_32 is
- variable f : t_axi4_full_master_in_32;
- begin
- f.ARREADY := l.ARREADY;
- f.AWREADY := l.AWREADY;
- f.BVALID := l.BVALID;
- f.RLAST := l.RLAST;
- f.RVALID := l.RVALID;
- f.WREADY := l.WREADY;
- f.BID := (others => '0');
- f.RID := (others => '0');
- f.BRESP := l.BRESP;
- f.RRESP := l.RRESP;
- f.RDATA := l.RDATA;
-
- return f;
-
- end f_axi4_lite_to_full;
-
-
-end package body;
+-------------------------------------------------------------------------------
+-- Title : AXI4Lite-to-WB bridge package
+-- Project : General Cores
+-------------------------------------------------------------------------------
+-- File : axi4_pkg.vhd
+-- Author : Tomasz Wlostowski
+-- Company : CERN
+-- Platform : FPGA-generics
+-- Standard : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 0.51 (the "License") (which enables you, at your option,
+-- to treat this file as licensed under the Apache License 2.0); you may not
+-- use this file except in compliance with the License. You may obtain a copy
+-- of the License at http://solderpad.org/licenses/SHL-0.51.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wishbone_pkg.all;
+
+package axi4_pkg is
+
+ -- AXI4-Full interface, master output ports, 32 bits
+ type t_axi4_full_master_out_32 is record
+ ARVALID : std_logic;
+ AWVALID : std_logic;
+ BREADY : std_logic;
+ RREADY : std_logic;
+ WLAST : std_logic;
+ WVALID : std_logic;
+ ARID : std_logic_vector (11 downto 0);
+ AWID : std_logic_vector (11 downto 0);
+ WID : std_logic_vector (11 downto 0);
+ ARBURST : std_logic_vector (1 downto 0);
+ ARLOCK : std_logic_vector (1 downto 0);
+ ARSIZE : std_logic_vector (2 downto 0);
+ AWBURST : std_logic_vector (1 downto 0);
+ AWLOCK : std_logic_vector (1 downto 0);
+ AWSIZE : std_logic_vector (2 downto 0);
+ ARPROT : std_logic_vector (2 downto 0);
+ AWPROT : std_logic_vector (2 downto 0);
+ ARADDR : std_logic_vector (31 downto 0);
+ AWADDR : std_logic_vector (31 downto 0);
+ WDATA : std_logic_vector (31 downto 0);
+ ARCACHE : std_logic_vector (3 downto 0);
+ ARLEN : std_logic_vector (3 downto 0);
+ ARQOS : std_logic_vector (3 downto 0);
+ AWCACHE : std_logic_vector (3 downto 0);
+ AWLEN : std_logic_vector (3 downto 0);
+ AWQOS : std_logic_vector (3 downto 0);
+ WSTRB : std_logic_vector (3 downto 0);
+ end record;
+
+ -- AXI4-Full interface, master input ports, 32 bits
+ type t_axi4_full_master_in_32 is record
+ ARREADY : std_logic;
+ AWREADY : std_logic;
+ BVALID : std_logic;
+ RLAST : std_logic;
+ RVALID : std_logic;
+ WREADY : std_logic;
+ BID : std_logic_vector (11 downto 0);
+ RID : std_logic_vector (11 downto 0);
+ BRESP : std_logic_vector (1 downto 0);
+ RRESP : std_logic_vector (1 downto 0);
+ RDATA : std_logic_vector (31 downto 0);
+ end record;
+
+ -- AXI4-Lite interface, master output ports, 32 bits
+ type t_axi4_lite_master_out_32 is record
+ ARVALID : std_logic;
+ AWVALID : std_logic;
+ BREADY : std_logic;
+ RREADY : std_logic;
+ WLAST : std_logic;
+ WVALID : std_logic;
+ ARADDR : std_logic_vector (31 downto 0);
+ AWADDR : std_logic_vector (31 downto 0);
+ WDATA : std_logic_vector (31 downto 0);
+ WSTRB : std_logic_vector (3 downto 0);
+ end record;
+
+ -- AXI4-Lite interface, master input ports, 32 bits
+ type t_axi4_lite_master_in_32 is record
+ ARREADY : std_logic;
+ AWREADY : std_logic;
+ BVALID : std_logic;
+ RLAST : std_logic;
+ RVALID : std_logic;
+ WREADY : std_logic;
+ BRESP : std_logic_vector (1 downto 0);
+ RRESP : std_logic_vector (1 downto 0);
+ RDATA : std_logic_vector (31 downto 0);
+ end record;
+
+ constant c_axi4_lite_default_master_in_32 : t_axi4_lite_master_in_32 :=
+ (
+ AWREADY => '0',
+ ARREADY => '0',
+ BVALID => '0',
+ RLAST => '0',
+ RVALID => '0',
+ WREADY => '0',
+ BRESP => "00",
+ RRESP => "00",
+ RDATA => (others => '0')
+ );
+
+
+ constant c_axi4_lite_default_master_out_32 : t_axi4_lite_master_out_32 :=
+ (
+ ARVALID => '0',
+ AWVALID => '0',
+ BREADY => '0',
+ RREADY => '0',
+ WLAST => '0',
+ WVALID => '0',
+ ARADDR => (others => '0'),
+ AWADDR => (others => '0'),
+ WDATA => (others => '0'),
+ WSTRB => (others => '0')
+ );
+
+
+
+ subtype t_axi4_lite_slave_in_32 is t_axi4_lite_master_out_32;
+ subtype t_axi4_lite_slave_out_32 is t_axi4_lite_master_in_32;
+
+ constant c_AXI4_RESP_OKAY : std_logic_vector(1 downto 0) := "00";
+ constant c_AXI4_RESP_EXOKAY : std_logic_vector(1 downto 0) := "01";
+ constant c_AXI4_RESP_SLVERR : std_logic_vector(1 downto 0) := "10";
+ constant c_AXI4_RESP_DECERR : std_logic_vector(1 downto 0) := "11";
+
+ function f_axi4_full_to_lite (
+ f : t_axi4_full_master_out_32
+ ) return t_axi4_lite_master_out_32;
+
+ function f_axi4_lite_to_full (
+ l : t_axi4_lite_master_in_32
+ ) return t_axi4_full_master_in_32;
+
+ component xwb_axi4lite_bridge is
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ axi4_slave_i : in t_axi4_lite_slave_in_32;
+ axi4_slave_o : out t_axi4_lite_slave_out_32;
+ wb_master_o : out t_wishbone_master_out;
+ wb_master_i : in t_wishbone_master_in);
+ end component xwb_axi4lite_bridge;
+
+ component wb_axi4lite_bridge is
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ ARVALID : in std_logic;
+ AWVALID : in std_logic;
+ BREADY : in std_logic;
+ RREADY : in std_logic;
+ WLAST : in std_logic;
+ WVALID : in std_logic;
+ ARADDR : in std_logic_vector (31 downto 0);
+ AWADDR : in std_logic_vector (31 downto 0);
+ WDATA : in std_logic_vector (31 downto 0);
+ WSTRB : in std_logic_vector (3 downto 0);
+ ARREADY : out std_logic;
+ AWREADY : out std_logic;
+ BVALID : out std_logic;
+ RLAST : out std_logic;
+ RVALID : out std_logic;
+ WREADY : out std_logic;
+ BRESP : out std_logic_vector (1 downto 0);
+ RRESP : out std_logic_vector (1 downto 0);
+ RDATA : out std_logic_vector (31 downto 0);
+
+ wb_adr : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+ wb_dat_m2s : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_sel : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+ wb_cyc : out std_logic;
+ wb_stb : out std_logic;
+ wb_we : out std_logic;
+
+ wb_dat_s2m : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_err : in std_logic := '0';
+ wb_rty : in std_logic := '0';
+ wb_ack : in std_logic;
+ wb_stall : in std_logic
+ );
+ end component;
+
+end package;
+
+package body axi4_pkg is
+
+ function f_axi4_full_to_lite (
+ f : t_axi4_full_master_out_32
+ ) return t_axi4_lite_master_out_32 is
+ variable l : t_axi4_lite_master_out_32;
+ begin
+
+ l.ARVALID := f.ARVALID;
+ l.AWVALID := f.AWVALID;
+ l.BREADY := f.BREADY;
+ l.RREADY := f.RREADY;
+ l.WLAST := f.WLAST;
+ l.WVALID := f.WVALID;
+ l.ARADDR := f.ARADDR;
+ l.AWADDR := f.AWADDR;
+ l.WDATA := f.WDATA;
+ l.WSTRB := f.WSTRB;
+
+ return l;
+
+ end f_axi4_full_to_lite;
+
+ function f_axi4_lite_to_full (
+ l : t_axi4_lite_master_in_32
+ ) return t_axi4_full_master_in_32 is
+ variable f : t_axi4_full_master_in_32;
+ begin
+ f.ARREADY := l.ARREADY;
+ f.AWREADY := l.AWREADY;
+ f.BVALID := l.BVALID;
+ f.RLAST := l.RLAST;
+ f.RVALID := l.RVALID;
+ f.WREADY := l.WREADY;
+ f.BID := (others => '0');
+ f.RID := (others => '0');
+ f.BRESP := l.BRESP;
+ f.RRESP := l.RRESP;
+ f.RDATA := l.RDATA;
+
+ return f;
+
+ end f_axi4_lite_to_full;
+
+
+end package body;
diff --git a/modules/common/gc_arbitrated_mux.vhd b/modules/common/gc_arbitrated_mux.vhd
index bce71ee5..3e43a245 100644
--- a/modules/common/gc_arbitrated_mux.vhd
+++ b/modules/common/gc_arbitrated_mux.vhd
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
--- Last update: 2012-02-21
+-- Last update: 2019-09-09
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
@@ -17,13 +17,13 @@
-- Copyright (c) 2011 CERN / BE-CO-HT
--
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
+-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--
diff --git a/modules/common/gc_async_signals_input_stage.vhd b/modules/common/gc_async_signals_input_stage.vhd
index 03d97d4d..e95908b3 100644
--- a/modules/common/gc_async_signals_input_stage.vhd
+++ b/modules/common/gc_async_signals_input_stage.vhd
@@ -34,13 +34,13 @@
-- Copyright (c) 2016 CERN/TE-MS-MM
--
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
+-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--
diff --git a/modules/common/gc_bicolor_led_ctrl.vhd b/modules/common/gc_bicolor_led_ctrl.vhd
index 34d6b2c2..12e18727 100644
--- a/modules/common/gc_bicolor_led_ctrl.vhd
+++ b/modules/common/gc_bicolor_led_ctrl.vhd
@@ -49,13 +49,13 @@
-- Copyright (c) 2012 - 2017 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
+-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--
diff --git a/modules/common/gc_extend_pulse.vhd b/modules/common/gc_extend_pulse.vhd
index e3a38e42..c7c2314f 100644
--- a/modules/common/gc_extend_pulse.vhd
+++ b/modules/common/gc_extend_pulse.vhd
@@ -18,13 +18,13 @@
-- Copyright (c) 2009-2011 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
+-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--
diff --git a/modules/common/gc_reset.vhd b/modules/common/gc_reset.vhd
index 6930524b..c6e53482 100644
--- a/modules/common/gc_reset.vhd
+++ b/modules/common/gc_reset.vhd
@@ -10,13 +10,13 @@
-- Copyright (c) 2012-2017 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
+-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
diff --git a/modules/common/gc_serial_dac.vhd b/modules/common/gc_serial_dac.vhd
index bdfe972f..03642718 100644
--- a/modules/common/gc_serial_dac.vhd
+++ b/modules/common/gc_serial_dac.vhd
@@ -6,7 +6,7 @@
-- Author : Pablo Alvarez Sanchez
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
--- Last update: 2011-04-29
+-- Last update: 2019-09-09
-- Platform : FPGA-generic
-- Standard : VHDL '87
-------------------------------------------------------------------------------
@@ -17,13 +17,13 @@
-- Copyright (c) 2009 - 2010 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
+-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--
diff --git a/modules/genrams/xilinx/generic_simple_dpram.vhd b/modules/genrams/xilinx/generic_simple_dpram.vhd
index 0aae1de1..7a5778fd 100644
--- a/modules/genrams/xilinx/generic_simple_dpram.vhd
+++ b/modules/genrams/xilinx/generic_simple_dpram.vhd
@@ -21,13 +21,13 @@
-- Copyright (c) 2011 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
+-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--
diff --git a/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd b/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
index f1238f06..eeb58b71 100644
--- a/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
@@ -1,125 +1,125 @@
--------------------------------------------------------------------------------
--- Title : AXI4Lite-to-WB bridge
--- Project : General Cores
--------------------------------------------------------------------------------
--- File : wb_axi4lite_bridge.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN
--- Platform : FPGA-generics
--- Standard : VHDL '93
--------------------------------------------------------------------------------
--- Copyright (c) 2017 CERN
---
--- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
--- to treat this file as licensed under the Apache License 2.0); you may not
--- use this file except in compliance with the License. You may obtain a copy
--- of the License at http://solderpad.org/licenses/SHL-0.51.
--- Unless required by applicable law or agreed to in writing, software,
--- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
--- or implied. See the License for the specific language governing permissions
--- and limitations under the License.
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.axi4_pkg.all;
-use work.wishbone_pkg.all;
-
-entity wb_axi4lite_bridge is
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
-
- ARVALID : in std_logic;
- AWVALID : in std_logic;
- BREADY : in std_logic;
- RREADY : in std_logic;
- WLAST : in std_logic;
- WVALID : in std_logic;
- ARADDR : in std_logic_vector (31 downto 0);
- AWADDR : in std_logic_vector (31 downto 0);
- WDATA : in std_logic_vector (31 downto 0);
- WSTRB : in std_logic_vector (3 downto 0);
- ARREADY : out std_logic;
- AWREADY : out std_logic;
- BVALID : out std_logic;
- RLAST : out std_logic;
- RVALID : out std_logic;
- WREADY : out std_logic;
- BRESP : out std_logic_vector (1 downto 0);
- RRESP : out std_logic_vector (1 downto 0);
- RDATA : out std_logic_vector (31 downto 0);
-
- wb_adr : out std_logic_vector(c_wishbone_address_width-1 downto 0);
- wb_dat_m2s : out std_logic_vector(c_wishbone_data_width-1 downto 0);
- wb_sel : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
- wb_cyc : out std_logic;
- wb_stb : out std_logic;
- wb_we : out std_logic;
-
- wb_dat_s2m : in std_logic_vector(c_wishbone_data_width-1 downto 0);
- wb_err : in std_logic := '0';
- wb_rty : in std_logic := '0';
- wb_ack : in std_logic;
- wb_stall : in std_logic
- );
-
-end wb_axi4lite_bridge;
-
-architecture rtl of wb_axi4lite_bridge is
-
- signal axi_in : t_axi4_lite_master_out_32;
- signal axi_out : t_axi4_lite_master_in_32;
- signal wb_in : t_wishbone_master_in;
- signal wb_out : t_wishbone_master_out;
-
-begin
-
- axi_in.ARVALID <= ARVALID;
- axi_in.AWVALID <= AWVALID;
- axi_in.BREADY <= BREADY;
- axi_in.RREADY <= RREADY;
- axi_in.WLAST <= WLAST;
- axi_in.WVALID <= WVALID;
- axi_in.ARADDR <= ARADDR;
- axi_in.AWADDR <= AWADDR;
- axi_in.WDATA <= WDATA;
- axi_in.WSTRB <= WSTRB;
- ARREADY <= axi_out.ARREADY;
- AWREADY <= axi_out.AWREADY;
- BVALID <= axi_out.BVALID;
- RLAST <= axi_out.RLAST;
- RVALID <= axi_out.RVALID;
- WREADY <= axi_out.WREADY;
- BRESP <= axi_out.BRESP;
- RRESP <= axi_out.RRESP;
- RDATA <= axi_out.RDATA;
-
- wb_adr <= wb_out.adr;
- wb_dat_m2s <= wb_out.dat;
- wb_stb <= wb_out.stb;
- wb_sel <= wb_out.sel;
- wb_cyc <= wb_out.cyc;
- wb_we <= wb_out.we;
-
- wb_in.err <= wb_err;
- wb_in.rty <= wb_rty;
- wb_in.ack <= wb_ack;
- wb_in.stall <= wb_stall;
- wb_in.dat <= wb_dat_s2m;
-
- U_Wrapped_Bridge : xwb_axi4lite_bridge
- port map (
- clk_sys_i => clk_sys_i,
- rst_n_i => rst_n_i,
- axi4_slave_i => axi_in,
- axi4_slave_o => axi_out,
- wb_master_o => wb_out,
- wb_master_i => wb_in);
-
-end rtl;
-
+-------------------------------------------------------------------------------
+-- Title : AXI4Lite-to-WB bridge
+-- Project : General Cores
+-------------------------------------------------------------------------------
+-- File : wb_axi4lite_bridge.vhd
+-- Author : Tomasz Wlostowski
+-- Company : CERN
+-- Platform : FPGA-generics
+-- Standard : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 0.51 (the "License") (which enables you, at your option,
+-- to treat this file as licensed under the Apache License 2.0); you may not
+-- use this file except in compliance with the License. You may obtain a copy
+-- of the License at http://solderpad.org/licenses/SHL-0.51.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.axi4_pkg.all;
+use work.wishbone_pkg.all;
+
+entity wb_axi4lite_bridge is
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ ARVALID : in std_logic;
+ AWVALID : in std_logic;
+ BREADY : in std_logic;
+ RREADY : in std_logic;
+ WLAST : in std_logic;
+ WVALID : in std_logic;
+ ARADDR : in std_logic_vector (31 downto 0);
+ AWADDR : in std_logic_vector (31 downto 0);
+ WDATA : in std_logic_vector (31 downto 0);
+ WSTRB : in std_logic_vector (3 downto 0);
+ ARREADY : out std_logic;
+ AWREADY : out std_logic;
+ BVALID : out std_logic;
+ RLAST : out std_logic;
+ RVALID : out std_logic;
+ WREADY : out std_logic;
+ BRESP : out std_logic_vector (1 downto 0);
+ RRESP : out std_logic_vector (1 downto 0);
+ RDATA : out std_logic_vector (31 downto 0);
+
+ wb_adr : out std_logic_vector(c_wishbone_address_width-1 downto 0);
+ wb_dat_m2s : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_sel : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+ wb_cyc : out std_logic;
+ wb_stb : out std_logic;
+ wb_we : out std_logic;
+
+ wb_dat_s2m : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_err : in std_logic := '0';
+ wb_rty : in std_logic := '0';
+ wb_ack : in std_logic;
+ wb_stall : in std_logic
+ );
+
+end wb_axi4lite_bridge;
+
+architecture rtl of wb_axi4lite_bridge is
+
+ signal axi_in : t_axi4_lite_master_out_32;
+ signal axi_out : t_axi4_lite_master_in_32;
+ signal wb_in : t_wishbone_master_in;
+ signal wb_out : t_wishbone_master_out;
+
+begin
+
+ axi_in.ARVALID <= ARVALID;
+ axi_in.AWVALID <= AWVALID;
+ axi_in.BREADY <= BREADY;
+ axi_in.RREADY <= RREADY;
+ axi_in.WLAST <= WLAST;
+ axi_in.WVALID <= WVALID;
+ axi_in.ARADDR <= ARADDR;
+ axi_in.AWADDR <= AWADDR;
+ axi_in.WDATA <= WDATA;
+ axi_in.WSTRB <= WSTRB;
+ ARREADY <= axi_out.ARREADY;
+ AWREADY <= axi_out.AWREADY;
+ BVALID <= axi_out.BVALID;
+ RLAST <= axi_out.RLAST;
+ RVALID <= axi_out.RVALID;
+ WREADY <= axi_out.WREADY;
+ BRESP <= axi_out.BRESP;
+ RRESP <= axi_out.RRESP;
+ RDATA <= axi_out.RDATA;
+
+ wb_adr <= wb_out.adr;
+ wb_dat_m2s <= wb_out.dat;
+ wb_stb <= wb_out.stb;
+ wb_sel <= wb_out.sel;
+ wb_cyc <= wb_out.cyc;
+ wb_we <= wb_out.we;
+
+ wb_in.err <= wb_err;
+ wb_in.rty <= wb_rty;
+ wb_in.ack <= wb_ack;
+ wb_in.stall <= wb_stall;
+ wb_in.dat <= wb_dat_s2m;
+
+ U_Wrapped_Bridge : xwb_axi4lite_bridge
+ port map (
+ clk_sys_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+ axi4_slave_i => axi_in,
+ axi4_slave_o => axi_out,
+ wb_master_o => wb_out,
+ wb_master_i => wb_in);
+
+end rtl;
+
diff --git a/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd b/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
index 3b4b9978..dbcb448b 100644
--- a/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
@@ -1,191 +1,191 @@
--------------------------------------------------------------------------------
--- Title : AXI4Lite-to-WB bridge wrapper
--- Project : General Cores
--------------------------------------------------------------------------------
--- File : xwb_axi4lite_bridge.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN
--- Platform : FPGA-generics
--- Standard : VHDL '93
--------------------------------------------------------------------------------
--- Copyright (c) 2017 CERN
---
--- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
--- to treat this file as licensed under the Apache License 2.0); you may not
--- use this file except in compliance with the License. You may obtain a copy
--- of the License at http://solderpad.org/licenses/SHL-0.51.
--- Unless required by applicable law or agreed to in writing, software,
--- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
--- or implied. See the License for the specific language governing permissions
--- and limitations under the License.
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.axi4_pkg.all;
-use work.wishbone_pkg.all;
-
-entity xwb_axi4lite_bridge is
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
-
- axi4_slave_i : in t_axi4_lite_slave_in_32;
- axi4_slave_o : out t_axi4_lite_slave_out_32;
-
- wb_master_o : out t_wishbone_master_out;
- wb_master_i : in t_wishbone_master_in
-
- );
-
-end xwb_axi4lite_bridge;
-
-architecture rtl of xwb_axi4lite_bridge is
-
- constant c_timeout : integer := 256;
-
- type t_state is
- (IDLE, ISSUE_WRITE, ISSUE_READ, COMPLETE_WRITE, COMPLETE_READ, WAIT_ACK_READ, WAIT_ACK_WRITE, RESPONSE_READ, RESPONSE_WRITE);
-
- signal state : t_state;
-
- signal count : unsigned(10 downto 0);
-
-begin
-
- process(clk_sys_i)
- begin
- if rising_edge(clk_sys_i) then
- if rst_n_i = '0' then
- axi4_slave_o <= c_axi4_lite_default_master_in_32;
- wb_master_o.cyc <= '0';
- state <= IDLE;
- else
- case state is
- when IDLE =>
- wb_master_o.cyc <= '0';
- axi4_slave_o.ARREADY <= '1';
- axi4_slave_o.AWREADY <= '1';
- axi4_slave_o.WREADY <= '0';
- axi4_slave_o.BVALID <= '0';
- axi4_slave_o.BRESP <= (others => 'X');
- axi4_slave_o.RDATA <= (others => 'X');
- axi4_slave_o.RRESP <= (others => 'X');
- axi4_slave_o.RVALID <= '0';
- axi4_slave_o.RLAST <= '0';
-
- if(axi4_slave_i.AWVALID = '1') then
- state <= ISSUE_WRITE;
- wb_master_o.adr <= axi4_slave_i.AWADDR;
- elsif (axi4_slave_i.ARVALID = '1') then
- state <= ISSUE_READ;
- wb_master_o.adr <= axi4_slave_i.ARADDR;
- end if;
-
- when ISSUE_WRITE =>
- axi4_slave_o.WREADY <= '1';
-
- wb_master_o.cyc <= '1';
- wb_master_o.we <= '1';
-
- if(axi4_slave_i.WVALID = '1') then
- wb_master_o.stb <= '1';
- wb_master_o.sel <= axi4_slave_i.WSTRB;
- wb_master_o.dat <= axi4_slave_i.WDATA;
- state <= COMPLETE_WRITE;
- end if;
-
- when ISSUE_READ =>
-
- wb_master_o.cyc <= '1';
- wb_master_o.stb <= '1';
- wb_master_o.we <= '0';
- axi4_slave_o.RVALID <= '0';
- axi4_slave_o.RLAST <= '0';
- state <= COMPLETE_READ;
-
- when COMPLETE_READ =>
- if(wb_master_i.stall = '0') then
- wb_master_o.stb <= '0';
- if(wb_master_i.ack = '1') then
- state <= IDLE;
- axi4_slave_o.RRESP <= c_AXI4_RESP_EXOKAY;
- axi4_slave_o.RDATA <= wb_master_i.dat;
- axi4_slave_o.RVALID <= '1';
- axi4_slave_o.RLAST <= '1';
- wb_master_o.cyc <= '0';
- else
- state <= WAIT_ACK_READ;
- count <= (others => '0');
- end if;
- end if;
-
-
- when COMPLETE_WRITE =>
- if(wb_master_i.stall = '0') then
- wb_master_o.stb <= '0';
- if(wb_master_i.ack = '1') then
- state <= RESPONSE_WRITE;
- axi4_slave_o.BRESP <= c_AXI4_RESP_EXOKAY;
- wb_master_o.cyc <= '0';
- else
- state <= WAIT_ACK_WRITE;
- count <= (others => '0');
- end if;
- end if;
-
-
- when WAIT_ACK_WRITE =>
- if(wb_master_i.ack = '1') then
- state <= RESPONSE_WRITE;
- axi4_slave_o.BRESP <= c_AXI4_RESP_EXOKAY;
- wb_master_o.cyc <= '0';
- elsif count = c_timeout then
- state <= RESPONSE_WRITE;
- axi4_slave_o.BRESP <= c_AXI4_RESP_SLVERR;
- wb_master_o.cyc <= '0';
- end if;
- count <= count + 1;
-
- when WAIT_ACK_READ =>
- if(wb_master_i.ack = '1') then
- state <= IDLE;
- axi4_slave_o.RRESP <= c_AXI4_RESP_EXOKAY;
- axi4_slave_o.RVALID <= '1';
- axi4_slave_o.RLAST <= '1';
- axi4_slave_o.RDATA <= wb_master_i.dat;
- wb_master_o.cyc <= '0';
- elsif count = c_timeout then
- state <= IDLE;
- axi4_slave_o.RRESP <= c_AXI4_RESP_SLVERR;
- axi4_slave_o.RVALID <= '1';
- axi4_slave_o.RLAST <= '1';
- axi4_slave_o.RDATA <= (others => 'X');
- wb_master_o.cyc <= '0';
- end if;
- count <= count + 1;
-
-
- when RESPONSE_WRITE =>
- if (axi4_slave_i.BREADY = '1') then
- axi4_slave_o.BVALID <= '1';
- state <= IDLE;
- end if;
-
- when RESPONSE_READ => null;
-
-
- end case;
-
-
-
- end if;
- end if;
- end process;
-
-end rtl;
-
+-------------------------------------------------------------------------------
+-- Title : AXI4Lite-to-WB bridge wrapper
+-- Project : General Cores
+-------------------------------------------------------------------------------
+-- File : xwb_axi4lite_bridge.vhd
+-- Author : Tomasz Wlostowski
+-- Company : CERN
+-- Platform : FPGA-generics
+-- Standard : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 0.51 (the "License") (which enables you, at your option,
+-- to treat this file as licensed under the Apache License 2.0); you may not
+-- use this file except in compliance with the License. You may obtain a copy
+-- of the License at http://solderpad.org/licenses/SHL-0.51.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.axi4_pkg.all;
+use work.wishbone_pkg.all;
+
+entity xwb_axi4lite_bridge is
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ axi4_slave_i : in t_axi4_lite_slave_in_32;
+ axi4_slave_o : out t_axi4_lite_slave_out_32;
+
+ wb_master_o : out t_wishbone_master_out;
+ wb_master_i : in t_wishbone_master_in
+
+ );
+
+end xwb_axi4lite_bridge;
+
+architecture rtl of xwb_axi4lite_bridge is
+
+ constant c_timeout : integer := 256;
+
+ type t_state is
+ (IDLE, ISSUE_WRITE, ISSUE_READ, COMPLETE_WRITE, COMPLETE_READ, WAIT_ACK_READ, WAIT_ACK_WRITE, RESPONSE_READ, RESPONSE_WRITE);
+
+ signal state : t_state;
+
+ signal count : unsigned(10 downto 0);
+
+begin
+
+ process(clk_sys_i)
+ begin
+ if rising_edge(clk_sys_i) then
+ if rst_n_i = '0' then
+ axi4_slave_o <= c_axi4_lite_default_master_in_32;
+ wb_master_o.cyc <= '0';
+ state <= IDLE;
+ else
+ case state is
+ when IDLE =>
+ wb_master_o.cyc <= '0';
+ axi4_slave_o.ARREADY <= '1';
+ axi4_slave_o.AWREADY <= '1';
+ axi4_slave_o.WREADY <= '0';
+ axi4_slave_o.BVALID <= '0';
+ axi4_slave_o.BRESP <= (others => 'X');
+ axi4_slave_o.RDATA <= (others => 'X');
+ axi4_slave_o.RRESP <= (others => 'X');
+ axi4_slave_o.RVALID <= '0';
+ axi4_slave_o.RLAST <= '0';
+
+ if(axi4_slave_i.AWVALID = '1') then
+ state <= ISSUE_WRITE;
+ wb_master_o.adr <= axi4_slave_i.AWADDR;
+ elsif (axi4_slave_i.ARVALID = '1') then
+ state <= ISSUE_READ;
+ wb_master_o.adr <= axi4_slave_i.ARADDR;
+ end if;
+
+ when ISSUE_WRITE =>
+ axi4_slave_o.WREADY <= '1';
+
+ wb_master_o.cyc <= '1';
+ wb_master_o.we <= '1';
+
+ if(axi4_slave_i.WVALID = '1') then
+ wb_master_o.stb <= '1';
+ wb_master_o.sel <= axi4_slave_i.WSTRB;
+ wb_master_o.dat <= axi4_slave_i.WDATA;
+ state <= COMPLETE_WRITE;
+ end if;
+
+ when ISSUE_READ =>
+
+ wb_master_o.cyc <= '1';
+ wb_master_o.stb <= '1';
+ wb_master_o.we <= '0';
+ axi4_slave_o.RVALID <= '0';
+ axi4_slave_o.RLAST <= '0';
+ state <= COMPLETE_READ;
+
+ when COMPLETE_READ =>
+ if(wb_master_i.stall = '0') then
+ wb_master_o.stb <= '0';
+ if(wb_master_i.ack = '1') then
+ state <= IDLE;
+ axi4_slave_o.RRESP <= c_AXI4_RESP_EXOKAY;
+ axi4_slave_o.RDATA <= wb_master_i.dat;
+ axi4_slave_o.RVALID <= '1';
+ axi4_slave_o.RLAST <= '1';
+ wb_master_o.cyc <= '0';
+ else
+ state <= WAIT_ACK_READ;
+ count <= (others => '0');
+ end if;
+ end if;
+
+
+ when COMPLETE_WRITE =>
+ if(wb_master_i.stall = '0') then
+ wb_master_o.stb <= '0';
+ if(wb_master_i.ack = '1') then
+ state <= RESPONSE_WRITE;
+ axi4_slave_o.BRESP <= c_AXI4_RESP_EXOKAY;
+ wb_master_o.cyc <= '0';
+ else
+ state <= WAIT_ACK_WRITE;
+ count <= (others => '0');
+ end if;
+ end if;
+
+
+ when WAIT_ACK_WRITE =>
+ if(wb_master_i.ack = '1') then
+ state <= RESPONSE_WRITE;
+ axi4_slave_o.BRESP <= c_AXI4_RESP_EXOKAY;
+ wb_master_o.cyc <= '0';
+ elsif count = c_timeout then
+ state <= RESPONSE_WRITE;
+ axi4_slave_o.BRESP <= c_AXI4_RESP_SLVERR;
+ wb_master_o.cyc <= '0';
+ end if;
+ count <= count + 1;
+
+ when WAIT_ACK_READ =>
+ if(wb_master_i.ack = '1') then
+ state <= IDLE;
+ axi4_slave_o.RRESP <= c_AXI4_RESP_EXOKAY;
+ axi4_slave_o.RVALID <= '1';
+ axi4_slave_o.RLAST <= '1';
+ axi4_slave_o.RDATA <= wb_master_i.dat;
+ wb_master_o.cyc <= '0';
+ elsif count = c_timeout then
+ state <= IDLE;
+ axi4_slave_o.RRESP <= c_AXI4_RESP_SLVERR;
+ axi4_slave_o.RVALID <= '1';
+ axi4_slave_o.RLAST <= '1';
+ axi4_slave_o.RDATA <= (others => 'X');
+ wb_master_o.cyc <= '0';
+ end if;
+ count <= count + 1;
+
+
+ when RESPONSE_WRITE =>
+ if (axi4_slave_i.BREADY = '1') then
+ axi4_slave_o.BVALID <= '1';
+ state <= IDLE;
+ end if;
+
+ when RESPONSE_READ => null;
+
+
+ end case;
+
+
+
+ end if;
+ end if;
+ end process;
+
+end rtl;
+
diff --git a/modules/wishbone/wb_irq/msidemo/crt0.S b/modules/wishbone/wb_irq/msidemo/crt0.S
index de7de225..eca38268 100644
--- a/modules/wishbone/wb_irq/msidemo/crt0.S
+++ b/modules/wishbone/wb_irq/msidemo/crt0.S
@@ -1,138 +1,138 @@
-/****************************************************************************
-**
-** Name: crt0ram.S
-**
-** Description:
-** Implements boot-code that calls LatticeDDInit (that calls main())
-** Implements exception handlers (actually, redirectors)
-**
-** $Revision: $
-**
-** Disclaimer:
-**
-** This source code is intended as a design reference which
-** illustrates how these types of functions can be implemented. It
-** is the user's responsibility to verify their design for
-** consistency and functionality through the use of formal
-** verification methods. Lattice Semiconductor provides no warranty
-** regarding the use or functionality of this code.
-**
-** --------------------------------------------------------------------
-**
-** Lattice Semiconductor Corporation
-** 5555 NE Moore Court
-** Hillsboro, OR 97214
-** U.S.A
-**
-** TEL: 1-800-Lattice (USA and Canada)
-** (503)268-8001 (other locations)
-**
-** web: http://www.latticesemi.com
-** email: techsupport@latticesemi.com
-**
-** --------------------------------------------------------------------------
-**
-** Change History (Latest changes on top)
-**
-** Ver Date Description
-** --------------------------------------------------------------------------
-** 3.8 Apr-15-2011 Added __MICO_USER_<handler>_HANDLER__ preprocessor to
-** allow customers to implement their own handlers for:
-** DATA_ABORT, INST_ABORT
-**
-** 3.1 Jun-18-2008 Added __MICO_NO_INTERRUPTS__ preprocessor
-** option to exclude invoking MicoISRHandler
-** to reduce code-size in apps that don't use
-** interrupts
-**
-** 3.0 Mar-25-2008 Added Header
-**
-**---------------------------------------------------------------------------
-*****************************************************************************/
-
-/*
- * LatticeMico32 C startup code.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/* From include/sys/signal.h */
-#define SIGINT 2 /* interrupt */
-#define SIGTRAP 5 /* trace trap */
-#define SIGFPE 8 /* arithmetic exception */
-#define SIGSEGV 11 /* segmentation violation */
+/****************************************************************************
+**
+** Name: crt0ram.S
+**
+** Description:
+** Implements boot-code that calls LatticeDDInit (that calls main())
+** Implements exception handlers (actually, redirectors)
+**
+** $Revision: $
+**
+** Disclaimer:
+**
+** This source code is intended as a design reference which
+** illustrates how these types of functions can be implemented. It
+** is the user's responsibility to verify their design for
+** consistency and functionality through the use of formal
+** verification methods. Lattice Semiconductor provides no warranty
+** regarding the use or functionality of this code.
+**
+** --------------------------------------------------------------------
+**
+** Lattice Semiconductor Corporation
+** 5555 NE Moore Court
+** Hillsboro, OR 97214
+** U.S.A
+**
+** TEL: 1-800-Lattice (USA and Canada)
+** (503)268-8001 (other locations)
+**
+** web: http://www.latticesemi.com
+** email: techsupport@latticesemi.com
+**
+** --------------------------------------------------------------------------
+**
+** Change History (Latest changes on top)
+**
+** Ver Date Description
+** --------------------------------------------------------------------------
+** 3.8 Apr-15-2011 Added __MICO_USER_<handler>_HANDLER__ preprocessor to
+** allow customers to implement their own handlers for:
+** DATA_ABORT, INST_ABORT
+**
+** 3.1 Jun-18-2008 Added __MICO_NO_INTERRUPTS__ preprocessor
+** option to exclude invoking MicoISRHandler
+** to reduce code-size in apps that don't use
+** interrupts
+**
+** 3.0 Mar-25-2008 Added Header
+**
+**---------------------------------------------------------------------------
+*****************************************************************************/
-//#define MICO32_FULL_CONTEXT_SAVE_RESTORE
+/*
+ * LatticeMico32 C startup code.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
-
-/* Exception handlers - Must be 32 bytes long. */
- .section .boot, "ax", @progbits
-
- .global _start
-_start:
-
- .global _reset_handler
- .type _reset_handler, @function
-_reset_handler:
- xor r0, r0, r0
- wcsr IE, r0
- wcsr IM, r0
- mvhi r1, hi(_reset_handler)
- ori r1, r1, lo(_reset_handler)
- wcsr EBA, r1
- calli _crt0
- nop
- .size _reset_handler, .-_reset_handler
-
+/* From include/sys/signal.h */
+#define SIGINT 2 /* interrupt */
+#define SIGTRAP 5 /* trace trap */
+#define SIGFPE 8 /* arithmetic exception */
+#define SIGSEGV 11 /* segmentation violation */
+
+//#define MICO32_FULL_CONTEXT_SAVE_RESTORE
+
+
+/* Exception handlers - Must be 32 bytes long. */
+ .section .boot, "ax", @progbits
+
+ .global _start
+_start:
+
+ .global _reset_handler
+ .type _reset_handler, @function
+_reset_handler:
+ xor r0, r0, r0
+ wcsr IE, r0
+ wcsr IM, r0
+ mvhi r1, hi(_reset_handler)
+ ori r1, r1, lo(_reset_handler)
+ wcsr EBA, r1
+ calli _crt0
+ nop
+ .size _reset_handler, .-_reset_handler
+
.extern _irq_entry
.org 0xc0
- .global _interrupt_handler
- .type _interrupt_handler, @function
-_interrupt_handler:
- sw (sp+0), ra
- calli _save_all
- mvi r1, SIGINT
-#ifndef __MICO_NO_INTERRUPTS__
+ .global _interrupt_handler
+ .type _interrupt_handler, @function
+_interrupt_handler:
+ sw (sp+0), ra
+ calli _save_all
+ mvi r1, SIGINT
+#ifndef __MICO_NO_INTERRUPTS__
calli _irq_entry
-#else
- wcsr IE, r0
-#endif
- bi _restore_all_and_return
- nop
- nop
- nop
+#else
+ wcsr IE, r0
+#endif
+ bi _restore_all_and_return
+ nop
+ nop
+ nop
.org 0x100
- .global _crt0
- .type _crt0, @function
-_crt0:
- /* Clear r0 */
- xor r0, r0, r0
- /* Setup stack and global pointer */
- mvhi sp, hi(_fstack)
- ori sp, sp, lo(_fstack)
- mvhi gp, hi(_gp)
- ori gp, gp, lo(_gp)
-
+ .global _crt0
+ .type _crt0, @function
+_crt0:
+ /* Clear r0 */
+ xor r0, r0, r0
+ /* Setup stack and global pointer */
+ mvhi sp, hi(_fstack)
+ ori sp, sp, lo(_fstack)
+ mvhi gp, hi(_gp)
+ ori gp, gp, lo(_gp)
+
mvhi r1, hi(_fbss)
ori r1, r1, lo(_fbss)
mvi r2, 0
@@ -140,120 +140,120 @@ _crt0:
ori r3, r3, lo(_ebss)
sub r3, r3, r1
calli memset
- mvi r1, 0
- mvi r2, 0
- mvi r3, 0
+ mvi r1, 0
+ mvi r2, 0
+ mvi r3, 0
calli main
loopf:
bi loopf
- .global _save_all
- .type _save_all, @function
-_save_all:
-#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
- addi sp, sp, -128
-#else
- addi sp, sp, -60
-#endif
- sw (sp+4), r1
- sw (sp+8), r2
- sw (sp+12), r3
- sw (sp+16), r4
- sw (sp+20), r5
- sw (sp+24), r6
- sw (sp+28), r7
- sw (sp+32), r8
- sw (sp+36), r9
- sw (sp+40), r10
-#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
- sw (sp+44), r11
- sw (sp+48), r12
- sw (sp+52), r13
- sw (sp+56), r14
- sw (sp+60), r15
- sw (sp+64), r16
- sw (sp+68), r17
- sw (sp+72), r18
- sw (sp+76), r19
- sw (sp+80), r20
- sw (sp+84), r21
- sw (sp+88), r22
- sw (sp+92), r23
- sw (sp+96), r24
- sw (sp+100), r25
- sw (sp+104), r26
- sw (sp+108), r27
- sw (sp+120), ea
- sw (sp+124), ba
- /* ra and sp need special handling, as they have been modified */
- lw r1, (sp+128)
- sw (sp+116), r1
- mv r1, sp
- addi r1, r1, 128
- sw (sp+112), r1
-#else
- sw (sp+52), ea
- sw (sp+56), ba
- /* ra and sp need special handling, as they have been modified */
- lw r1, (sp+60)
- sw (sp+48), r1
- mv r1, sp
- addi r1, r1, 60
- sw (sp+44), r1
-#endif
-// xor r1, r1, r1
-// wcsr ie, r1
- ret
- .size _save_all, .-_save_all
-
- .global _restore_all_and_return
- .type _restore_all_and_return, @function
- /* Restore all registers and return from exception */
-_restore_all_and_return:
-// addi r1, r0, 2
-// wcsr ie, r1
- lw r1, (sp+4)
- lw r2, (sp+8)
- lw r3, (sp+12)
- lw r4, (sp+16)
- lw r5, (sp+20)
- lw r6, (sp+24)
- lw r7, (sp+28)
- lw r8, (sp+32)
- lw r9, (sp+36)
- lw r10, (sp+40)
-#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
- lw r11, (sp+44)
- lw r12, (sp+48)
- lw r13, (sp+52)
- lw r14, (sp+56)
- lw r15, (sp+60)
- lw r16, (sp+64)
- lw r17, (sp+68)
- lw r18, (sp+72)
- lw r19, (sp+76)
- lw r20, (sp+80)
- lw r21, (sp+84)
- lw r22, (sp+88)
- lw r23, (sp+92)
- lw r24, (sp+96)
- lw r25, (sp+100)
- lw r26, (sp+104)
- lw r27, (sp+108)
- lw ra, (sp+116)
- lw ea, (sp+120)
- lw ba, (sp+124)
- /* Stack pointer must be restored last, in case it has been updated */
- lw sp, (sp+112)
-#else
- lw ra, (sp+48)
- lw ea, (sp+52)
- lw ba, (sp+56)
- /* Stack pointer must be restored last, in case it has been updated */
- lw sp, (sp+44)
-#endif
- nop
- eret
- .size _restore_all_and_return, .-_restore_all_and_return
-
+ .global _save_all
+ .type _save_all, @function
+_save_all:
+#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
+ addi sp, sp, -128
+#else
+ addi sp, sp, -60
+#endif
+ sw (sp+4), r1
+ sw (sp+8), r2
+ sw (sp+12), r3
+ sw (sp+16), r4
+ sw (sp+20), r5
+ sw (sp+24), r6
+ sw (sp+28), r7
+ sw (sp+32), r8
+ sw (sp+36), r9
+ sw (sp+40), r10
+#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
+ sw (sp+44), r11
+ sw (sp+48), r12
+ sw (sp+52), r13
+ sw (sp+56), r14
+ sw (sp+60), r15
+ sw (sp+64), r16
+ sw (sp+68), r17
+ sw (sp+72), r18
+ sw (sp+76), r19
+ sw (sp+80), r20
+ sw (sp+84), r21
+ sw (sp+88), r22
+ sw (sp+92), r23
+ sw (sp+96), r24
+ sw (sp+100), r25
+ sw (sp+104), r26
+ sw (sp+108), r27
+ sw (sp+120), ea
+ sw (sp+124), ba
+ /* ra and sp need special handling, as they have been modified */
+ lw r1, (sp+128)
+ sw (sp+116), r1
+ mv r1, sp
+ addi r1, r1, 128
+ sw (sp+112), r1
+#else
+ sw (sp+52), ea
+ sw (sp+56), ba
+ /* ra and sp need special handling, as they have been modified */
+ lw r1, (sp+60)
+ sw (sp+48), r1
+ mv r1, sp
+ addi r1, r1, 60
+ sw (sp+44), r1
+#endif
+// xor r1, r1, r1
+// wcsr ie, r1
+ ret
+ .size _save_all, .-_save_all
+
+ .global _restore_all_and_return
+ .type _restore_all_and_return, @function
+ /* Restore all registers and return from exception */
+_restore_all_and_return:
+// addi r1, r0, 2
+// wcsr ie, r1
+ lw r1, (sp+4)
+ lw r2, (sp+8)
+ lw r3, (sp+12)
+ lw r4, (sp+16)
+ lw r5, (sp+20)
+ lw r6, (sp+24)
+ lw r7, (sp+28)
+ lw r8, (sp+32)
+ lw r9, (sp+36)
+ lw r10, (sp+40)
+#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
+ lw r11, (sp+44)
+ lw r12, (sp+48)
+ lw r13, (sp+52)
+ lw r14, (sp+56)
+ lw r15, (sp+60)
+ lw r16, (sp+64)
+ lw r17, (sp+68)
+ lw r18, (sp+72)
+ lw r19, (sp+76)
+ lw r20, (sp+80)
+ lw r21, (sp+84)
+ lw r22, (sp+88)
+ lw r23, (sp+92)
+ lw r24, (sp+96)
+ lw r25, (sp+100)
+ lw r26, (sp+104)
+ lw r27, (sp+108)
+ lw ra, (sp+116)
+ lw ea, (sp+120)
+ lw ba, (sp+124)
+ /* Stack pointer must be restored last, in case it has been updated */
+ lw sp, (sp+112)
+#else
+ lw ra, (sp+48)
+ lw ea, (sp+52)
+ lw ba, (sp+56)
+ /* Stack pointer must be restored last, in case it has been updated */
+ lw sp, (sp+44)
+#endif
+ nop
+ eret
+ .size _restore_all_and_return, .-_restore_all_and_return
+
diff --git a/modules/wishbone/wb_lm32/platform/kintex7/jtag_tap.v b/modules/wishbone/wb_lm32/platform/kintex7/jtag_tap.v
index 555a9458..5938e9e7 100644
--- a/modules/wishbone/wb_lm32/platform/kintex7/jtag_tap.v
+++ b/modules/wishbone/wb_lm32/platform/kintex7/jtag_tap.v
@@ -1,45 +1,45 @@
-
-module jtag_tap(
- output tck,
- output tdi,
- input tdo,
- output capture,
- output shift,
- output e1dr,
- output update,
- output reset
-);
-
-// Unfortunately the exit1 state for DR (e1dr) is mising
-// We can simulate it by interpretting 'update' as e1dr and delaying 'update'
-wire sel;
-wire g_capture;
-wire g_shift;
-wire g_update;
-reg update_delay;
-
-assign capture = g_capture & sel;
-assign shift = g_shift & sel;
-assign e1dr = g_update & sel;
-assign update = update_delay;
-
-BSCANE2 #(
- .JTAG_CHAIN(1)
-) bscan (
- .CAPTURE(g_capture),
- .DRCK(tck),
- .RESET(reset),
- .RUNTEST(),
- .SEL(sel),
- .SHIFT(g_shift),
- .TCK(),
- .TDI(tdi),
- .TMS(),
- .UPDATE(g_update),
- .TDO(tdo)
-);
-
-always@(posedge tck)
- update_delay <= g_update;
-
-endmodule
+
+module jtag_tap(
+ output tck,
+ output tdi,
+ input tdo,
+ output capture,
+ output shift,
+ output e1dr,
+ output update,
+ output reset
+);
+
+// Unfortunately the exit1 state for DR (e1dr) is mising
+// We can simulate it by interpretting 'update' as e1dr and delaying 'update'
+wire sel;
+wire g_capture;
+wire g_shift;
+wire g_update;
+reg update_delay;
+
+assign capture = g_capture & sel;
+assign shift = g_shift & sel;
+assign e1dr = g_update & sel;
+assign update = update_delay;
+
+BSCANE2 #(
+ .JTAG_CHAIN(1)
+) bscan (
+ .CAPTURE(g_capture),
+ .DRCK(tck),
+ .RESET(reset),
+ .RUNTEST(),
+ .SEL(sel),
+ .SHIFT(g_shift),
+ .TCK(),
+ .TDI(tdi),
+ .TMS(),
+ .UPDATE(g_update),
+ .TDO(tdo)
+);
+
+always@(posedge tck)
+ update_delay <= g_update;
+
+endmodule
diff --git a/modules/wishbone/wb_lm32/platform/kintex7/lm32_multiplier.v b/modules/wishbone/wb_lm32/platform/kintex7/lm32_multiplier.v
index e888c11c..8b854ff1 100644
--- a/modules/wishbone/wb_lm32/platform/kintex7/lm32_multiplier.v
+++ b/modules/wishbone/wb_lm32/platform/kintex7/lm32_multiplier.v
@@ -1,120 +1,120 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
-//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
-// FILE DETAILS
-// Project : LatticeMico32
-// File : lm32_multiplier.v
-// Title : Pipelined multiplier.
-// Dependencies : lm32_include.v
-// Version : 6.1.17
-// : Initial Release
-// Version : 7.0SP2, 3.0
-// : No Change
-// Version : 3.1
-// : No Change
-// =============================================================================
-
-`include "../../src/lm32_include.v"
-//`include "lm32_include.v"
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_multiplier (
- // ----- Inputs -----
- clk_i,
- rst_i,
- stall_x,
- stall_m,
- operand_0,
- operand_1,
- // ----- Ouputs -----
- result
- );
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input clk_i; // Clock
-input rst_i; // Reset
-input stall_x; // Stall instruction in X stage
-input stall_m; // Stall instruction in M stage
-input [`LM32_WORD_RNG] operand_0; // Muliplicand
-input [`LM32_WORD_RNG] operand_1; // Multiplier
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output [`LM32_WORD_RNG] result; // Product of multiplication
-wire [`LM32_WORD_RNG] result;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-// Divide multiplicands into high and low
-`define HALF_WORD_WIDTH (`LM32_WORD_WIDTH/2)
-`define HALF_WORD_RNG (`HALF_WORD_WIDTH-1):0
-
-// Result = c+d+e = a*b
-reg [`HALF_WORD_RNG] a0, a1, b0, b1;
-reg [`HALF_WORD_RNG] c0, c1;
-reg [`HALF_WORD_RNG] d1, e1;
-reg [`HALF_WORD_RNG] result0, result1;
-
-assign result = {result1, result0};
-
-/////////////////////////////////////////////////////
-// Sequential logic
-/////////////////////////////////////////////////////
-
-always @(posedge clk_i `CFG_RESET_SENSITIVITY)
-begin
- if (rst_i == `TRUE)
- begin
- a0 <= {`HALF_WORD_WIDTH{1'b0}};
- a1 <= {`HALF_WORD_WIDTH{1'b0}};
- b0 <= {`HALF_WORD_WIDTH{1'b0}};
- b1 <= {`HALF_WORD_WIDTH{1'b0}};
- c0 <= {`HALF_WORD_WIDTH{1'b0}};
- c1 <= {`HALF_WORD_WIDTH{1'b0}};
- d1 <= {`HALF_WORD_WIDTH{1'b0}};
- e1 <= {`HALF_WORD_WIDTH{1'b0}};
- result0 <= {`HALF_WORD_WIDTH{1'b0}};
- result1 <= {`HALF_WORD_WIDTH{1'b0}};
- end
- else
- begin
- if (stall_x == `FALSE)
- begin
- {a1, a0} <= operand_0;
- {b1, b0} <= operand_1;
- end
- if (stall_m == `FALSE)
- begin
- {c1, c0} <= a0 * b0;
- d1 <= a0 * b1;
- e1 <= a1 * b0;
- end
-
- result0 <= c0;
- result1 <= c1 + d1 + e1;
- end
-end
-
-endmodule
+// =============================================================================
+// COPYRIGHT NOTICE
+// Copyright 2006 (c) Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// This confidential and proprietary software may be used only as authorised by
+// a licensing agreement from Lattice Semiconductor Corporation.
+// The entire notice above must be reproduced on all authorized copies and
+// copies may only be made to the extent permitted by a licensing agreement from
+// Lattice Semiconductor Corporation.
+//
+// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
+// 5555 NE Moore Court 408-826-6000 (other locations)
+// Hillsboro, OR 97124 web : http://www.latticesemi.com/
+// U.S.A email: techsupport@latticesemi.com
+// =============================================================================/
+// FILE DETAILS
+// Project : LatticeMico32
+// File : lm32_multiplier.v
+// Title : Pipelined multiplier.
+// Dependencies : lm32_include.v
+// Version : 6.1.17
+// : Initial Release
+// Version : 7.0SP2, 3.0
+// : No Change
+// Version : 3.1
+// : No Change
+// =============================================================================
+
+`include "../../src/lm32_include.v"
+//`include "lm32_include.v"
+
+/////////////////////////////////////////////////////
+// Module interface
+/////////////////////////////////////////////////////
+
+module lm32_multiplier (
+ // ----- Inputs -----
+ clk_i,
+ rst_i,
+ stall_x,
+ stall_m,
+ operand_0,
+ operand_1,
+ // ----- Ouputs -----
+ result
+ );
+
+/////////////////////////////////////////////////////
+// Inputs
+/////////////////////////////////////////////////////
+
+input clk_i; // Clock
+input rst_i; // Reset
+input stall_x; // Stall instruction in X stage
+input stall_m; // Stall instruction in M stage
+input [`LM32_WORD_RNG] operand_0; // Muliplicand
+input [`LM32_WORD_RNG] operand_1; // Multiplier
+
+/////////////////////////////////////////////////////
+// Outputs
+/////////////////////////////////////////////////////
+
+output [`LM32_WORD_RNG] result; // Product of multiplication
+wire [`LM32_WORD_RNG] result;
+
+/////////////////////////////////////////////////////
+// Internal nets and registers
+/////////////////////////////////////////////////////
+
+// Divide multiplicands into high and low
+`define HALF_WORD_WIDTH (`LM32_WORD_WIDTH/2)
+`define HALF_WORD_RNG (`HALF_WORD_WIDTH-1):0
+
+// Result = c+d+e = a*b
+reg [`HALF_WORD_RNG] a0, a1, b0, b1;
+reg [`HALF_WORD_RNG] c0, c1;
+reg [`HALF_WORD_RNG] d1, e1;
+reg [`HALF_WORD_RNG] result0, result1;
+
+assign result = {result1, result0};
+
+/////////////////////////////////////////////////////
+// Sequential logic
+/////////////////////////////////////////////////////
+
+always @(posedge clk_i `CFG_RESET_SENSITIVITY)
+begin
+ if (rst_i == `TRUE)
+ begin
+ a0 <= {`HALF_WORD_WIDTH{1'b0}};
+ a1 <= {`HALF_WORD_WIDTH{1'b0}};
+ b0 <= {`HALF_WORD_WIDTH{1'b0}};
+ b1 <= {`HALF_WORD_WIDTH{1'b0}};
+ c0 <= {`HALF_WORD_WIDTH{1'b0}};
+ c1 <= {`HALF_WORD_WIDTH{1'b0}};
+ d1 <= {`HALF_WORD_WIDTH{1'b0}};
+ e1 <= {`HALF_WORD_WIDTH{1'b0}};
+ result0 <= {`HALF_WORD_WIDTH{1'b0}};
+ result1 <= {`HALF_WORD_WIDTH{1'b0}};
+ end
+ else
+ begin
+ if (stall_x == `FALSE)
+ begin
+ {a1, a0} <= operand_0;
+ {b1, b0} <= operand_1;
+ end
+ if (stall_m == `FALSE)
+ begin
+ {c1, c0} <= a0 * b0;
+ d1 <= a0 * b1;
+ e1 <= a1 * b0;
+ end
+
+ result0 <= c0;
+ result1 <= c1 + d1 + e1;
+ end
+end
+
+endmodule
diff --git a/modules/wishbone/wb_simple_pwm/simple_pwm_wb.wb b/modules/wishbone/wb_simple_pwm/simple_pwm_wb.wb
index 0fd713d8..ca0ee14e 100644
--- a/modules/wishbone/wb_simple_pwm/simple_pwm_wb.wb
+++ b/modules/wishbone/wb_simple_pwm/simple_pwm_wb.wb
@@ -5,7 +5,7 @@
-- Project : General Cores Collection
-------------------------------------------------------------------------------
-- File : simple_pwm_wb.wb
--- Author : Tomasz WÅ‚ostowski
+-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-12-10
-- Last update: 2013-01-09
diff --git a/modules/wishbone/wb_simple_timer/Manifest.py b/modules/wishbone/wb_simple_timer/Manifest.py
index ed5a1b24..50eca963 100644
--- a/modules/wishbone/wb_simple_timer/Manifest.py
+++ b/modules/wishbone/wb_simple_timer/Manifest.py
@@ -1 +1 @@
-files = ["wb_tics.vhd", "xwb_tics.vhd"];
\ No newline at end of file
+files = ["wb_tics.vhd", "xwb_tics.vhd"];
diff --git a/modules/wishbone/wb_uart/uart_async_rx.vhd b/modules/wishbone/wb_uart/uart_async_rx.vhd
index cf0a906c..ea996e08 100644
--- a/modules/wishbone/wb_uart/uart_async_rx.vhd
+++ b/modules/wishbone/wb_uart/uart_async_rx.vhd
@@ -1,229 +1,229 @@
-------------------------------------------------------------------------------
--- Title : Simple Wishbone UART - receiver
--- Project : General Cores Collection (gencores) library
-------------------------------------------------------------------------------
--- File : uart_async_rx.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN
--- Platform : FPGA-generic
--- Standard : VHDL'93
--------------------------------------------------------------------------------
--- Copyright (c) 2010 CERN
---
--- This source file is free software; you can redistribute it
--- and/or modify it under the terms of the GNU Lesser General
--- Public License as published by the Free Software Foundation;
--- either version 2.1 of the License, or (at your option) any
--- later version.
---
--- This source is distributed in the hope that it will be
--- useful, but WITHOUT ANY WARRANTY; without even the implied
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
--- PURPOSE. See the GNU Lesser General Public License for more
--- details.
---
--- You should have received a copy of the GNU Lesser General
--- Public License along with this source; if not, download it
--- from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity uart_async_rx is
-
-
- port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
-
- baud8_tick_i: in std_logic;
-
- rxd_i : in std_logic;
- rx_ready_o : out std_logic;
- rx_error_o : out std_logic;
- rx_data_o : out std_logic_vector(7 downto 0)
-
- );
-
-end uart_async_rx;
-
-
-architecture behavioral of uart_async_rx is
-
- signal Baud8Tick : std_logic;
-
- signal RxD_sync_inv : std_logic_vector(1 downto 0);
- signal RxD_cnt_inv : unsigned(1 downto 0);
- signal RxD_bit_inv : std_logic;
-
- signal state : std_logic_vector(3 downto 0);
- signal bit_spacing : std_logic_vector(3 downto 0);
- signal next_bit : std_logic;
-
- signal RxD_data : std_logic_vector(7 downto 0);
- signal RxD_data_ready : std_logic;
- signal RxD_data_error : std_logic;
-
-
-
-begin -- behavioral
-
- Baud8Tick <= baud8_tick_i;
-
-
- process(clk_sys_i, rst_n_i)
- begin
- if rising_edge(clk_sys_i) then
- if rst_n_i = '0' then
- RxD_sync_inv <= (others => '0');
- else
- if(Baud8Tick = '1') then
- RxD_sync_inv <= RxD_sync_inv(0) & (not rxd_i);
- end if;
- end if;
- end if;
- end process;
-
- process(clk_sys_i, rst_n_i)
- begin
- if rising_edge(clk_sys_i) then
- if rst_n_i = '0' then
- RxD_bit_inv <= '0';
- RxD_cnt_inv <= (others => '0');
- else
- if(Baud8Tick = '1') then
- if(RxD_sync_inv(1) = '1' and RxD_cnt_inv /= "11") then
- RxD_cnt_inv <= RxD_cnt_inv + 1;
- elsif (RxD_sync_inv(1) = '0' and RxD_cnt_inv /= "00") then
- RxD_cnt_inv <= RxD_cnt_inv - 1;
- end if;
-
- if(RxD_cnt_inv = "00") then
- RxD_bit_inv <= '0';
- elsif(RxD_cnt_inv = "11") then
- RxD_bit_inv <= '1';
- end if;
- end if;
- end if;
- end if;
- end process;
-
-
- next_bit <= '1' when (bit_spacing = x"a") else '0';
-
- process(clk_sys_i, rst_n_i)
- begin
- if rising_edge(clk_sys_i) then
- if rst_n_i = '0' then
- bit_spacing <= (others => '0');
- else
- if(state = x"0") then
- bit_spacing <= "0000";
- elsif(Baud8Tick = '1') then
--- bit_spacing <= std_logic_vector(resize((unsigned(bit_spacing(2 downto 0)) + 1), 4))
- bit_spacing <= std_logic_vector(unsigned('0' & bit_spacing(2 downto 0)) + 1)
- or (bit_spacing(3) & "000");
- end if;
- end if;
- end if;
- end process;
-
- process(clk_sys_i, rst_n_i)
- begin
- if rising_edge(clk_sys_i) then
- if rst_n_i = '0' then
- state <= (others => '0');
- else
- if(Baud8Tick = '1') then
- case state is
- when "0000" =>
- if(RxD_bit_inv = '1') then -- start bit
- state <= "1000";
- end if;
- when "1000" =>
- if(next_bit = '1') then
- state <= "1001"; -- bit 0
- end if;
- when "1001" =>
- if(next_bit = '1') then
- state <= "1010"; -- bit 1
- end if;
- when "1010" =>
- if(next_bit = '1') then
- state <= "1011"; -- bit 2
- end if;
- when "1011" =>
- if(next_bit = '1') then
- state <= "1100"; -- bit 3
- end if;
- when "1100" =>
- if(next_bit = '1') then
- state <= "1101"; -- bit 4
- end if;
- when "1101" =>
- if(next_bit = '1') then
- state <= "1110"; -- bit 5
- end if;
- when "1110" =>
- if(next_bit = '1') then
- state <= "1111"; -- bit 6
- end if;
- when "1111" =>
- if(next_bit = '1') then
- state <= "0001"; -- bit 7
- end if;
- when "0001" =>
- if(next_bit = '1') then
- state <= "0000"; -- bit stop
- end if;
- when others => state <= "0000";
- end case;
- end if;
- end if;
- end if;
- end process;
-
-
- process(clk_sys_i, rst_n_i)
- begin
- if rising_edge(clk_sys_i) then
- if rst_n_i = '0' then
- RxD_data <= (others => '0');
- else
- if(Baud8Tick = '1' and next_bit = '1' and state(3) = '1') then
- RxD_data <= (not RxD_bit_inv) & RxD_data(7 downto 1);
- end if;
- end if;
- end if;
- end process;
-
- process(clk_sys_i, rst_n_i)
- begin
- if rising_edge(clk_sys_i) then
- if rst_n_i = '0' then
- RxD_data_error <= '0';
- RxD_data_ready <= '0';
- else
- if(Baud8Tick = '1' and next_bit = '1' and state = "0001" and RxD_bit_inv = '0') then
- RxD_data_ready <= '1';
- else
- RxD_data_ready <= '0';
- end if;
-
- if(Baud8Tick = '1' and next_bit = '1' and state = "0001" and RxD_bit_inv = '1') then
- RxD_data_error <= '1';
- else
- RxD_data_error <= '0';
- end if;
- end if;
- end if;
- end process;
-
- rx_data_o <= RxD_data;
- rx_ready_o <= RxD_data_ready;
- rx_error_o <= RxD_data_error;
-
-
-end behavioral;
+------------------------------------------------------------------------------
+-- Title : Simple Wishbone UART - receiver
+-- Project : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File : uart_async_rx.vhd
+-- Author : Tomasz Wlostowski
+-- Company : CERN
+-- Platform : FPGA-generic
+-- Standard : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity uart_async_rx is
+
+
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ baud8_tick_i: in std_logic;
+
+ rxd_i : in std_logic;
+ rx_ready_o : out std_logic;
+ rx_error_o : out std_logic;
+ rx_data_o : out std_logic_vector(7 downto 0)
+
+ );
+
+end uart_async_rx;
+
+
+architecture behavioral of uart_async_rx is
+
+ signal Baud8Tick : std_logic;
+
+ signal RxD_sync_inv : std_logic_vector(1 downto 0);
+ signal RxD_cnt_inv : unsigned(1 downto 0);
+ signal RxD_bit_inv : std_logic;
+
+ signal state : std_logic_vector(3 downto 0);
+ signal bit_spacing : std_logic_vector(3 downto 0);
+ signal next_bit : std_logic;
+
+ signal RxD_data : std_logic_vector(7 downto 0);
+ signal RxD_data_ready : std_logic;
+ signal RxD_data_error : std_logic;
+
+
+
+begin -- behavioral
+
+ Baud8Tick <= baud8_tick_i;
+
+
+ process(clk_sys_i, rst_n_i)
+ begin
+ if rising_edge(clk_sys_i) then
+ if rst_n_i = '0' then
+ RxD_sync_inv <= (others => '0');
+ else
+ if(Baud8Tick = '1') then
+ RxD_sync_inv <= RxD_sync_inv(0) & (not rxd_i);
+ end if;
+ end if;
+ end if;
+ end process;
+
+ process(clk_sys_i, rst_n_i)
+ begin
+ if rising_edge(clk_sys_i) then
+ if rst_n_i = '0' then
+ RxD_bit_inv <= '0';
+ RxD_cnt_inv <= (others => '0');
+ else
+ if(Baud8Tick = '1') then
+ if(RxD_sync_inv(1) = '1' and RxD_cnt_inv /= "11") then
+ RxD_cnt_inv <= RxD_cnt_inv + 1;
+ elsif (RxD_sync_inv(1) = '0' and RxD_cnt_inv /= "00") then
+ RxD_cnt_inv <= RxD_cnt_inv - 1;
+ end if;
+
+ if(RxD_cnt_inv = "00") then
+ RxD_bit_inv <= '0';
+ elsif(RxD_cnt_inv = "11") then
+ RxD_bit_inv <= '1';
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ next_bit <= '1' when (bit_spacing = x"a") else '0';
+
+ process(clk_sys_i, rst_n_i)
+ begin
+ if rising_edge(clk_sys_i) then
+ if rst_n_i = '0' then
+ bit_spacing <= (others => '0');
+ else
+ if(state = x"0") then
+ bit_spacing <= "0000";
+ elsif(Baud8Tick = '1') then
+-- bit_spacing <= std_logic_vector(resize((unsigned(bit_spacing(2 downto 0)) + 1), 4))
+ bit_spacing <= std_logic_vector(unsigned('0' & bit_spacing(2 downto 0)) + 1)
+ or (bit_spacing(3) & "000");
+ end if;
+ end if;
+ end if;
+ end process;
+
+ process(clk_sys_i, rst_n_i)
+ begin
+ if rising_edge(clk_sys_i) then
+ if rst_n_i = '0' then
+ state <= (others => '0');
+ else
+ if(Baud8Tick = '1') then
+ case state is
+ when "0000" =>
+ if(RxD_bit_inv = '1') then -- start bit
+ state <= "1000";
+ end if;
+ when "1000" =>
+ if(next_bit = '1') then
+ state <= "1001"; -- bit 0
+ end if;
+ when "1001" =>
+ if(next_bit = '1') then
+ state <= "1010"; -- bit 1
+ end if;
+ when "1010" =>
+ if(next_bit = '1') then
+ state <= "1011"; -- bit 2
+ end if;
+ when "1011" =>
+ if(next_bit = '1') then
+ state <= "1100"; -- bit 3
+ end if;
+ when "1100" =>
+ if(next_bit = '1') then
+ state <= "1101"; -- bit 4
+ end if;
+ when "1101" =>
+ if(next_bit = '1') then
+ state <= "1110"; -- bit 5
+ end if;
+ when "1110" =>
+ if(next_bit = '1') then
+ state <= "1111"; -- bit 6
+ end if;
+ when "1111" =>
+ if(next_bit = '1') then
+ state <= "0001"; -- bit 7
+ end if;
+ when "0001" =>
+ if(next_bit = '1') then
+ state <= "0000"; -- bit stop
+ end if;
+ when others => state <= "0000";
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ process(clk_sys_i, rst_n_i)
+ begin
+ if rising_edge(clk_sys_i) then
+ if rst_n_i = '0' then
+ RxD_data <= (others => '0');
+ else
+ if(Baud8Tick = '1' and next_bit = '1' and state(3) = '1') then
+ RxD_data <= (not RxD_bit_inv) & RxD_data(7 downto 1);
+ end if;
+ end if;
+ end if;
+ end process;
+
+ process(clk_sys_i, rst_n_i)
+ begin
+ if rising_edge(clk_sys_i) then
+ if rst_n_i = '0' then
+ RxD_data_error <= '0';
+ RxD_data_ready <= '0';
+ else
+ if(Baud8Tick = '1' and next_bit = '1' and state = "0001" and RxD_bit_inv = '0') then
+ RxD_data_ready <= '1';
+ else
+ RxD_data_ready <= '0';
+ end if;
+
+ if(Baud8Tick = '1' and next_bit = '1' and state = "0001" and RxD_bit_inv = '1') then
+ RxD_data_error <= '1';
+ else
+ RxD_data_error <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ rx_data_o <= RxD_data;
+ rx_ready_o <= RxD_data_ready;
+ rx_error_o <= RxD_data_error;
+
+
+end behavioral;
diff --git a/modules/wishbone/wbgen2/wbgen2_dpssram.vhd b/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
index a2842d8c..ff98f1ac 100644
--- a/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
@@ -11,13 +11,13 @@
-- Copyright (c) 2011 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
+-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
diff --git a/modules/wishbone/wbgen2/wbgen2_eic.vhd b/modules/wishbone/wbgen2/wbgen2_eic.vhd
index 127a29f4..d3cd3530 100644
--- a/modules/wishbone/wbgen2/wbgen2_eic.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_eic.vhd
@@ -11,13 +11,13 @@
-- Copyright (c) 2011 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
+-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
diff --git a/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd b/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
index 606514ce..388fa021 100644
--- a/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
@@ -11,13 +11,13 @@
-- Copyright (c) 2011 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
+-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
diff --git a/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd b/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
index da72760c..e26d86fc 100644
--- a/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
@@ -11,13 +11,13 @@
-- Copyright (c) 2011 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
+-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
diff --git a/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd b/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
index 851dcdb3..16066d85 100644
--- a/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
+++ b/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
@@ -3,7 +3,7 @@
-- Project : General Cores Library
-------------------------------------------------------------------------------
-- File : wb_xilinx_fpga_loader.vhd
--- Author : Tomasz WÅ‚ostowski
+-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-30
-- Last update : 2012-01-30
diff --git a/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.wb b/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.wb
index 278f65fd..a5ef4df9 100644
--- a/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.wb
+++ b/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.wb
@@ -5,7 +5,7 @@
-- Project : General Cores Library
-------------------------------------------------------------------------------
-- File : xloader_wb.wb
--- Author : Tomasz WÅ‚ostowski
+-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-30
-- Last update : 2012-01-30
diff --git a/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd b/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
index c4db01b8..b4e66e05 100644
--- a/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
+++ b/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
@@ -3,7 +3,7 @@
-- Project : General Cores Library
-------------------------------------------------------------------------------
-- File : xwb_xilinx_fpga_loader.vhd
--- Author : Tomasz WÅ‚ostowski
+-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-30
-- Last update : 2012-01-30
diff --git a/testbench/wishbone/lm32_testsys/sw/target/lm32/crt0.S b/testbench/wishbone/lm32_testsys/sw/target/lm32/crt0.S
index de7de225..eca38268 100755
--- a/testbench/wishbone/lm32_testsys/sw/target/lm32/crt0.S
+++ b/testbench/wishbone/lm32_testsys/sw/target/lm32/crt0.S
@@ -1,138 +1,138 @@
-/****************************************************************************
-**
-** Name: crt0ram.S
-**
-** Description:
-** Implements boot-code that calls LatticeDDInit (that calls main())
-** Implements exception handlers (actually, redirectors)
-**
-** $Revision: $
-**
-** Disclaimer:
-**
-** This source code is intended as a design reference which
-** illustrates how these types of functions can be implemented. It
-** is the user's responsibility to verify their design for
-** consistency and functionality through the use of formal
-** verification methods. Lattice Semiconductor provides no warranty
-** regarding the use or functionality of this code.
-**
-** --------------------------------------------------------------------
-**
-** Lattice Semiconductor Corporation
-** 5555 NE Moore Court
-** Hillsboro, OR 97214
-** U.S.A
-**
-** TEL: 1-800-Lattice (USA and Canada)
-** (503)268-8001 (other locations)
-**
-** web: http://www.latticesemi.com
-** email: techsupport@latticesemi.com
-**
-** --------------------------------------------------------------------------
-**
-** Change History (Latest changes on top)
-**
-** Ver Date Description
-** --------------------------------------------------------------------------
-** 3.8 Apr-15-2011 Added __MICO_USER_<handler>_HANDLER__ preprocessor to
-** allow customers to implement their own handlers for:
-** DATA_ABORT, INST_ABORT
-**
-** 3.1 Jun-18-2008 Added __MICO_NO_INTERRUPTS__ preprocessor
-** option to exclude invoking MicoISRHandler
-** to reduce code-size in apps that don't use
-** interrupts
-**
-** 3.0 Mar-25-2008 Added Header
-**
-**---------------------------------------------------------------------------
-*****************************************************************************/
-
-/*
- * LatticeMico32 C startup code.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/* From include/sys/signal.h */
-#define SIGINT 2 /* interrupt */
-#define SIGTRAP 5 /* trace trap */
-#define SIGFPE 8 /* arithmetic exception */
-#define SIGSEGV 11 /* segmentation violation */
+/****************************************************************************
+**
+** Name: crt0ram.S
+**
+** Description:
+** Implements boot-code that calls LatticeDDInit (that calls main())
+** Implements exception handlers (actually, redirectors)
+**
+** $Revision: $
+**
+** Disclaimer:
+**
+** This source code is intended as a design reference which
+** illustrates how these types of functions can be implemented. It
+** is the user's responsibility to verify their design for
+** consistency and functionality through the use of formal
+** verification methods. Lattice Semiconductor provides no warranty
+** regarding the use or functionality of this code.
+**
+** --------------------------------------------------------------------
+**
+** Lattice Semiconductor Corporation
+** 5555 NE Moore Court
+** Hillsboro, OR 97214
+** U.S.A
+**
+** TEL: 1-800-Lattice (USA and Canada)
+** (503)268-8001 (other locations)
+**
+** web: http://www.latticesemi.com
+** email: techsupport@latticesemi.com
+**
+** --------------------------------------------------------------------------
+**
+** Change History (Latest changes on top)
+**
+** Ver Date Description
+** --------------------------------------------------------------------------
+** 3.8 Apr-15-2011 Added __MICO_USER_<handler>_HANDLER__ preprocessor to
+** allow customers to implement their own handlers for:
+** DATA_ABORT, INST_ABORT
+**
+** 3.1 Jun-18-2008 Added __MICO_NO_INTERRUPTS__ preprocessor
+** option to exclude invoking MicoISRHandler
+** to reduce code-size in apps that don't use
+** interrupts
+**
+** 3.0 Mar-25-2008 Added Header
+**
+**---------------------------------------------------------------------------
+*****************************************************************************/
-//#define MICO32_FULL_CONTEXT_SAVE_RESTORE
+/*
+ * LatticeMico32 C startup code.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
-
-/* Exception handlers - Must be 32 bytes long. */
- .section .boot, "ax", @progbits
-
- .global _start
-_start:
-
- .global _reset_handler
- .type _reset_handler, @function
-_reset_handler:
- xor r0, r0, r0
- wcsr IE, r0
- wcsr IM, r0
- mvhi r1, hi(_reset_handler)
- ori r1, r1, lo(_reset_handler)
- wcsr EBA, r1
- calli _crt0
- nop
- .size _reset_handler, .-_reset_handler
-
+/* From include/sys/signal.h */
+#define SIGINT 2 /* interrupt */
+#define SIGTRAP 5 /* trace trap */
+#define SIGFPE 8 /* arithmetic exception */
+#define SIGSEGV 11 /* segmentation violation */
+
+//#define MICO32_FULL_CONTEXT_SAVE_RESTORE
+
+
+/* Exception handlers - Must be 32 bytes long. */
+ .section .boot, "ax", @progbits
+
+ .global _start
+_start:
+
+ .global _reset_handler
+ .type _reset_handler, @function
+_reset_handler:
+ xor r0, r0, r0
+ wcsr IE, r0
+ wcsr IM, r0
+ mvhi r1, hi(_reset_handler)
+ ori r1, r1, lo(_reset_handler)
+ wcsr EBA, r1
+ calli _crt0
+ nop
+ .size _reset_handler, .-_reset_handler
+
.extern _irq_entry
.org 0xc0
- .global _interrupt_handler
- .type _interrupt_handler, @function
-_interrupt_handler:
- sw (sp+0), ra
- calli _save_all
- mvi r1, SIGINT
-#ifndef __MICO_NO_INTERRUPTS__
+ .global _interrupt_handler
+ .type _interrupt_handler, @function
+_interrupt_handler:
+ sw (sp+0), ra
+ calli _save_all
+ mvi r1, SIGINT
+#ifndef __MICO_NO_INTERRUPTS__
calli _irq_entry
-#else
- wcsr IE, r0
-#endif
- bi _restore_all_and_return
- nop
- nop
- nop
+#else
+ wcsr IE, r0
+#endif
+ bi _restore_all_and_return
+ nop
+ nop
+ nop
.org 0x100
- .global _crt0
- .type _crt0, @function
-_crt0:
- /* Clear r0 */
- xor r0, r0, r0
- /* Setup stack and global pointer */
- mvhi sp, hi(_fstack)
- ori sp, sp, lo(_fstack)
- mvhi gp, hi(_gp)
- ori gp, gp, lo(_gp)
-
+ .global _crt0
+ .type _crt0, @function
+_crt0:
+ /* Clear r0 */
+ xor r0, r0, r0
+ /* Setup stack and global pointer */
+ mvhi sp, hi(_fstack)
+ ori sp, sp, lo(_fstack)
+ mvhi gp, hi(_gp)
+ ori gp, gp, lo(_gp)
+
mvhi r1, hi(_fbss)
ori r1, r1, lo(_fbss)
mvi r2, 0
@@ -140,120 +140,120 @@ _crt0:
ori r3, r3, lo(_ebss)
sub r3, r3, r1
calli memset
- mvi r1, 0
- mvi r2, 0
- mvi r3, 0
+ mvi r1, 0
+ mvi r2, 0
+ mvi r3, 0
calli main
loopf:
bi loopf
- .global _save_all
- .type _save_all, @function
-_save_all:
-#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
- addi sp, sp, -128
-#else
- addi sp, sp, -60
-#endif
- sw (sp+4), r1
- sw (sp+8), r2
- sw (sp+12), r3
- sw (sp+16), r4
- sw (sp+20), r5
- sw (sp+24), r6
- sw (sp+28), r7
- sw (sp+32), r8
- sw (sp+36), r9
- sw (sp+40), r10
-#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
- sw (sp+44), r11
- sw (sp+48), r12
- sw (sp+52), r13
- sw (sp+56), r14
- sw (sp+60), r15
- sw (sp+64), r16
- sw (sp+68), r17
- sw (sp+72), r18
- sw (sp+76), r19
- sw (sp+80), r20
- sw (sp+84), r21
- sw (sp+88), r22
- sw (sp+92), r23
- sw (sp+96), r24
- sw (sp+100), r25
- sw (sp+104), r26
- sw (sp+108), r27
- sw (sp+120), ea
- sw (sp+124), ba
- /* ra and sp need special handling, as they have been modified */
- lw r1, (sp+128)
- sw (sp+116), r1
- mv r1, sp
- addi r1, r1, 128
- sw (sp+112), r1
-#else
- sw (sp+52), ea
- sw (sp+56), ba
- /* ra and sp need special handling, as they have been modified */
- lw r1, (sp+60)
- sw (sp+48), r1
- mv r1, sp
- addi r1, r1, 60
- sw (sp+44), r1
-#endif
-// xor r1, r1, r1
-// wcsr ie, r1
- ret
- .size _save_all, .-_save_all
-
- .global _restore_all_and_return
- .type _restore_all_and_return, @function
- /* Restore all registers and return from exception */
-_restore_all_and_return:
-// addi r1, r0, 2
-// wcsr ie, r1
- lw r1, (sp+4)
- lw r2, (sp+8)
- lw r3, (sp+12)
- lw r4, (sp+16)
- lw r5, (sp+20)
- lw r6, (sp+24)
- lw r7, (sp+28)
- lw r8, (sp+32)
- lw r9, (sp+36)
- lw r10, (sp+40)
-#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
- lw r11, (sp+44)
- lw r12, (sp+48)
- lw r13, (sp+52)
- lw r14, (sp+56)
- lw r15, (sp+60)
- lw r16, (sp+64)
- lw r17, (sp+68)
- lw r18, (sp+72)
- lw r19, (sp+76)
- lw r20, (sp+80)
- lw r21, (sp+84)
- lw r22, (sp+88)
- lw r23, (sp+92)
- lw r24, (sp+96)
- lw r25, (sp+100)
- lw r26, (sp+104)
- lw r27, (sp+108)
- lw ra, (sp+116)
- lw ea, (sp+120)
- lw ba, (sp+124)
- /* Stack pointer must be restored last, in case it has been updated */
- lw sp, (sp+112)
-#else
- lw ra, (sp+48)
- lw ea, (sp+52)
- lw ba, (sp+56)
- /* Stack pointer must be restored last, in case it has been updated */
- lw sp, (sp+44)
-#endif
- nop
- eret
- .size _restore_all_and_return, .-_restore_all_and_return
-
+ .global _save_all
+ .type _save_all, @function
+_save_all:
+#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
+ addi sp, sp, -128
+#else
+ addi sp, sp, -60
+#endif
+ sw (sp+4), r1
+ sw (sp+8), r2
+ sw (sp+12), r3
+ sw (sp+16), r4
+ sw (sp+20), r5
+ sw (sp+24), r6
+ sw (sp+28), r7
+ sw (sp+32), r8
+ sw (sp+36), r9
+ sw (sp+40), r10
+#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
+ sw (sp+44), r11
+ sw (sp+48), r12
+ sw (sp+52), r13
+ sw (sp+56), r14
+ sw (sp+60), r15
+ sw (sp+64), r16
+ sw (sp+68), r17
+ sw (sp+72), r18
+ sw (sp+76), r19
+ sw (sp+80), r20
+ sw (sp+84), r21
+ sw (sp+88), r22
+ sw (sp+92), r23
+ sw (sp+96), r24
+ sw (sp+100), r25
+ sw (sp+104), r26
+ sw (sp+108), r27
+ sw (sp+120), ea
+ sw (sp+124), ba
+ /* ra and sp need special handling, as they have been modified */
+ lw r1, (sp+128)
+ sw (sp+116), r1
+ mv r1, sp
+ addi r1, r1, 128
+ sw (sp+112), r1
+#else
+ sw (sp+52), ea
+ sw (sp+56), ba
+ /* ra and sp need special handling, as they have been modified */
+ lw r1, (sp+60)
+ sw (sp+48), r1
+ mv r1, sp
+ addi r1, r1, 60
+ sw (sp+44), r1
+#endif
+// xor r1, r1, r1
+// wcsr ie, r1
+ ret
+ .size _save_all, .-_save_all
+
+ .global _restore_all_and_return
+ .type _restore_all_and_return, @function
+ /* Restore all registers and return from exception */
+_restore_all_and_return:
+// addi r1, r0, 2
+// wcsr ie, r1
+ lw r1, (sp+4)
+ lw r2, (sp+8)
+ lw r3, (sp+12)
+ lw r4, (sp+16)
+ lw r5, (sp+20)
+ lw r6, (sp+24)
+ lw r7, (sp+28)
+ lw r8, (sp+32)
+ lw r9, (sp+36)
+ lw r10, (sp+40)
+#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
+ lw r11, (sp+44)
+ lw r12, (sp+48)
+ lw r13, (sp+52)
+ lw r14, (sp+56)
+ lw r15, (sp+60)
+ lw r16, (sp+64)
+ lw r17, (sp+68)
+ lw r18, (sp+72)
+ lw r19, (sp+76)
+ lw r20, (sp+80)
+ lw r21, (sp+84)
+ lw r22, (sp+88)
+ lw r23, (sp+92)
+ lw r24, (sp+96)
+ lw r25, (sp+100)
+ lw r26, (sp+104)
+ lw r27, (sp+108)
+ lw ra, (sp+116)
+ lw ea, (sp+120)
+ lw ba, (sp+124)
+ /* Stack pointer must be restored last, in case it has been updated */
+ lw sp, (sp+112)
+#else
+ lw ra, (sp+48)
+ lw ea, (sp+52)
+ lw ba, (sp+56)
+ /* Stack pointer must be restored last, in case it has been updated */
+ lw sp, (sp+44)
+#endif
+ nop
+ eret
+ .size _restore_all_and_return, .-_restore_all_and_return
+
--
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