From f9cf7649f7707527d1edecb5c0ac730f2a5ce04a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tomasz=20W=C5=82ostowski?= <tomasz.wlostowski@cern.ch>
Date: Tue, 13 Mar 2012 09:52:58 +0100
Subject: [PATCH] modules/wishbone/wbgen2: added reset lines to wbgen2 FIFOs
---
modules/wishbone/wbgen2/wbgen2_fifo_async.vhd | 10 ++++++----
modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd | 5 ++++-
modules/wishbone/wbgen2/wbgen2_pkg.vhd | 4 +++-
3 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd b/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
index 59357942..3fda6af6 100644
--- a/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
@@ -13,6 +13,8 @@ entity wbgen2_fifo_async is
port
(
+ rst_n_i : in std_logic := '1';
+
rd_clk_i : in std_logic;
rd_req_i : in std_logic;
rd_data_o : out std_logic_vector(g_width-1 downto 0);
@@ -29,7 +31,7 @@ entity wbgen2_fifo_async is
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0)
- );
+ );
end wbgen2_fifo_async;
architecture rtl of wbgen2_fifo_async is
@@ -73,7 +75,7 @@ architecture rtl of wbgen2_fifo_async is
begin
- wrapped_fifo: generic_async_fifo
+ wrapped_fifo : generic_async_fifo
generic map (
g_data_width => g_width,
g_size => g_size,
@@ -91,7 +93,7 @@ begin
g_almost_empty_threshold => 0,
g_almost_full_threshold => 0)
port map (
- rst_n_i => '1',
+ rst_n_i => rst_n_i,
clk_wr_i => wr_clk_i,
d_i => wr_data_i,
we_i => wr_req_i,
@@ -108,5 +110,5 @@ begin
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => rd_usedw_o);
-
+
end rtl;
diff --git a/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd b/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
index 1641280e..8b098506 100644
--- a/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
@@ -13,7 +13,10 @@ entity wbgen2_fifo_sync is
port
(
+
clk_i : in std_logic;
+ rst_n_i : in std_logic := '1';
+
wr_data_i : in std_logic_vector(g_width-1 downto 0);
wr_req_i : in std_logic;
@@ -88,7 +91,7 @@ begin
g_with_almost_full => false,
g_with_count => true)
port map (
- rst_n_i => '1',
+ rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => wr_data_i,
we_i => wr_req_i,
diff --git a/modules/wishbone/wbgen2/wbgen2_pkg.vhd b/modules/wishbone/wbgen2/wbgen2_pkg.vhd
index 02699195..18dc0a47 100644
--- a/modules/wishbone/wbgen2/wbgen2_pkg.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_pkg.vhd
@@ -28,7 +28,7 @@ package wbgen2_pkg is
wr_b_i : in std_logic);
end component;
-
+
component wbgen2_eic
generic (
g_num_interrupts : natural;
@@ -86,6 +86,7 @@ package wbgen2_pkg is
g_width : integer;
g_usedw_size : integer);
port (
+ rst_n_i : in std_logic := '1';
rd_clk_i : in std_logic;
rd_req_i : in std_logic;
rd_data_o : out std_logic_vector(g_width-1 downto 0);
@@ -108,6 +109,7 @@ package wbgen2_pkg is
g_usedw_size : integer);
port (
clk_i : in std_logic;
+ rst_n_i : in std_logic := '1';
wr_data_i : in std_logic_vector(g_width-1 downto 0);
wr_req_i : in std_logic;
rd_data_o : out std_logic_vector(g_width-1 downto 0);
--
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