From f35ba5efe43dba18233de620d8129c42a64ba9ea Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tomasz=20W=C5=82ostowski?= <tomasz.wlostowski@cern.ch>
Date: Tue, 31 Oct 2017 11:14:44 +0100
Subject: [PATCH] axi4: add 512-bit data width AXI4-full record, fixed
compilation issue in axi->wb bridge
---
.../wishbone/wb_axi4lite_bridge/axi4_pkg.vhd | 47 ++++++++++++++++++-
.../xwb_axi4lite_bridge.vhd | 2 +-
2 files changed, 46 insertions(+), 3 deletions(-)
diff --git a/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd b/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
index 8f73de85..8dbbbec2 100644
--- a/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
@@ -134,6 +134,50 @@ package axi4_pkg is
wb_master_i : in t_wishbone_master_in);
end component xwb_axi4lite_bridge;
+ -- AXI4-Full interface, master output ports, 512 bits
+ type t_axi4_full_master_out_512 is record
+ ARVALID : std_logic;
+ AWVALID : std_logic;
+ BREADY : std_logic;
+ RREADY : std_logic;
+ WLAST : std_logic;
+ WVALID : std_logic;
+ ARID : std_logic_vector (11 downto 0);
+ AWID : std_logic_vector (11 downto 0);
+ ARBURST : std_logic_vector (1 downto 0);
+ ARLOCK : std_logic;
+ ARSIZE : std_logic_vector (2 downto 0);
+ AWBURST : std_logic_vector (1 downto 0);
+ AWLOCK : std_logic;
+ AWSIZE : std_logic_vector (2 downto 0);
+ ARPROT : std_logic_vector (2 downto 0);
+ AWPROT : std_logic_vector (2 downto 0);
+ ARADDR : std_logic_vector (31 downto 0);
+ AWADDR : std_logic_vector (31 downto 0);
+ WDATA : std_logic_vector (511 downto 0);
+ ARCACHE : std_logic_vector (3 downto 0);
+ ARLEN : std_logic_vector (7 downto 0);
+ ARQOS : std_logic_vector (3 downto 0);
+ AWCACHE : std_logic_vector (3 downto 0);
+ AWLEN : std_logic_vector (7 downto 0);
+ AWQOS : std_logic_vector (3 downto 0);
+ WSTRB : std_logic_vector (31 downto 0);
+ end record;
+
+ -- AXI4-Full interface, master input ports, 512 bits
+ type t_axi4_full_master_in_512 is record
+ ARREADY : std_logic;
+ AWREADY : std_logic;
+ BVALID : std_logic;
+ RLAST : std_logic;
+ RVALID : std_logic;
+ WREADY : std_logic;
+ BID : std_logic_vector (11 downto 0);
+ RID : std_logic_vector (11 downto 0);
+ BRESP : std_logic_vector (1 downto 0);
+ RRESP : std_logic_vector (1 downto 0);
+ RDATA : std_logic_vector (511 downto 0);
+ end record;
end package;
package body axi4_pkg is
@@ -177,8 +221,7 @@ package body axi4_pkg is
f.RDATA := l.RDATA;
return f;
-
- end f_axi4_lite_to_full;
+ end f_axi4_lite_to_full;
end package body;
diff --git a/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd b/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
index bf5bd3d9..c25f33f8 100644
--- a/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
@@ -155,7 +155,7 @@ begin
state <= IDLE;
end if;
- when RESPONSE_READ => null;
+ when RESPONSE_READ =>
if (axi4_slave_i.RREADY = '1') then
axi4_slave_o.RVALID <= '0';
state <= IDLE;
--
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