diff --git a/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd b/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
index 8f73de85c5b060fd3a31ceb8f272fdc26aa40ff3..8dbbbec2d5f038b365fce8791612677a786e5a55 100644
--- a/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
@@ -134,6 +134,50 @@ package axi4_pkg is
       wb_master_i  : in  t_wishbone_master_in);
   end component xwb_axi4lite_bridge;
   
+  -- AXI4-Full interface, master output ports, 512 bits
+  type t_axi4_full_master_out_512 is record
+    ARVALID : std_logic;
+    AWVALID : std_logic;
+    BREADY  : std_logic;
+    RREADY  : std_logic;
+    WLAST   : std_logic;
+    WVALID  : std_logic;
+    ARID    : std_logic_vector (11 downto 0);
+    AWID    : std_logic_vector (11 downto 0);
+    ARBURST : std_logic_vector (1 downto 0);
+    ARLOCK  : std_logic;
+    ARSIZE  : std_logic_vector (2 downto 0);
+    AWBURST : std_logic_vector (1 downto 0);
+    AWLOCK  : std_logic;
+    AWSIZE  : std_logic_vector (2 downto 0);
+    ARPROT  : std_logic_vector (2 downto 0);
+    AWPROT  : std_logic_vector (2 downto 0);
+    ARADDR  : std_logic_vector (31 downto 0);
+    AWADDR  : std_logic_vector (31 downto 0);
+    WDATA   : std_logic_vector (511 downto 0);
+    ARCACHE : std_logic_vector (3 downto 0);
+    ARLEN   : std_logic_vector (7 downto 0);
+    ARQOS   : std_logic_vector (3 downto 0);
+    AWCACHE : std_logic_vector (3 downto 0);
+    AWLEN   : std_logic_vector (7 downto 0);
+    AWQOS   : std_logic_vector (3 downto 0);
+    WSTRB   : std_logic_vector (31 downto 0);
+  end record;
+
+  -- AXI4-Full interface, master input ports, 512 bits
+  type t_axi4_full_master_in_512 is record
+    ARREADY : std_logic;
+    AWREADY : std_logic;
+    BVALID  : std_logic;
+    RLAST   : std_logic;
+    RVALID  : std_logic;
+    WREADY  : std_logic;
+    BID     : std_logic_vector (11 downto 0);
+    RID     : std_logic_vector (11 downto 0);
+    BRESP   : std_logic_vector (1 downto 0);
+    RRESP   : std_logic_vector (1 downto 0);
+    RDATA   : std_logic_vector (511 downto 0);
+  end record;
 end package;
 
 package body axi4_pkg is
@@ -177,8 +221,7 @@ package body axi4_pkg is
     f.RDATA   := l.RDATA;
 
     return f;
-    
-  end f_axi4_lite_to_full;
 
+  end f_axi4_lite_to_full;
 
 end package body;
diff --git a/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd b/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
index bf5bd3d9f5e97e7ca756b1643806d2a7cf6d69ec..c25f33f8413e880d77d4ba63ff3ec88534adb419 100644
--- a/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
@@ -155,7 +155,7 @@ begin
               state               <= IDLE;
             end if;
 
-          when RESPONSE_READ => null;
+          when RESPONSE_READ =>
             if (axi4_slave_i.RREADY = '1') then
               axi4_slave_o.RVALID <= '0';
               state               <= IDLE;