diff --git a/modules/wishbone/wb_lm32/platform/xilinx/jtag_tap.v b/modules/wishbone/wb_lm32/platform/xilinx/jtag_tap.v
index 10a347ad8dba47d103d23dd530724d742a8cabc3..30641168af18aeb31df0062325a08a7e61693837 100644
--- a/modules/wishbone/wb_lm32/platform/xilinx/jtag_tap.v
+++ b/modules/wishbone/wb_lm32/platform/xilinx/jtag_tap.v
@@ -12,6 +12,7 @@ module jtag_tap(
 
 // Unfortunately the exit1 state for DR (e1dr) is mising
 // We can simulate it by interpretting 'update' as e1dr and delaying 'update'
+wire sel;
 wire g_capture;
 wire g_shift;
 wire g_update;