diff --git a/modules/wishbone/wb_virtual_uart/manifest.py b/modules/wishbone/wb_virtual_uart/manifest.py
deleted file mode 100644
index 9c9fdb422743c116ca5658477060e7945627142c..0000000000000000000000000000000000000000
--- a/modules/wishbone/wb_virtual_uart/manifest.py
+++ /dev/null
@@ -1,2 +0,0 @@
-files = ["wb_virtual_uart.vhd",
- "wb_virtual_uart_slave.vhd" ];
diff --git a/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd b/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd
deleted file mode 100644
index ee63b39353d9a361eed78a039e4aaae4f8c4c82f..0000000000000000000000000000000000000000
--- a/modules/wishbone/wb_virtual_uart/wb_virtual_uart.vhd
+++ /dev/null
@@ -1,92 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity wb_virtual_uart is
- port(
- rst_n_i : in std_logic;
- clk_sys_i : in std_logic;
- wb_addr_i : in std_logic_vector(2 downto 0);
- wb_data_i : in std_logic_vector(31 downto 0);
- wb_data_o : out std_logic_vector(31 downto 0);
- wb_cyc_i : in std_logic;
- wb_sel_i : in std_logic_vector(3 downto 0);
- wb_stb_i : in std_logic;
- wb_we_i : in std_logic;
- wb_ack_o : out std_logic
- );
-end wb_virtual_uart;
-
-architecture struct of wb_virtual_uart is
-
- component wb_virtual_uart_slave
- port (
- rst_n_i : in std_logic;
- wb_clk_i : in std_logic;
- wb_addr_i : in std_logic_vector(2 downto 0);
- wb_data_i : in std_logic_vector(31 downto 0);
- wb_data_o : out std_logic_vector(31 downto 0);
- wb_cyc_i : in std_logic;
- wb_sel_i : in std_logic_vector(3 downto 0);
- wb_stb_i : in std_logic;
- wb_we_i : in std_logic;
- wb_ack_o : out std_logic;
- uart_sr_tx_busy_i : in std_logic;
- uart_sr_rx_rdy_i : in std_logic;
- uart_bcr_o : out std_logic_vector(31 downto 0);
- uart_tdr_tx_data_o : out std_logic_vector(7 downto 0);
- uart_tdr_tx_data_i : in std_logic_vector(7 downto 0);
- uart_tdr_tx_data_load_o : out std_logic;
- uart_rdr_rx_data_i : in std_logic_vector(7 downto 0);
- rdr_rack_o : out std_logic;
- uart_debug_wr_req_i : in std_logic;
- uart_debug_wr_full_o : out std_logic;
- uart_debug_wr_empty_o : out std_logic;
- uart_debug_wr_usedw_o : out std_logic_vector(10 downto 0);
- uart_debug_tx_i : in std_logic_vector(7 downto 0);
- uart_debug_dupa_i : in std_logic_vector(31 downto 0));
- end component;
-
-
- signal tx_data : std_logic_vector(7 downto 0);
- signal tx_data_load : std_logic;
- signal tdr_load : std_logic;
- signal fifo_full : std_logic;
-
-begin
-
- tx_data_load <= (not fifo_full) and tdr_load;
-
- WB_SLAVE: wb_virtual_uart_slave
- port map(
- rst_n_i => rst_n_i,
- wb_clk_i => clk_sys_i,
- wb_addr_i => wb_addr_i,
- wb_data_i => wb_data_i,
- wb_data_o => wb_data_o,
- wb_cyc_i => wb_cyc_i,
- wb_sel_i => wb_sel_i,
- wb_stb_i => wb_stb_i,
- wb_we_i => wb_we_i,
- wb_ack_o => wb_ack_o,
- uart_sr_tx_busy_i => '0',
- uart_sr_rx_rdy_i => '0',
- uart_bcr_o => open,
- uart_tdr_tx_data_o => tx_data,
- uart_tdr_tx_data_i => x"00",
- uart_tdr_tx_data_load_o => tdr_load,
- uart_rdr_rx_data_i => x"00",
- rdr_rack_o => open,
- -- FIFO write request
- uart_debug_wr_req_i => tx_data_load,
- -- FIFO full flag
- uart_debug_wr_full_o => fifo_full,
- -- FIFO empty flag
- uart_debug_wr_empty_o => open,
- -- FIFO number of used words
- uart_debug_wr_usedw_o => open,
- uart_debug_tx_i => tx_data,
- uart_debug_dupa_i => x"00000000"
- );
-
-
-end struct;
diff --git a/modules/wishbone/wb_virtual_uart/wb_virtual_uart.wb b/modules/wishbone/wb_virtual_uart/wb_virtual_uart.wb
deleted file mode 100644
index eb7fffa9910ffd1acd2356211e969f88ea5baf26..0000000000000000000000000000000000000000
--- a/modules/wishbone/wb_virtual_uart/wb_virtual_uart.wb
+++ /dev/null
@@ -1,105 +0,0 @@
--- -*- Mode: LUA; tab-width: 2 -*-
-
-peripheral {
- name = "Virtual UART";
- description = "A simple Wishbone FIFO that acts as UART";
- prefix = "UART";
- hdl_entity = "wb_virtual_uart_slave";
-
- reg {
- name = "Status Register";
- prefix = "SR";
-
- field {
- name = "TX busy";
- description = "1: UART is busy transmitting a byte\n0: UART is idle and ready to transmit next byte";
- prefix = "TX_BUSY";
- type = BIT;
- access_bus = READ_ONLY;
- access_dev = WRITE_ONLY;
- };
-
- field {
- name = "RX ready";
- description = "1: UART received a byte and its in RXD register\n0: no data in RXD register";
-
- prefix = "RX_RDY";
- type = BIT;
- access_bus = READ_ONLY;
- access_dev = WRITE_ONLY;
- };
-
- };
-
- reg {
- name = "Baudrate control register";
- description = "Register controlling the UART baudrate";
- prefix = "BCR";
-
- field {
- name = "Baudrate divider setting";
- description = "Baudrate setting. The value can be calculated using the following equation:\
- BRATE = ((Baudrate * 8) << 9 + (ClockFreq >> 8)) / (ClockFreq >> 7)";
- size = 32;
- type = SLV;
- access_bus = READ_WRITE;
- access_dev = READ_ONLY;
- };
- };
-
- reg {
- name = "Transmit data regsiter";
- prefix = "TDR";
-
- field {
- name = "Transmit data";
- prefix = "TX_DATA";
- size = 8;
- type = SLV;
- access_bus = READ_WRITE;
- access_dev = READ_WRITE;
- load = LOAD_EXT;
- };
- };
-
- reg {
- name = "Receive data regsiter";
- prefix = "RDR";
-
-
- field {
- ack_read = "rdr_rack_o";
- name = "Received data";
- prefix = "RX_DATA";
- size = 8;
- type = SLV;
- access_bus = READ_ONLY;
- access_dev = WRITE_ONLY;
- };
- };
-
- fifo_reg {
- size = 2048;
- direction = CORE_TO_BUS;
- prefix = "debug";
- name = "UART TX FIFO";
- description = "This FIFO holds the TX chars that UART tries to send away";
- flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
- flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
-
- field {
- name = "Char sent by UART to TX";
- prefix = "tx";
- type = SLV;
- size = 8;
- };
-
- field {
- name = "Dupa";
- prefix = "dupa";
- type = SLV;
- size = 32;
- };
-
- };
-};
diff --git a/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd b/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd
deleted file mode 100644
index 74534dbc40868a96eb12b1aa448ed774be234abb..0000000000000000000000000000000000000000
--- a/modules/wishbone/wb_virtual_uart/wb_virtual_uart_slave.vhd
+++ /dev/null
@@ -1,352 +0,0 @@
----------------------------------------------------------------------------------------
--- Title : Wishbone slave core for Virtual UART
----------------------------------------------------------------------------------------
--- File : wb_virtual_uart_slave.vhd
--- Author : auto-generated by wbgen2 from wb_virtual_uart.wb
--- Created : Sun Apr 10 20:25:49 2011
--- Standard : VHDL'87
----------------------------------------------------------------------------------------
--- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_virtual_uart.wb
--- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
----------------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.wbgen2_pkg.all;
-
-entity wb_virtual_uart_slave is
- port (
- rst_n_i : in std_logic;
- wb_clk_i : in std_logic;
- wb_addr_i : in std_logic_vector(2 downto 0);
- wb_data_i : in std_logic_vector(31 downto 0);
- wb_data_o : out std_logic_vector(31 downto 0);
- wb_cyc_i : in std_logic;
- wb_sel_i : in std_logic_vector(3 downto 0);
- wb_stb_i : in std_logic;
- wb_we_i : in std_logic;
- wb_ack_o : out std_logic;
--- Port for BIT field: 'TX busy' in reg: 'Status Register'
- uart_sr_tx_busy_i : in std_logic;
--- Port for BIT field: 'RX ready' in reg: 'Status Register'
- uart_sr_rx_rdy_i : in std_logic;
--- Port for std_logic_vector field: 'Baudrate divider setting' in reg: 'Baudrate control register'
- uart_bcr_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Transmit data' in reg: 'Transmit data regsiter'
- uart_tdr_tx_data_o : out std_logic_vector(7 downto 0);
- uart_tdr_tx_data_i : in std_logic_vector(7 downto 0);
- uart_tdr_tx_data_load_o : out std_logic;
--- Port for std_logic_vector field: 'Received data' in reg: 'Receive data regsiter'
- uart_rdr_rx_data_i : in std_logic_vector(7 downto 0);
- rdr_rack_o : out std_logic;
--- FIFO write request
- uart_debug_wr_req_i : in std_logic;
--- FIFO full flag
- uart_debug_wr_full_o : out std_logic;
--- FIFO empty flag
- uart_debug_wr_empty_o : out std_logic;
--- FIFO number of used words
- uart_debug_wr_usedw_o : out std_logic_vector(10 downto 0);
- uart_debug_tx_i : in std_logic_vector(7 downto 0);
- uart_debug_dupa_i : in std_logic_vector(31 downto 0)
- );
-end wb_virtual_uart_slave;
-
-architecture syn of wb_virtual_uart_slave is
-
-signal uart_bcr_int : std_logic_vector(31 downto 0);
-signal uart_debug_in_int : std_logic_vector(39 downto 0);
-signal uart_debug_out_int : std_logic_vector(39 downto 0);
-signal uart_debug_rdreq_int : std_logic ;
-signal uart_debug_rdreq_int_d0 : std_logic ;
-signal uart_debug_full_int : std_logic ;
-signal uart_debug_empty_int : std_logic ;
-signal uart_debug_usedw_int : std_logic_vector(10 downto 0);
-signal ack_sreg : std_logic_vector(9 downto 0);
-signal rddata_reg : std_logic_vector(31 downto 0);
-signal wrdata_reg : std_logic_vector(31 downto 0);
-signal bwsel_reg : std_logic_vector(3 downto 0);
-signal rwaddr_reg : std_logic_vector(2 downto 0);
-signal ack_in_progress : std_logic ;
-signal wr_int : std_logic ;
-signal rd_int : std_logic ;
-signal bus_clock_int : std_logic ;
-signal allones : std_logic_vector(31 downto 0);
-signal allzeros : std_logic_vector(31 downto 0);
-
-begin
--- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
- wrdata_reg <= wb_data_i;
- bwsel_reg <= wb_sel_i;
- bus_clock_int <= wb_clk_i;
- rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
- wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
- allones <= (others => '1');
- allzeros <= (others => '0');
---
--- Main register bank access process.
- process (bus_clock_int, rst_n_i)
- begin
- if (rst_n_i = '0') then
- ack_sreg <= "0000000000";
- ack_in_progress <= '0';
- rddata_reg <= "00000000000000000000000000000000";
- uart_bcr_int <= "00000000000000000000000000000000";
- uart_tdr_tx_data_load_o <= '0';
- rdr_rack_o <= '0';
- uart_debug_rdreq_int <= '0';
- elsif rising_edge(bus_clock_int) then
--- advance the ACK generator shift register
- ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
- ack_sreg(9) <= '0';
- if (ack_in_progress = '1') then
- if (ack_sreg(0) = '1') then
- uart_tdr_tx_data_load_o <= '0';
- rdr_rack_o <= '0';
- ack_in_progress <= '0';
- else
- uart_tdr_tx_data_load_o <= '0';
- end if;
- else
- if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
- case rwaddr_reg(2 downto 0) is
- when "000" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(0) <= uart_sr_tx_busy_i;
- rddata_reg(1) <= uart_sr_rx_rdy_i;
- rddata_reg(2) <= 'X';
- rddata_reg(3) <= 'X';
- rddata_reg(4) <= 'X';
- rddata_reg(5) <= 'X';
- rddata_reg(6) <= 'X';
- rddata_reg(7) <= 'X';
- rddata_reg(8) <= 'X';
- rddata_reg(9) <= 'X';
- rddata_reg(10) <= 'X';
- rddata_reg(11) <= 'X';
- rddata_reg(12) <= 'X';
- rddata_reg(13) <= 'X';
- rddata_reg(14) <= 'X';
- rddata_reg(15) <= 'X';
- rddata_reg(16) <= 'X';
- rddata_reg(17) <= 'X';
- rddata_reg(18) <= 'X';
- rddata_reg(19) <= 'X';
- rddata_reg(20) <= 'X';
- rddata_reg(21) <= 'X';
- rddata_reg(22) <= 'X';
- rddata_reg(23) <= 'X';
- rddata_reg(24) <= 'X';
- rddata_reg(25) <= 'X';
- rddata_reg(26) <= 'X';
- rddata_reg(27) <= 'X';
- rddata_reg(28) <= 'X';
- rddata_reg(29) <= 'X';
- rddata_reg(30) <= 'X';
- rddata_reg(31) <= 'X';
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "001" =>
- if (wb_we_i = '1') then
- uart_bcr_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= uart_bcr_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "010" =>
- if (wb_we_i = '1') then
- uart_tdr_tx_data_load_o <= '1';
- else
- rddata_reg(7 downto 0) <= uart_tdr_tx_data_i;
- rddata_reg(8) <= 'X';
- rddata_reg(9) <= 'X';
- rddata_reg(10) <= 'X';
- rddata_reg(11) <= 'X';
- rddata_reg(12) <= 'X';
- rddata_reg(13) <= 'X';
- rddata_reg(14) <= 'X';
- rddata_reg(15) <= 'X';
- rddata_reg(16) <= 'X';
- rddata_reg(17) <= 'X';
- rddata_reg(18) <= 'X';
- rddata_reg(19) <= 'X';
- rddata_reg(20) <= 'X';
- rddata_reg(21) <= 'X';
- rddata_reg(22) <= 'X';
- rddata_reg(23) <= 'X';
- rddata_reg(24) <= 'X';
- rddata_reg(25) <= 'X';
- rddata_reg(26) <= 'X';
- rddata_reg(27) <= 'X';
- rddata_reg(28) <= 'X';
- rddata_reg(29) <= 'X';
- rddata_reg(30) <= 'X';
- rddata_reg(31) <= 'X';
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "011" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(7 downto 0) <= uart_rdr_rx_data_i;
- rdr_rack_o <= '1';
- rddata_reg(8) <= 'X';
- rddata_reg(9) <= 'X';
- rddata_reg(10) <= 'X';
- rddata_reg(11) <= 'X';
- rddata_reg(12) <= 'X';
- rddata_reg(13) <= 'X';
- rddata_reg(14) <= 'X';
- rddata_reg(15) <= 'X';
- rddata_reg(16) <= 'X';
- rddata_reg(17) <= 'X';
- rddata_reg(18) <= 'X';
- rddata_reg(19) <= 'X';
- rddata_reg(20) <= 'X';
- rddata_reg(21) <= 'X';
- rddata_reg(22) <= 'X';
- rddata_reg(23) <= 'X';
- rddata_reg(24) <= 'X';
- rddata_reg(25) <= 'X';
- rddata_reg(26) <= 'X';
- rddata_reg(27) <= 'X';
- rddata_reg(28) <= 'X';
- rddata_reg(29) <= 'X';
- rddata_reg(30) <= 'X';
- rddata_reg(31) <= 'X';
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "100" =>
- if (wb_we_i = '1') then
- else
- if (uart_debug_rdreq_int_d0 = '0') then
- uart_debug_rdreq_int <= not uart_debug_rdreq_int;
- else
- rddata_reg(7 downto 0) <= uart_debug_out_int(7 downto 0);
- ack_in_progress <= '1';
- ack_sreg(0) <= '1';
- end if;
- rddata_reg(8) <= 'X';
- rddata_reg(9) <= 'X';
- rddata_reg(10) <= 'X';
- rddata_reg(11) <= 'X';
- rddata_reg(12) <= 'X';
- rddata_reg(13) <= 'X';
- rddata_reg(14) <= 'X';
- rddata_reg(15) <= 'X';
- rddata_reg(16) <= 'X';
- rddata_reg(17) <= 'X';
- rddata_reg(18) <= 'X';
- rddata_reg(19) <= 'X';
- rddata_reg(20) <= 'X';
- rddata_reg(21) <= 'X';
- rddata_reg(22) <= 'X';
- rddata_reg(23) <= 'X';
- rddata_reg(24) <= 'X';
- rddata_reg(25) <= 'X';
- rddata_reg(26) <= 'X';
- rddata_reg(27) <= 'X';
- rddata_reg(28) <= 'X';
- rddata_reg(29) <= 'X';
- rddata_reg(30) <= 'X';
- rddata_reg(31) <= 'X';
- end if;
- when "101" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= uart_debug_out_int(39 downto 8);
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "110" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(16) <= uart_debug_full_int;
- rddata_reg(17) <= uart_debug_empty_int;
- rddata_reg(10 downto 0) <= uart_debug_usedw_int;
- rddata_reg(11) <= 'X';
- rddata_reg(12) <= 'X';
- rddata_reg(13) <= 'X';
- rddata_reg(14) <= 'X';
- rddata_reg(15) <= 'X';
- rddata_reg(18) <= 'X';
- rddata_reg(19) <= 'X';
- rddata_reg(20) <= 'X';
- rddata_reg(21) <= 'X';
- rddata_reg(22) <= 'X';
- rddata_reg(23) <= 'X';
- rddata_reg(24) <= 'X';
- rddata_reg(25) <= 'X';
- rddata_reg(26) <= 'X';
- rddata_reg(27) <= 'X';
- rddata_reg(28) <= 'X';
- rddata_reg(29) <= 'X';
- rddata_reg(30) <= 'X';
- rddata_reg(31) <= 'X';
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when others =>
--- prevent the slave from hanging the bus on invalid address
- ack_in_progress <= '1';
- ack_sreg(0) <= '1';
- end case;
- end if;
- end if;
- end if;
- end process;
-
-
--- Drive the data output bus
- wb_data_o <= rddata_reg;
--- TX busy
--- RX ready
--- Baudrate divider setting
- uart_bcr_o <= uart_bcr_int;
--- Transmit data
- uart_tdr_tx_data_o <= wrdata_reg(7 downto 0);
--- Received data
--- extra code for reg/fifo/mem: UART TX FIFO
- uart_debug_in_int(7 downto 0) <= uart_debug_tx_i;
- uart_debug_in_int(39 downto 8) <= uart_debug_dupa_i;
- uart_debug_INST : wbgen2_fifo_sync
- generic map (
- g_size => 2048,
- g_width => 40,
- g_usedw_size => 11
- )
- port map (
- wr_req_i => uart_debug_wr_req_i,
- wr_full_o => uart_debug_wr_full_o,
- wr_empty_o => uart_debug_wr_empty_o,
- wr_usedw_o => uart_debug_wr_usedw_o,
- rd_full_o => uart_debug_full_int,
- rd_empty_o => uart_debug_empty_int,
- rd_usedw_o => uart_debug_usedw_int,
- rd_req_i => uart_debug_rdreq_int,
- clk_i => bus_clock_int,
- wr_data_i => uart_debug_in_int,
- rd_data_o => uart_debug_out_int
- );
-
--- extra code for reg/fifo/mem: FIFO 'UART TX FIFO' data output register 0
- process (bus_clock_int, rst_n_i)
- begin
- if (rst_n_i = '0') then
- uart_debug_rdreq_int_d0 <= '0';
- elsif rising_edge(bus_clock_int) then
- uart_debug_rdreq_int_d0 <= uart_debug_rdreq_int;
- end if;
- end process;
-
-
--- extra code for reg/fifo/mem: FIFO 'UART TX FIFO' data output register 1
- rwaddr_reg <= wb_addr_i;
--- ACK signal generation. Just pass the LSB of ACK counter.
- wb_ack_o <= ack_sreg(0);
-end syn;
diff --git a/modules/wishbone/wb_virtual_uart/wb_vuart.h b/modules/wishbone/wb_virtual_uart/wb_vuart.h
deleted file mode 100644
index 95a41b4c75898829c0f754bc68db0e1bd18aec38..0000000000000000000000000000000000000000
--- a/modules/wishbone/wb_virtual_uart/wb_vuart.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- Register definitions for slave core: Virtual UART
-
- * File : wb_vuart.h
- * Author : auto-generated by wbgen2 from wb_virtual_uart.wb
- * Created : Thu Apr 7 00:51:02 2011
- * Standard : ANSI C
-
- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_virtual_uart.wb
- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
-
-*/
-
-#ifndef __WBGEN2_REGDEFS_WB_VIRTUAL_UART_WB
-#define __WBGEN2_REGDEFS_WB_VIRTUAL_UART_WB
-
-#include <inttypes.h>
-
-#if defined( __GNUC__)
-#define PACKED __attribute__ ((packed))
-#else
-#error "Unsupported compiler?"
-#endif
-
-#ifndef __WBGEN2_MACROS_DEFINED__
-#define __WBGEN2_MACROS_DEFINED__
-#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
-#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
-#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
-#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
-#endif
-
-
-/* definitions for register: Status Register */
-
-/* definitions for field: TX busy in reg: Status Register */
-#define UART_SR_TX_BUSY WBGEN2_GEN_MASK(0, 1)
-
-/* definitions for field: RX ready in reg: Status Register */
-#define UART_SR_RX_RDY WBGEN2_GEN_MASK(1, 1)
-
-/* definitions for register: Baudrate control register */
-
-/* definitions for register: Transmit data regsiter */
-
-/* definitions for field: Transmit data in reg: Transmit data regsiter */
-#define UART_TDR_TX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
-#define UART_TDR_TX_DATA_SHIFT 0
-#define UART_TDR_TX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
-#define UART_TDR_TX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
-
-/* definitions for register: Receive data regsiter */
-
-/* definitions for field: Received data in reg: Receive data regsiter */
-#define UART_RDR_RX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
-#define UART_RDR_RX_DATA_SHIFT 0
-#define UART_RDR_RX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
-#define UART_RDR_RX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
-
-/* definitions for register: FIFO 'UART TX FIFO' data output register 0 */
-
-/* definitions for field: Char sent by UART to TX in reg: FIFO 'UART TX FIFO' data output register 0 */
-#define UART_DEBUG_R0_TX_MASK WBGEN2_GEN_MASK(0, 8)
-#define UART_DEBUG_R0_TX_SHIFT 0
-#define UART_DEBUG_R0_TX_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
-#define UART_DEBUG_R0_TX_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
-
-/* definitions for register: FIFO 'UART TX FIFO' data output register 1 */
-
-/* definitions for field: Dupa in reg: FIFO 'UART TX FIFO' data output register 1 */
-#define UART_DEBUG_R1_DUPA_MASK WBGEN2_GEN_MASK(0, 32)
-#define UART_DEBUG_R1_DUPA_SHIFT 0
-#define UART_DEBUG_R1_DUPA_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
-#define UART_DEBUG_R1_DUPA_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
-
-/* definitions for register: FIFO 'UART TX FIFO' control/status register */
-
-/* definitions for field: FIFO full flag in reg: FIFO 'UART TX FIFO' control/status register */
-#define UART_DEBUG_CSR_FULL WBGEN2_GEN_MASK(16, 1)
-
-/* definitions for field: FIFO empty flag in reg: FIFO 'UART TX FIFO' control/status register */
-#define UART_DEBUG_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
-
-/* definitions for field: FIFO counter in reg: FIFO 'UART TX FIFO' control/status register */
-#define UART_DEBUG_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
-#define UART_DEBUG_CSR_USEDW_SHIFT 0
-#define UART_DEBUG_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
-#define UART_DEBUG_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
-/* [0x0]: REG Status Register */
-#define UART_REG_SR 0x00000000
-/* [0x4]: REG Baudrate control register */
-#define UART_REG_BCR 0x00000004
-/* [0x8]: REG Transmit data regsiter */
-#define UART_REG_TDR 0x00000008
-/* [0xc]: REG Receive data regsiter */
-#define UART_REG_RDR 0x0000000c
-/* [0x10]: REG FIFO 'UART TX FIFO' data output register 0 */
-#define UART_REG_DEBUG_R0 0x00000010
-/* [0x14]: REG FIFO 'UART TX FIFO' data output register 1 */
-#define UART_REG_DEBUG_R1 0x00000014
-/* [0x18]: REG FIFO 'UART TX FIFO' control/status register */
-#define UART_REG_DEBUG_CSR 0x00000018
-#endif