From e4f3f8c874cfec8f162bfc0da9794e66e39b911b Mon Sep 17 00:00:00 2001
From: Dimitris Lampridis <dimitris.lampridis@cern.ch>
Date: Mon, 28 Jan 2019 16:24:20 +0100
Subject: [PATCH] hdl: minor cleanup of async fifos sources
---
.../genrams/common/inferred_async_fifo.vhd | 112 +++++++++---------
.../common/inferred_async_fifo_dual_rst.vhd | 4 +-
2 files changed, 58 insertions(+), 58 deletions(-)
diff --git a/modules/genrams/common/inferred_async_fifo.vhd b/modules/genrams/common/inferred_async_fifo.vhd
index 8cd8f658..6e746139 100644
--- a/modules/genrams/common/inferred_async_fifo.vhd
+++ b/modules/genrams/common/inferred_async_fifo.vhd
@@ -37,20 +37,20 @@ entity inferred_async_fifo is
generic (
g_data_width : natural;
g_size : natural;
- g_show_ahead : boolean := false;
+ g_show_ahead : boolean := FALSE;
-- Read-side flag selection
- g_with_rd_empty : boolean := true; -- with empty flag
- g_with_rd_full : boolean := false; -- with full flag
- g_with_rd_almost_empty : boolean := false;
- g_with_rd_almost_full : boolean := false;
- g_with_rd_count : boolean := false; -- with words counter
-
- g_with_wr_empty : boolean := false;
- g_with_wr_full : boolean := true;
- g_with_wr_almost_empty : boolean := false;
- g_with_wr_almost_full : boolean := false;
- g_with_wr_count : boolean := false;
+ g_with_rd_empty : boolean := TRUE; -- with empty flag
+ g_with_rd_full : boolean := FALSE; -- with full flag
+ g_with_rd_almost_empty : boolean := FALSE;
+ g_with_rd_almost_full : boolean := FALSE;
+ g_with_rd_count : boolean := FALSE; -- with words counter
+
+ g_with_wr_empty : boolean := FALSE;
+ g_with_wr_full : boolean := TRUE;
+ g_with_wr_almost_empty : boolean := FALSE;
+ g_with_wr_almost_full : boolean := FALSE;
+ g_with_wr_count : boolean := FALSE;
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
@@ -67,7 +67,7 @@ entity inferred_async_fifo is
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
- wr_almost_empty_o : out std_logic; -- TODO: assign
+ wr_almost_empty_o : out std_logic; -- TODO: assign
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
@@ -79,7 +79,7 @@ entity inferred_async_fifo is
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
- rd_almost_full_o : out std_logic; -- TODO: assign
+ rd_almost_full_o : out std_logic; -- TODO: assign
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
@@ -90,16 +90,16 @@ architecture syn of inferred_async_fifo is
function f_bin2gray(bin : std_logic_vector) return std_logic_vector is
begin
- return bin(bin'left) & (bin(bin'left-1 downto 0) xor bin(bin'left downto 1));
+ return bin(bin'LEFT) & (bin(bin'LEFT-1 downto 0) xor bin(bin'LEFT downto 1));
end f_bin2gray;
function f_gray2bin(gray : std_logic_vector) return std_logic_vector is
- variable bin : std_logic_vector(gray'left downto 0);
+ variable bin : std_logic_vector(gray'LEFT downto 0);
begin
-- gray to binary
- for i in 0 to gray'left loop
+ for i in 0 to gray'LEFT loop
bin(i) := '0';
- for j in i to gray'left loop
+ for j in i to gray'LEFT loop
bin(i) := bin(i) xor gray(j);
end loop; -- j
end loop; -- i
@@ -114,10 +114,10 @@ architecture syn of inferred_async_fifo is
bin_x, gray_x, gray_xm : t_counter;
end record;
- type t_mem_type is array (0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
+ type t_mem_type is array (0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
signal mem : t_mem_type := (others => (others => '0'));
- signal rcb, wcb : t_counter_block;
+ signal rcb, wcb : t_counter_block;
signal rd_ptr_muxed : t_counter;
@@ -126,7 +126,7 @@ architecture syn of inferred_async_fifo is
signal going_full : std_logic;
signal wr_count, rd_count : t_counter;
- signal rd_int, we_int : std_logic;
+ signal rd_int, we_int : std_logic;
signal wr_empty_xm, wr_empty_x : std_logic;
signal rd_full_xm, rd_full_x : std_logic;
@@ -141,7 +141,7 @@ begin -- syn
rd_int <= rd_i and not empty_int;
we_int <= we_i and not full_int;
- p_rd_ptr_mux: process(rcb, rd_int)
+ p_rd_ptr_mux : process(rcb, rd_int)
begin
if(rd_int = '1' and g_show_ahead) then
rd_ptr_muxed <= rcb.bin_next;
@@ -154,19 +154,19 @@ begin -- syn
begin
if rising_edge(clk_wr_i) then
if(we_int = '1') then
- mem(to_integer(unsigned(wcb.bin(wcb.bin'left-1 downto 0)))) <= d_i;
+ mem(to_integer(unsigned(wcb.bin(wcb.bin'LEFT-1 downto 0)))) <= d_i;
end if;
end if;
- end process;
+ end process p_mem_write;
p_mem_read : process(clk_rd_i)
begin
if rising_edge(clk_rd_i) then
if(rd_int = '1' or g_show_ahead) then
- q_int <= mem(to_integer(unsigned(rd_ptr_muxed(rd_ptr_muxed'left-1 downto 0))));
+ q_int <= mem(to_integer(unsigned(rd_ptr_muxed(rd_ptr_muxed'LEFT-1 downto 0))));
end if;
end if;
- end process;
+ end process p_mem_read;
q_o <= q_int;
@@ -184,7 +184,7 @@ begin -- syn
wcb.gray <= wcb.gray_next;
end if;
end if;
- end process;
+ end process p_write_ptr;
rcb.bin_next <= std_logic_vector(unsigned(rcb.bin) + 1);
rcb.gray_next <= f_bin2gray(rcb.bin_next);
@@ -200,25 +200,25 @@ begin -- syn
rcb.gray <= rcb.gray_next;
end if;
end if;
- end process;
+ end process p_read_ptr;
- U_Sync1: gc_sync_register
+ U_Sync1 : gc_sync_register
generic map (
g_width => c_counter_bits)
port map (
- clk_i => clk_wr_i,
- rst_n_a_i => rst_n_i,
- d_i => rcb.gray,
- q_o => rcb.gray_x);
+ clk_i => clk_wr_i,
+ rst_n_a_i => rst_n_i,
+ d_i => rcb.gray,
+ q_o => rcb.gray_x);
- U_Sync2: gc_sync_register
+ U_Sync2 : gc_sync_register
generic map (
g_width => c_counter_bits)
port map (
- clk_i => clk_rd_i,
- rst_n_a_i => rst_n_i,
- d_i => wcb.gray,
- q_o => wcb.gray_x);
+ clk_i => clk_rd_i,
+ rst_n_a_i => rst_n_i,
+ d_i => wcb.gray,
+ q_o => wcb.gray_x);
wcb.bin_x <= f_gray2bin(wcb.gray_x);
rcb.bin_x <= f_gray2bin(rcb.gray_x);
@@ -234,9 +234,9 @@ begin -- syn
empty_int <= '0';
end if;
end if;
- end process;
+ end process p_gen_empty;
- U_Sync_Empty: gc_sync_ffs
+ U_Sync_Empty : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
@@ -245,7 +245,7 @@ begin -- syn
data_i => empty_int,
synced_o => wr_empty_x);
- U_Sync_Full: gc_sync_ffs
+ U_Sync_Full : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
@@ -253,25 +253,25 @@ begin -- syn
rst_n_i => rst_n_i,
data_i => full_int,
synced_o => rd_full_x);
-
-
+
+
rd_empty_o <= empty_int;
wr_empty_o <= wr_empty_x;
p_gen_going_full : process(we_int, wcb, rcb)
begin
- if ((wcb.bin (wcb.bin'left-1 downto 0) = rcb.bin_x(rcb.bin_x'left-1 downto 0))
- and (wcb.bin(wcb.bin'left) /= rcb.bin_x(rcb.bin_x'left))) then
+ if ((wcb.bin (wcb.bin'LEFT-1 downto 0) = rcb.bin_x(rcb.bin_x'LEFT-1 downto 0))
+ and (wcb.bin(wcb.bin'LEFT) /= rcb.bin_x(rcb.bin_x'LEFT))) then
going_full <= '1';
elsif (we_int = '1'
- and (wcb.bin_next(wcb.bin'left-1 downto 0) = rcb.bin_x(rcb.bin_x'left-1 downto 0))
- and (wcb.bin_next(wcb.bin'left) /= rcb.bin_x(rcb.bin_x'left))) then
+ and (wcb.bin_next(wcb.bin'LEFT-1 downto 0) = rcb.bin_x(rcb.bin_x'LEFT-1 downto 0))
+ and (wcb.bin_next(wcb.bin'LEFT) /= rcb.bin_x(rcb.bin_x'LEFT))) then
going_full <= '1';
else
going_full <= '0';
end if;
- end process;
+ end process p_gen_going_full;
p_register_full : process(clk_wr_i, rst_n_i)
begin
@@ -280,7 +280,7 @@ begin -- syn
elsif rising_edge (clk_wr_i) then
full_int <= going_full;
end if;
- end process;
+ end process p_register_full;
wr_full_o <= full_int;
rd_full_o <= rd_full_x;
@@ -297,9 +297,9 @@ begin -- syn
almost_full_int <= '0';
end if;
end if;
- end process;
+ end process p_reg_almost_full;
- U_Sync_AlmostFull: gc_sync_ffs
+ U_Sync_AlmostFull : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
@@ -308,24 +308,24 @@ begin -- syn
data_i => almost_full_int,
synced_o => almost_full_x);
- wr_almost_full_o <= almost_full_int;
- rd_almost_full_o <= almost_full_x;
+ wr_almost_full_o <= almost_full_int;
+ rd_almost_full_o <= almost_full_x;
p_reg_almost_empty : process(clk_rd_i, rst_n_i)
begin
if rst_n_i = '0' then
almost_empty_int <= '1';
elsif rising_edge(clk_rd_i) then
- rd_count <= std_logic_vector(unsigned(wcb.bin_x) - unsigned(rcb.bin));
+ rd_count <= std_logic_vector(unsigned(wcb.bin_x) - unsigned(rcb.bin));
if (unsigned(rd_count) <= g_almost_empty_threshold) then
almost_empty_int <= '1';
else
almost_empty_int <= '0';
end if;
end if;
- end process;
+ end process p_reg_almost_empty;
- U_Sync_AlmostEmpty: gc_sync_ffs
+ U_Sync_AlmostEmpty : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
diff --git a/modules/genrams/common/inferred_async_fifo_dual_rst.vhd b/modules/genrams/common/inferred_async_fifo_dual_rst.vhd
index 6cfa9032..45cddbcc 100644
--- a/modules/genrams/common/inferred_async_fifo_dual_rst.vhd
+++ b/modules/genrams/common/inferred_async_fifo_dual_rst.vhd
@@ -114,7 +114,7 @@ begin -- syn
rd_int <= rd_i and not empty_int;
we_int <= we_i and not full_int;
- p_rd_ptr_mux: process(rcb, rd_int)
+ p_rd_ptr_mux : process(rcb, rd_int)
begin
if(rd_int = '1' and g_show_ahead) then
rd_ptr_muxed <= rcb.bin_next;
@@ -136,7 +136,7 @@ begin -- syn
begin
if rising_edge(clk_rd_i) then
if(rd_int = '1' or g_show_ahead) then
- q_int <= mem(to_integer(unsigned(rd_ptr_muxed(rd_ptr_muxed'left-1 downto 0))));
+ q_int <= mem(to_integer(unsigned(rd_ptr_muxed(rd_ptr_muxed'LEFT-1 downto 0))));
end if;
end if;
end process p_mem_read;
--
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