From e3950a08d7487f1df53025f6b35e814d451646cf Mon Sep 17 00:00:00 2001
From: Dimitris Lampridis <dimitris.lampridis@cern.ch>
Date: Mon, 28 Jan 2019 16:21:05 +0100
Subject: [PATCH] hdl: implement g_show ahead for async fifos
---
modules/genrams/common/inferred_async_fifo.vhd | 18 ++++++++++++++----
.../common/inferred_async_fifo_dual_rst.vhd | 16 +++++++++++++---
2 files changed, 27 insertions(+), 7 deletions(-)
diff --git a/modules/genrams/common/inferred_async_fifo.vhd b/modules/genrams/common/inferred_async_fifo.vhd
index 8b1ba631..8cd8f658 100644
--- a/modules/genrams/common/inferred_async_fifo.vhd
+++ b/modules/genrams/common/inferred_async_fifo.vhd
@@ -115,11 +115,12 @@ architecture syn of inferred_async_fifo is
end record;
type t_mem_type is array (0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
- signal mem : t_mem_type;
+ signal mem : t_mem_type := (others => (others => '0'));
signal rcb, wcb : t_counter_block;
-
+ signal rd_ptr_muxed : t_counter;
+
signal full_int, empty_int : std_logic;
signal almost_full_int, almost_empty_int : std_logic;
signal going_full : std_logic;
@@ -140,6 +141,15 @@ begin -- syn
rd_int <= rd_i and not empty_int;
we_int <= we_i and not full_int;
+ p_rd_ptr_mux: process(rcb, rd_int)
+ begin
+ if(rd_int = '1' and g_show_ahead) then
+ rd_ptr_muxed <= rcb.bin_next;
+ elsif((rd_int = '1' and not g_show_ahead) or (g_show_ahead)) then
+ rd_ptr_muxed <= rcb.bin;
+ end if;
+ end process p_rd_ptr_mux;
+
p_mem_write : process(clk_wr_i)
begin
if rising_edge(clk_wr_i) then
@@ -152,8 +162,8 @@ begin -- syn
p_mem_read : process(clk_rd_i)
begin
if rising_edge(clk_rd_i) then
- if(rd_int = '1') then
- q_int <= mem(to_integer(unsigned(rcb.bin(rcb.bin'left-1 downto 0))));
+ if(rd_int = '1' or g_show_ahead) then
+ q_int <= mem(to_integer(unsigned(rd_ptr_muxed(rd_ptr_muxed'left-1 downto 0))));
end if;
end if;
end process;
diff --git a/modules/genrams/common/inferred_async_fifo_dual_rst.vhd b/modules/genrams/common/inferred_async_fifo_dual_rst.vhd
index 0cb8657f..6cfa9032 100644
--- a/modules/genrams/common/inferred_async_fifo_dual_rst.vhd
+++ b/modules/genrams/common/inferred_async_fifo_dual_rst.vhd
@@ -88,10 +88,11 @@ architecture syn of inferred_async_fifo_dual_rst is
end record;
type t_mem_type is array (0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
- signal mem : t_mem_type;
+ signal mem : t_mem_type := (others => (others => '0'));
signal rcb, wcb : t_counter_block;
+ signal rd_ptr_muxed : t_counter;
signal full_int, empty_int : std_logic;
signal almost_full_int, almost_empty_int : std_logic;
@@ -113,6 +114,15 @@ begin -- syn
rd_int <= rd_i and not empty_int;
we_int <= we_i and not full_int;
+ p_rd_ptr_mux: process(rcb, rd_int)
+ begin
+ if(rd_int = '1' and g_show_ahead) then
+ rd_ptr_muxed <= rcb.bin_next;
+ elsif((rd_int = '1' and not g_show_ahead) or (g_show_ahead)) then
+ rd_ptr_muxed <= rcb.bin;
+ end if;
+ end process p_rd_ptr_mux;
+
p_mem_write : process(clk_wr_i)
begin
if rising_edge(clk_wr_i) then
@@ -125,8 +135,8 @@ begin -- syn
p_mem_read : process(clk_rd_i)
begin
if rising_edge(clk_rd_i) then
- if rd_int = '1' then
- q_int <= mem(to_integer(unsigned(rcb.bin(rcb.bin'LEFT-1 downto 0))));
+ if(rd_int = '1' or g_show_ahead) then
+ q_int <= mem(to_integer(unsigned(rd_ptr_muxed(rd_ptr_muxed'left-1 downto 0))));
end if;
end if;
end process p_mem_read;
--
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