diff --git a/testbench/wishbone/lm32_testsys/lm32_test_system.vhd b/testbench/wishbone/lm32_testsys/lm32_test_system.vhd
index 1559f160e21ac47520e5e7452014c40c0ef4163c..159ad68e771e9b1244451eb0ba3bfb01914a3d6f 100644
--- a/testbench/wishbone/lm32_testsys/lm32_test_system.vhd
+++ b/testbench/wishbone/lm32_testsys/lm32_test_system.vhd
@@ -92,60 +92,60 @@ begin -- rtl
slave2_i => cnx_master_out(1),
slave2_o => cnx_master_in(1));
- U_peripheral_Fanout : xwb_bus_fanout
- generic map (
- g_num_outputs => c_peripherals,
- g_bits_per_slave => 8,
- g_address_granularity => BYTE,
- g_slave_interface_mode => PIPELINED)
- port map (
- clk_sys_i => clk_sys_i,
- rst_n_i => rst_n_i,
- slave_i => cnx_master_out(2),
- slave_o => cnx_master_in(2),
- master_i => periph_in,
- master_o => periph_out);
-
- U_GPIO : xwb_gpio_port
- generic map (
- g_interface_mode => CLASSIC,
- g_address_granularity => BYTE,
- g_num_pins => 32,
- g_with_builtin_tristates => true)
- port map (
- clk_sys_i => clk_sys_i,
- rst_n_i => rst_n_i,
- slave_i => periph_out(0),
- slave_o => periph_in(0),
- gpio_b => gpio_b,
- gpio_in_i => x"00000000"
- );
+ --U_peripheral_Fanout : xwb_bus_fanout
+ -- generic map (
+ -- g_num_outputs => c_peripherals,
+ -- g_bits_per_slave => 8,
+ -- g_address_granularity => BYTE,
+ -- g_slave_interface_mode => PIPELINED)
+ -- port map (
+ -- clk_sys_i => clk_sys_i,
+ -- rst_n_i => rst_n_i,
+ -- slave_i => cnx_master_out(2),
+ -- slave_o => cnx_master_in(2),
+ -- master_i => periph_in,
+ -- master_o => periph_out);
+
+ --U_GPIO : xwb_gpio_port
+ -- generic map (
+ -- g_interface_mode => CLASSIC,
+ -- g_address_granularity => BYTE,
+ -- g_num_pins => 32,
+ -- g_with_builtin_tristates => true)
+ -- port map (
+ -- clk_sys_i => clk_sys_i,
+ -- rst_n_i => rst_n_i,
+ -- slave_i => periph_out(0),
+ -- slave_o => periph_in(0),
+ -- gpio_b => gpio_b,
+ -- gpio_in_i => x"00000000"
+ -- );
U_UART : xwb_simple_uart
generic map (
- g_interface_mode => CLASSIC,
+ g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
- slave_i => periph_out(1),
- slave_o => periph_in(1),
+ slave_i => cnx_master_out(2),
+ slave_o => cnx_master_in(2),
uart_rxd_i => rxd_i,
uart_txd_o => txd_o);
- U_OneWire : xwb_onewire_master
- generic map (
- g_interface_mode => CLASSIC,
- g_address_granularity => BYTE,
- g_num_ports => 1)
- port map (
- clk_sys_i => clk_sys_i,
- rst_n_i => rst_n_i,
- slave_i => periph_out(2),
- slave_o => periph_in(2),
- owr_en_o => owr_en_slv,
- owr_i => owr_in_slv);
-
- onewire_b <= '0' when owr_en_slv(0) = '1' else 'Z';
- owr_in_slv(0) <= onewire_b;
+ --U_OneWire : xwb_onewire_master
+ -- generic map (
+ -- g_interface_mode => CLASSIC,
+ -- g_address_granularity => BYTE,
+ -- g_num_ports => 1)
+ -- port map (
+ -- clk_sys_i => clk_sys_i,
+ -- rst_n_i => rst_n_i,
+ -- slave_i => periph_out(2),
+ -- slave_o => periph_in(2),
+ -- owr_en_o => owr_en_slv,
+ -- owr_i => owr_in_slv);
+
+ --onewire_b <= '0' when owr_en_slv(0) = '1' else 'Z';
+ --owr_in_slv(0) <= onewire_b;
end rtl;
diff --git a/testbench/wishbone/lm32_testsys/sw/main.ram b/testbench/wishbone/lm32_testsys/sw/main.ram
index f732d823bfbb4f32b384b665b27c95396c101077..43e4885d4cb7b67a97a8024dfca329d23e28ba4f 100644
--- a/testbench/wishbone/lm32_testsys/sw/main.ram
+++ b/testbench/wishbone/lm32_testsys/sw/main.ram
@@ -138,7 +138,7 @@ write 88 2B9D0004
write 89 379C0004
write 8a C3A00000
write 8b 78012000
-write 8c 38210100
+write 8c 38210000
write 8d 3402147B
write 8e 58220004
write 8f C3A00000
@@ -146,7 +146,7 @@ write 90 379CFFFC
write 91 5B9D0004
write 92 78022000
write 93 202300FF
-write 94 38420100
+write 94 38420000
write 95 28410000
write 96 20210001
write 97 5C20FFFE
@@ -159,12 +159,12 @@ write 9d 2B9D0004
write 9e 379C0004
write 9f C3A00000
write a0 78012000
-write a1 38210100
+write a1 38210000
write a2 28210000
write a3 20210002
write a4 C3A00000
write a5 78012000
-write a6 38210100
+write a6 38210000
write a7 2821000C
write a8 202100FF
write a9 C3A00000
diff --git a/testbench/wishbone/lm32_testsys/sw/uart.c b/testbench/wishbone/lm32_testsys/sw/uart.c
index 20ab3f7843e550ef7bdfd6f6316c63abbd39639e..8841f8fb8d08eb2393089501b6a5eb6dbac465c2 100644
--- a/testbench/wishbone/lm32_testsys/sw/uart.c
+++ b/testbench/wishbone/lm32_testsys/sw/uart.c
@@ -3,7 +3,7 @@
#define CPU_CLOCK 1000000
#define UART_BAUDRATE 10000
-#define BASE_UART 0x20000100
+#define BASE_UART 0x20000000
#include "wb_uart.h"
diff --git a/testbench/wishbone/lm32_testsys/wave.do b/testbench/wishbone/lm32_testsys/wave.do
index 0a0a199e93854ab62ce875ed7904c9e4b4730b1b..ef4637163fe5b94cd0bb028253c81f1fbf1cec1b 100644
--- a/testbench/wishbone/lm32_testsys/wave.do
+++ b/testbench/wishbone/lm32_testsys/wave.do
@@ -1,21 +1,16 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
-add wave -noupdate /main/DUT/U_Intercon/g_num_masters
-add wave -noupdate /main/DUT/U_Intercon/g_num_slaves
-add wave -noupdate /main/DUT/U_Intercon/g_registered
-add wave -noupdate /main/DUT/U_Intercon/clk_sys_i
-add wave -noupdate /main/DUT/U_Intercon/rst_n_i
-add wave -noupdate /main/DUT/U_Intercon/slave_i
-add wave -noupdate /main/DUT/U_Intercon/slave_o
-add wave -noupdate /main/DUT/U_Intercon/master_i
-add wave -noupdate /main/DUT/U_Intercon/master_o
-add wave -noupdate /main/DUT/U_Intercon/cfg_address_i
-add wave -noupdate /main/DUT/U_Intercon/cfg_mask_i
-add wave -noupdate /main/DUT/U_Intercon/previous
-add wave -noupdate /main/DUT/U_Intercon/granted
-add wave -noupdate /main/DUT/U_Intercon/issue
+add wave -noupdate /main/DUT/U_CPU/D_STB_O
+add wave -noupdate /main/DUT/U_CPU/D_ADR
+add wave -noupdate /main/DUT/U_CPU/D_CYC
+add wave -noupdate /main/DUT/U_CPU/D_CTI
+add wave -noupdate /main/DUT/U_CPU/dwb_o
+add wave -noupdate /main/DUT/U_CPU/dwb_i
+add wave -noupdate /main/DUT/U_CPU/data_was_busy
+add wave -noupdate /main/DUT/U_CPU/data_addr_reg
+add wave -noupdate /main/DUT/U_CPU/data_remaining
TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {4093545 ps} 0}
+WaveRestoreCursors {{Cursor 1} {2672526 ps} 0}
configure wave -namecolwidth 350
configure wave -valuecolwidth 100
configure wave -justifyvalue left
@@ -30,4 +25,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
-WaveRestoreZoom {3879920 ps} {4290080 ps}
+WaveRestoreZoom {2262366 ps} {3082686 ps}