From d78e55d6fae8fd8ed89782536f19d9098672fc41 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <w.terpstra@gsi.de>
Date: Thu, 21 Apr 2016 18:00:20 +0200
Subject: [PATCH] msi: enable support in crossbar
---
.../wishbone/wb_crossbar/xwb_sdb_crossbar.vhd | 28 ++++++++++++++++---
modules/wishbone/wishbone_pkg.vhd | 16 +++++++----
2 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd b/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
index 0de69e92..361b52f0 100644
--- a/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
+++ b/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
@@ -15,11 +15,15 @@ entity xwb_sdb_crossbar is
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Master connections (INTERCON is a slave)
- slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
- slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
+ slave_i : in t_wishbone_slave_in_array (g_num_masters-1 downto 0);
+ slave_o : out t_wishbone_slave_out_array (g_num_masters-1 downto 0);
+ msi_master_i : in t_wishbone_master_in_array (g_num_masters-1 downto 0) := (others => cc_dummy_master_in);
+ msi_master_o : out t_wishbone_master_out_array(g_num_masters-1 downto 0);
-- Slave connections (INTERCON is a master)
- master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
- master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0));
+ master_i : in t_wishbone_master_in_array (g_num_slaves -1 downto 0);
+ master_o : out t_wishbone_master_out_array(g_num_slaves -1 downto 0);
+ msi_slave_i : in t_wishbone_slave_in_array (g_num_slaves -1 downto 0) := (others => cc_dummy_slave_in);
+ msi_slave_o : out t_wishbone_slave_out_array (g_num_slaves -1 downto 0));
end xwb_sdb_crossbar;
architecture rtl of xwb_sdb_crossbar is
@@ -256,4 +260,20 @@ begin
master_o => master_o_1,
sdb_sel_o => sdb_sel);
+ msi : xwb_crossbar
+ generic map(
+ g_num_masters => g_num_slaves,
+ g_num_slaves => g_num_masters,
+ g_registered => g_registered,
+ g_address => c_addresses.msi_address,
+ g_mask => c_addresses.msi_mask)
+ port map(
+ clk_sys_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+ slave_i => msi_slave_i,
+ slave_o => msi_slave_o,
+ master_i => msi_master_i,
+ master_o => msi_master_o,
+ sdb_sel_o => open);
+
end rtl;
diff --git a/modules/wishbone/wishbone_pkg.vhd b/modules/wishbone/wishbone_pkg.vhd
index 4d1826d6..358fe3c9 100644
--- a/modules/wishbone/wishbone_pkg.vhd
+++ b/modules/wishbone/wishbone_pkg.vhd
@@ -341,12 +341,16 @@ package wishbone_pkg is
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address);
port (
- clk_sys_i : in std_logic;
- rst_n_i : in std_logic;
- slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
- slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
- master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
- master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0));
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ slave_i : in t_wishbone_slave_in_array (g_num_masters-1 downto 0);
+ slave_o : out t_wishbone_slave_out_array (g_num_masters-1 downto 0);
+ msi_master_i : in t_wishbone_master_in_array (g_num_masters-1 downto 0) := (others => cc_dummy_master_in);
+ msi_master_o : out t_wishbone_master_out_array(g_num_masters-1 downto 0);
+ master_i : in t_wishbone_master_in_array (g_num_slaves -1 downto 0);
+ master_o : out t_wishbone_master_out_array(g_num_slaves -1 downto 0);
+ msi_slave_i : in t_wishbone_slave_in_array (g_num_slaves -1 downto 0) := (others => cc_dummy_slave_in);
+ msi_slave_o : out t_wishbone_slave_out_array (g_num_slaves -1 downto 0));
end component;
component xwb_register_link -- puts a register of delay between crossbars
--
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