diff --git a/modules/common/Manifest.py b/modules/common/Manifest.py
index bff9216cc579423d0af8272333a46b0db459bfb6..2e185e105bf76dc575076da8c2378a55ce285557 100644
--- a/modules/common/Manifest.py
+++ b/modules/common/Manifest.py
@@ -10,5 +10,4 @@ files = [ "gencores_pkg.vhd",
"gc_arbitrated_mux.vhd",
"gc_pulse_synchronizer.vhd",
"gc_frequency_meter.vhd",
- "gc_dual_clock_ram.vhd",
"gc_wfifo.vhd"];
diff --git a/modules/common/gc_dual_clock_ram.vhd b/modules/common/gc_dual_clock_ram.vhd
deleted file mode 100644
index 1f6e28a8f87d23f629308cf6804959a78b72f0cf..0000000000000000000000000000000000000000
--- a/modules/common/gc_dual_clock_ram.vhd
+++ /dev/null
@@ -1,48 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
--- Read during write has an undefined result
-entity gc_dual_clock_ram is
- generic(
- addr_width : natural := 4;
- data_width : natural := 32);
- port(
- -- write port
- w_clk_i : in std_logic;
- w_en_i : in std_logic;
- w_addr_i : in std_logic_vector(addr_width-1 downto 0);
- w_data_i : in std_logic_vector(data_width-1 downto 0);
- -- read port
- r_clk_i : in std_logic;
- r_en_i : in std_logic;
- r_addr_i : in std_logic_vector(addr_width-1 downto 0);
- r_data_o : out std_logic_vector(data_width-1 downto 0));
-end gc_dual_clock_ram;
-
-architecture rtl of gc_dual_clock_ram is
- type ram_t is array(2**addr_width-1 downto 0) of std_logic_vector(data_width-1 downto 0);
- signal ram : ram_t := (others => (others => '0'));
-
- -- Tell synthesizer we do not care about read during write behaviour
- attribute ramstyle : string;
- attribute ramstyle of ram : signal is "no_rw_check";
-begin
- write : process(w_clk_i)
- begin
- if rising_edge(w_clk_i) then
- if w_en_i = '1' then
- ram(to_integer(unsigned(w_addr_i))) <= w_data_i;
- end if;
- end if;
- end process;
-
- read : process(r_clk_i)
- begin
- if rising_edge(r_clk_i) then
- if r_en_i = '1' then
- r_data_o <= ram(to_integer(unsigned(r_addr_i)));
- end if;
- end if;
- end process;
-end rtl;
diff --git a/modules/common/gc_wfifo.vhd b/modules/common/gc_wfifo.vhd
index dd6734c77d237a779f34360d76dd2f1d296f2b66..60b2673ffb644dfb1e5d2a6d0fe7e911f907e6cd 100644
--- a/modules/common/gc_wfifo.vhd
+++ b/modules/common/gc_wfifo.vhd
@@ -1,7 +1,10 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
+
+library work;
use work.gencores_pkg.all;
+use work.genram_pkg.all;
entity gc_wfifo is
generic(
@@ -31,6 +34,10 @@ entity gc_wfifo is
end gc_wfifo;
architecture rtl of gc_wfifo is
+ -- Quartus 11 sometimes goes crazy and infers an altshift_taps! Stop it.
+ attribute altera_attribute : string;
+ attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
+
subtype counter is unsigned(addr_width downto 0);
type counter_shift is array(sync_depth downto 0) of counter;
@@ -45,11 +52,7 @@ architecture rtl of gc_wfifo is
signal r_idx_shift_a : counter_shift; -- r_idx_gray in a_clk
signal w_idx_shift_r : counter_shift; -- w_idx_gray in r_clk
- attribute altera_attribute : string;
- -- Quartus 11 sometimes goes crazy and infers an altshift_taps! Stop it.
- attribute altera_attribute of r_idx_shift_w : signal is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
- attribute altera_attribute of r_idx_shift_a : signal is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
- attribute altera_attribute of w_idx_shift_r : signal is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
+ signal qb : std_logic_vector(data_width-1 downto 0);
function bin2gray(a : unsigned) return unsigned is
variable o : unsigned(a'length downto 0);
@@ -94,21 +97,35 @@ architecture rtl of gc_wfifo is
end if;
end full;
begin
- ram : gc_dual_clock_ram
- generic map(addr_width => addr_width, data_width => data_width)
- port map(w_clk_i => w_clk_i, w_en_i => w_en_i, w_addr_i => index(w_idx_bnry), w_data_i => w_data_i,
- r_clk_i => r_clk_i, r_en_i => r_en_i, r_addr_i => index(r_idx_bnry), r_data_o => r_data_o);
-
+
+ ram : generic_simple_dpram
+ generic map(
+ g_data_width => data_width,
+ g_size => 2**addr_width,
+ g_addr_conflict_resolution => "dont_care",
+ g_dual_clock => gray_code)
+ port map(
+ clka_i => w_clk_i,
+ wea_i => w_en_i,
+ aa_i => index(w_idx_bnry),
+ da_i => w_data_i,
+ clkb_i => r_clk_i,
+ ab_i => index(r_idx_bnry),
+ qb_o => qb);
+
read : process(r_clk_i)
variable idx : counter;
begin
if rising_edge(r_clk_i) then
if r_rst_n_i = '0' then
idx := (others => '0');
+ r_data_o <= qb;
elsif r_en_i = '1' then
idx := r_idx_bnry + 1;
+ r_data_o <= qb;
else
idx := r_idx_bnry;
+ --r_data_o <= r_data_o; --implied
end if;
r_idx_bnry <= idx;
r_idx_gray <= bin2gray(idx);
@@ -161,4 +178,5 @@ begin
end process;
r_idx_shift_a(0) <= r_idx_gray;
a_rdy_o <= not full(a_idx_gray, r_idx_shift_a(sync_depth));
+
end rtl;
diff --git a/modules/common/gencores_pkg.vhd b/modules/common/gencores_pkg.vhd
index f0affd08355b106b93caa3049c2e95ed3c7165d0..91f65568c42dfc469e18ea3b6860cc9cb0ff6eac 100644
--- a/modules/common/gencores_pkg.vhd
+++ b/modules/common/gencores_pkg.vhd
@@ -189,24 +189,6 @@ package gencores_pkg is
q_input_id_o : out std_logic_vector(f_log2_size(g_num_inputs)-1 downto 0));
end component;
- -- Read during write has an undefined result
- component gc_dual_clock_ram is
- generic(
- addr_width : natural := 4;
- data_width : natural := 32);
- port(
- -- write port
- w_clk_i : in std_logic;
- w_en_i : in std_logic;
- w_addr_i : in std_logic_vector(addr_width-1 downto 0);
- w_data_i : in std_logic_vector(data_width-1 downto 0);
- -- read port
- r_clk_i : in std_logic;
- r_en_i : in std_logic;
- r_addr_i : in std_logic_vector(addr_width-1 downto 0);
- r_data_o : out std_logic_vector(data_width-1 downto 0));
- end component;
-
-- A 'Wes' FIFO. Generic FIFO using inferred memory.
-- Supports clock domain crossing
-- Should be safe from fast->slow or reversed