From bb12daa412a9ec0eefc3b12eb088910609167975 Mon Sep 17 00:00:00 2001
From: Matthieu Cattin <matthieu.cattin@cern.ch>
Date: Wed, 30 Oct 2013 14:32:14 +0100
Subject: [PATCH] genrams: Fix constants assigned to input ports ->
incompatible with VHDL'93.
Replaced by a function taking the number of bits in parameter and returning a vector.
---
modules/genrams/genram_pkg.vhd | 10 +++++++++-
modules/genrams/xilinx/generic_simple_dpram.vhd | 7 ++++---
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/modules/genrams/genram_pkg.vhd b/modules/genrams/genram_pkg.vhd
index 9f3ecf8b..3fa5e6c9 100644
--- a/modules/genrams/genram_pkg.vhd
+++ b/modules/genrams/genram_pkg.vhd
@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
--- Last update: 2012-01-24
+-- Last update: 2013-10-30
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
@@ -38,11 +38,13 @@
library ieee;
use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
package genram_pkg is
function f_log2_size (A : natural) return natural;
function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector;
+ function f_zeros (size : integer) return std_logic_vector;
type t_generic_ram_init is array (integer range <>, integer range <>) of std_logic;
@@ -212,5 +214,11 @@ package body genram_pkg is
return tmp;
end f_gen_dummy_vec;
+ function f_zeros(size : integer)
+ return std_logic_vector is
+ begin
+ return std_logic_vector(to_unsigned(0, size));
+ end f_zeros;
+
end genram_pkg;
diff --git a/modules/genrams/xilinx/generic_simple_dpram.vhd b/modules/genrams/xilinx/generic_simple_dpram.vhd
index 049b96c1..5eb14729 100644
--- a/modules/genrams/xilinx/generic_simple_dpram.vhd
+++ b/modules/genrams/xilinx/generic_simple_dpram.vhd
@@ -6,7 +6,7 @@
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-03-04
--- Last update: 2013-03-04
+-- Last update: 2013-10-30
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
@@ -70,6 +70,7 @@ end generic_simple_dpram;
architecture syn of generic_simple_dpram is
+
begin
-- Works well enough until a Xilinx guru can optimize it.
@@ -90,10 +91,10 @@ begin
da_i => da_i,
qa_o => open,
clkb_i => clkb_i,
- bweb_i => (others => '0'),
+ bweb_i => f_zeros((g_data_width+7)/8),
web_i => '0',
ab_i => ab_i,
- db_i => (others => '0'),
+ db_i => f_zeros(g_data_width),
qb_o => qb_o);
end syn;
--
GitLab