diff --git a/modules/genrams/genram_pkg.vhd b/modules/genrams/genram_pkg.vhd
index 9f3ecf8b4fb4b1cb60035cf9b6571f79ea5f2b2b..3fa5e6c9ce429642ae2f39f6b55f9919d158c448 100644
--- a/modules/genrams/genram_pkg.vhd
+++ b/modules/genrams/genram_pkg.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2011-01-25
--- Last update: 2012-01-24
+-- Last update: 2013-10-30
 -- Platform   : 
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -38,11 +38,13 @@
 
 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 
 package genram_pkg is
 
   function f_log2_size (A       : natural) return natural;
   function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector;
+  function f_zeros (size : integer) return std_logic_vector;
 
   type t_generic_ram_init is array (integer range <>, integer range <>) of std_logic;
   
@@ -212,5 +214,11 @@ package body genram_pkg is
     return tmp;
   end f_gen_dummy_vec;
 
+  function f_zeros(size : integer)
+    return std_logic_vector is
+  begin
+    return std_logic_vector(to_unsigned(0, size));
+  end f_zeros;
+
 
 end genram_pkg;
diff --git a/modules/genrams/xilinx/generic_simple_dpram.vhd b/modules/genrams/xilinx/generic_simple_dpram.vhd
index 049b96c1b59edd5752766cf23a3c28e6511f5fcc..5eb14729ad96a946f65c51277f8ff519b116ab63 100644
--- a/modules/genrams/xilinx/generic_simple_dpram.vhd
+++ b/modules/genrams/xilinx/generic_simple_dpram.vhd
@@ -6,7 +6,7 @@
 -- Author     : Wesley W. Terpstra
 -- Company    : GSI
 -- Created    : 2013-03-04
--- Last update: 2013-03-04
+-- Last update: 2013-10-30
 -- Platform   : 
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -70,6 +70,7 @@ end generic_simple_dpram;
 
 
 architecture syn of generic_simple_dpram is
+
 begin
 
   -- Works well enough until a Xilinx guru can optimize it.
@@ -90,10 +91,10 @@ begin
       da_i    => da_i,
       qa_o    => open,
       clkb_i  => clkb_i,
-      bweb_i  => (others => '0'),
+      bweb_i  => f_zeros((g_data_width+7)/8),
       web_i   => '0',
       ab_i    => ab_i,
-      db_i    => (others => '0'),
+      db_i    => f_zeros(g_data_width),
       qb_o    => qb_o);
 
 end syn;