diff --git a/modules/genrams/altera/generic_dpram.vhd b/modules/genrams/altera/generic_dpram.vhd
index eeb2b913193a890edbc0876bce0cd53c3e5f1de9..1df91c324a3e3b44e5efac06e518e6c048276ea5 100644
--- a/modules/genrams/altera/generic_dpram.vhd
+++ b/modules/genrams/altera/generic_dpram.vhd
@@ -78,7 +78,7 @@ architecture syn of generic_dpram is
   type t_ram_type_bs is array (0 to g_size - 1) of t_ram_word_bs;
 
   function f_memarray_to_ramtype(arr : t_meminit_array) return t_ram_type is
-    variable tmp    : t_ram_type;
+    variable tmp    : t_ram_type := (others => (others => '0'));
     variable n, pos : integer;
   begin
     pos := 0;
@@ -97,7 +97,7 @@ architecture syn of generic_dpram is
   end f_memarray_to_ramtype;
 
   function f_memarray_to_ramtype_bs(arr : t_meminit_array) return t_ram_type_bs is
-    variable tmp    : t_ram_type_bs;
+    variable tmp    : t_ram_type_bs := (others => (others => (others => '0')));
     variable n, pos : integer;
   begin
     pos := 0;
@@ -124,8 +124,8 @@ architecture syn of generic_dpram is
     end if;
   end f_file_contents;
   
-  signal ram : t_ram_type := f_memarray_to_ramtype(f_file_contents);
-  signal ram_bs : t_ram_type_bs:=f_memarray_to_ramtype_bs(f_file_contents);
+  signal ram    : t_ram_type    := f_memarray_to_ramtype   (f_file_contents);
+  signal ram_bs : t_ram_type_bs := f_memarray_to_ramtype_bs(f_file_contents);
   
   signal q_local_a       : t_ram_word_bs;
   signal q_local_b       : t_ram_word_bs;
diff --git a/modules/genrams/altera/generic_spram.vhd b/modules/genrams/altera/generic_spram.vhd
index 70ab1666b1cbf27686450622f5755deeab55419b..8bc1875dec41b44dda509f1c8970d9fac7e33371 100644
--- a/modules/genrams/altera/generic_spram.vhd
+++ b/modules/genrams/altera/generic_spram.vhd
@@ -75,8 +75,8 @@ architecture syn of generic_spram is
   type t_ram_word_bs is array (0 to 7) of std_logic_vector(7 downto 0);
   type t_ram_type_bs is array (0 to g_size - 1) of t_ram_word_bs;
 
-  signal ram     : t_ram_type;
-  signal ram_bs  : t_ram_type_bs;
+  signal ram     : t_ram_type    := (others => (others => '0'));
+  signal ram_bs  : t_ram_type_bs := (others => (others => (others => '0')));
   signal q_local : t_ram_word_bs;
 
   signal bwe_int : std_logic_vector(7 downto 0);