From abb8cf3b8f8c7c331a85af8de65f872085d00f45 Mon Sep 17 00:00:00 2001
From: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
Date: Wed, 5 Oct 2011 15:50:23 +0200
Subject: [PATCH] wishbone: wb_tics: added structized wrapped and WB slave
adapter
---
modules/wishbone/wb_simple_timer/Manifest.py | 2 +-
modules/wishbone/wb_simple_timer/wb_tics.vhd | 71 +++++++++++++-----
modules/wishbone/wb_simple_timer/xwb_tics.vhd | 73 +++++++++++++++++++
3 files changed, 127 insertions(+), 19 deletions(-)
create mode 100644 modules/wishbone/wb_simple_timer/xwb_tics.vhd
diff --git a/modules/wishbone/wb_simple_timer/Manifest.py b/modules/wishbone/wb_simple_timer/Manifest.py
index 2bd835b9..ed5a1b24 100644
--- a/modules/wishbone/wb_simple_timer/Manifest.py
+++ b/modules/wishbone/wb_simple_timer/Manifest.py
@@ -1 +1 @@
-files = ["wb_tics.vhd"];
\ No newline at end of file
+files = ["wb_tics.vhd", "xwb_tics.vhd"];
\ No newline at end of file
diff --git a/modules/wishbone/wb_simple_timer/wb_tics.vhd b/modules/wishbone/wb_simple_timer/wb_tics.vhd
index e780b526..71e0417a 100644
--- a/modules/wishbone/wb_simple_timer/wb_tics.vhd
+++ b/modules/wishbone/wb_simple_timer/wb_tics.vhd
@@ -6,9 +6,9 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-04-03
--- Last update: 2011-06-16
+-- Last update: 2011-10-04
-- Platform : FPGA-generics
--- Standard : VHDL
+-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-- WB_TICS is a simple counter with wishbone interface. Each step of a counter
@@ -20,6 +20,7 @@
-- Revisions :
-- Date Version Author Description
-- 2011-04-03 1.0 greg.d Created
+-- 2011-10-04 1.1 twlostow added wishbone adapter
-------------------------------------------------------------------------------
library ieee;
@@ -27,24 +28,28 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
+use work.wishbone_pkg.all;
+
entity wb_tics is
generic (
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD;
g_period : integer);
port(
rst_n_i : in std_logic;
-
clk_sys_i : in std_logic;
- wb_addr_i : in std_logic_vector(1 downto 0);
- wb_data_i : in std_logic_vector(31 downto 0);
- wb_data_o : out std_logic_vector(31 downto 0);
+ wb_adr_i : in std_logic_vector(3 downto 0);
+ wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
- wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
- wb_ack_o : out std_logic
+ wb_ack_o : out std_logic;
+ wb_stall_o: out std_logic
);
end wb_tics;
@@ -56,8 +61,38 @@ architecture behaviour of wb_tics is
signal cntr_tics : unsigned(31 downto 0);
signal cntr_overflow : std_logic;
+ signal wb_in : t_wishbone_slave_in;
+ signal wb_out : t_wishbone_slave_out;
+
+ signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
begin
+ resized_addr(3 downto 0) <= wb_adr_i;
+ resized_addr(c_wishbone_address_width-1 downto 4) <= (others => '0');
+
+ U_Adapter : wb_slave_adapter
+ generic map (
+ g_master_use_struct => true,
+ g_master_mode => CLASSIC,
+ g_master_granularity => WORD,
+ g_slave_use_struct => false,
+ g_slave_mode => g_interface_mode,
+ g_slave_granularity => g_address_granularity)
+ port map (
+ clk_sys_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+ master_i => wb_out,
+ master_o => wb_in,
+ sl_adr_i => resized_addr,
+ sl_dat_i => wb_dat_i,
+ sl_sel_i => wb_sel_i,
+ sl_cyc_i => wb_cyc_i,
+ sl_stb_i => wb_stb_i,
+ sl_we_i => wb_we_i,
+ sl_dat_o => wb_dat_o,
+ sl_ack_o => wb_ack_o,
+ sl_stall_o => wb_stall_o);
+
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
@@ -93,22 +128,22 @@ begin
begin
if rising_edge(clk_sys_i) then
if(rst_n_i = '0') then
- wb_ack_o <= '0';
- wb_data_o <= (others => '0');
+ wb_out.ack <= '0';
+ wb_out.dat <= (others => '0');
else
- if(wb_stb_i = '1' and wb_cyc_i = '1') then
- if(wb_we_i = '0') then
- case wb_addr_i is
+ if(wb_in.stb = '1' and wb_in.cyc = '1') then
+ if(wb_in.we = '0') then
+ case wb_in.adr(1 downto 0) is
when c_TICS_REG =>
- wb_data_o <= std_logic_vector(cntr_tics);
+ wb_out.dat <= std_logic_vector(cntr_tics);
when others =>
- wb_data_o <= (others => '0');
+ wb_out.dat <= (others => '0');
end case;
end if;
- wb_ack_o <= '1';
+ wb_out.ack <= '1';
else
- wb_data_o <= (others => '0');
- wb_ack_o <= '0';
+ wb_out.dat <= (others => '0');
+ wb_out.ack <= '0';
end if;
end if;
end if;
diff --git a/modules/wishbone/wb_simple_timer/xwb_tics.vhd b/modules/wishbone/wb_simple_timer/xwb_tics.vhd
new file mode 100644
index 00000000..800cb35e
--- /dev/null
+++ b/modules/wishbone/wb_simple_timer/xwb_tics.vhd
@@ -0,0 +1,73 @@
+-- todo: configurable interrupt, output compare, PWM?
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wishbone_pkg.all;
+
+entity xwb_tics is
+ generic(
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD;
+ g_period : integer
+ );
+
+ port(
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ -- Wishbone
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+ desc_o : out t_wishbone_device_descriptor
+
+ );
+
+end xwb_tics;
+
+architecture rtl of xwb_tics is
+
+ component wb_tics
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_address_granularity : t_wishbone_address_granularity := WORD;
+ g_period : integer);
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ wb_adr_i : in std_logic_vector(3 downto 0);
+ wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic);
+ end component;
+
+begin
+
+ U_Tics : wb_tics
+ generic map (
+ g_interface_mode => g_interface_mode,
+ g_address_granularity => g_address_granularity,
+ g_period => g_period)
+ port map (
+ rst_n_i => rst_n_i,
+ clk_sys_i => clk_sys_i,
+ wb_adr_i => slave_i.adr(3 downto 0),
+ wb_dat_i => slave_i.Dat,
+ wb_dat_o => slave_o.dat,
+ wb_cyc_i => slave_i.cyc,
+ wb_sel_i => slave_i.sel,
+ wb_stb_i => slave_i.stb,
+ wb_we_i => slave_i.we,
+ wb_ack_o => slave_o.ack,
+ wb_stall_o => slave_o.stall);
+
+ slave_o.err <= '0';
+ slave_o.int <= '0';
+ slave_o.rty <= '0';
+
+end rtl;
--
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