From aa3570a74138cfc3fdbf52d9b972894f698b0d7d Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <w.terpstra@gsi.de>
Date: Wed, 12 Aug 2015 13:16:00 +0200
Subject: [PATCH] pcie_wb: reduce FIFO depth to decrease max wait times (fixes
flash)
PCIe must respond to reads within a fairly tight deadline.
If we allow too many enqueued operations, that deadline may be missed.
Using a smaller FIFO depth causes back-pressure on the PCIe bus, slowing the
request arrival rate and thus increasing the time a single WB op can take.
Concretely, this makes it possible to perform an SPI flash write within
the PCIe time limit.
---
platform/altera/wb_pcie/pcie_wb.vhd | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/platform/altera/wb_pcie/pcie_wb.vhd b/platform/altera/wb_pcie/pcie_wb.vhd
index f4d7df6d..033e935f 100644
--- a/platform/altera/wb_pcie/pcie_wb.vhd
+++ b/platform/altera/wb_pcie/pcie_wb.vhd
@@ -174,7 +174,7 @@ begin
end process;
PC_to_FPGA_clock_crossing : xwb_clock_crossing
- generic map(g_size => 256) port map(
+ generic map(g_size => 8) port map(
slave_clk_i => internal_wb_clk,
slave_rst_n_i => internal_wb_rstn,
slave_i => int_slave_i,
@@ -192,7 +192,7 @@ begin
int_slave_i.adr(r_addr'right-1 downto 0) <= wb_adr(r_addr'right-1 downto 0);
FPGA_to_PC_clock_crossing : xwb_clock_crossing
- generic map(g_size => 256) port map(
+ generic map(g_size => 8) port map(
slave_clk_i => slave_clk_i,
slave_rst_n_i => slave_rstn_i,
slave_i => slave_i,
--
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