diff --git a/CHANGELOG.rst b/CHANGELOG.rst
index 317a3c41020cf21f6b209751f74bcc98ddb14761..2d16adcea890d2c5db37bfa9477b66347a30a25b 100644
--- a/CHANGELOG.rst
+++ b/CHANGELOG.rst
@@ -9,6 +9,15 @@ Change Log
 - Format inspired by: `Keep a Changelog <https://keepachangelog.com/en/1.0.0/>`_
 - Versioning scheme follows: `Semantic Versioning <https://semver.org/spec/v2.0.0.html>`_
 
+Unreleased
+==========
+https://ohwr.org/project/general-cores/compare/master...proposed_master
+
+Fixed
+-----
+- [hdl] avoid f_log2() circular dependencies in gc_extend_pulse.
+
+
 1.0.4 - 2020-03-26
 ==================
 https://www.ohwr.org/project/general-cores/tags/v1.0.4
diff --git a/modules/common/gc_extend_pulse.vhd b/modules/common/gc_extend_pulse.vhd
index c7c2314f539cf0ce955ed9adeecfb74dbf84a569..fd895284ce29d57498d1aebeeb7bad9642c27361 100644
--- a/modules/common/gc_extend_pulse.vhd
+++ b/modules/common/gc_extend_pulse.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2009-09-01
--- Last update: 2012-06-19
+-- Last update: 2020-03-30
 -- Platform   : FPGA-generic
 -- Standard   : VHDL '93
 -------------------------------------------------------------------------------
@@ -41,7 +41,6 @@ use ieee.NUMERIC_STD.all;
 
 library work;
 use work.gencores_pkg.all;
-use work.genram_pkg.all;
 
 entity gc_extend_pulse is
   
@@ -60,7 +59,7 @@ end gc_extend_pulse;
 
 architecture rtl of gc_extend_pulse is
 
-  signal cntr : unsigned(f_log2_size(g_width)-1 downto 0);
+  signal cntr : unsigned(f_log2_ceil(g_width)-1 downto 0);
   signal extended_int : std_logic;
   
 begin  -- rtl