From 95f5a4dfa852556543764e2eb3bc422e8dd140ec Mon Sep 17 00:00:00 2001
From: Evangelia Gousiou <egousiou@cern.ch>
Date: Fri, 10 Feb 2017 18:41:47 +0100
Subject: [PATCH] added gc_dyn_extend_pulse.vhd where the width of the extended
pulse comes as an input rather than a generic.
---
modules/common/gc_dyn_extend_pulse.vhd | 95 ++++++++++++++++++++++++++
modules/common/gencores_pkg.vhd | 11 +++
2 files changed, 106 insertions(+)
create mode 100644 modules/common/gc_dyn_extend_pulse.vhd
diff --git a/modules/common/gc_dyn_extend_pulse.vhd b/modules/common/gc_dyn_extend_pulse.vhd
new file mode 100644
index 00000000..b1ad6874
--- /dev/null
+++ b/modules/common/gc_dyn_extend_pulse.vhd
@@ -0,0 +1,95 @@
+-------------------------------------------------------------------------------
+-- Title : Pulse width extender
+-- Project : General Cores library
+-------------------------------------------------------------------------------
+-- File : gc_extend_pulse.vhd
+-- Author : Tomasz Wlostowski
+-- Company : CERN
+-- Created : 2009-09-01
+-- Last update: 2012-06-19
+-- Platform : FPGA-generic
+-- Standard : VHDL '93
+-------------------------------------------------------------------------------
+-- Description:
+-- Synchronous pulse extender. Generates a pulse of programmable width upon
+-- detection of a rising edge in the input.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2009-09-01 0.9 twlostow Created
+-- 2011-04-18 1.0 twlostow Added comments & header
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.NUMERIC_STD.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+
+entity gc_dyn_extend_pulse is
+ generic
+ (
+ -- Number of bits of the len_i input
+ g_len_width : natural := 10
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ -- input pulse (synchronous to clk_i)
+ pulse_i : in std_logic;
+ -- output pulse length in clk_i cycles
+ len_i : in std_logic_vector(g_len_width-1 downto 0);
+ -- extended output pulse
+ extended_o : out std_logic := '0');
+end gc_dyn_extend_pulse;
+
+architecture rtl of gc_dyn_extend_pulse is
+
+ signal cntr : unsigned(g_len_width-1 downto 0);
+ signal extended_int : std_logic;
+
+begin -- rtl
+
+ extend : process (clk_i, rst_n_i)
+ begin -- process extend
+ if rst_n_i = '0' then -- asynchronous reset (active low)
+ extended_int <= '0';
+ cntr <= (others => '0');
+ elsif clk_i'event and clk_i = '1' then -- rising clock edge
+ if(pulse_i = '1') then
+ extended_int <= '1';
+ cntr <= unsigned(len_i) - 2;
+ elsif cntr /= to_unsigned(0, cntr'length) then
+ cntr <= cntr - 1;
+ else
+ extended_int <= '0';
+ end if;
+ end if;
+ end process extend;
+
+ extended_o <= pulse_i or extended_int;
+
+end rtl;
+
diff --git a/modules/common/gencores_pkg.vhd b/modules/common/gencores_pkg.vhd
index e5660e0f..a84fa7de 100644
--- a/modules/common/gencores_pkg.vhd
+++ b/modules/common/gencores_pkg.vhd
@@ -72,6 +72,17 @@ package gencores_pkg is
extended_o : out std_logic);
end component;
+ component gc_dyn_extend_pulse is
+ generic (
+ g_len_width : natural := 10);
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ pulse_i : in std_logic;
+ len_i : in std_logic_vector(g_len_width-1 downto 0);
+ extended_o : out std_logic := '0');
+ end component;
+
------------------------------------------------------------------------------
-- CRC generator
------------------------------------------------------------------------------
--
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