From 824a460bd5b4ee3dc12c98e53bade2b3095e5f88 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <w.terpstra@gsi.de>
Date: Wed, 2 Nov 2011 16:49:58 +0100
Subject: [PATCH] Modelsim requires all wires explicitly declared.

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
---
 modules/wishbone/wb_lm32/platform/xilinx/jtag_tap.v | 1 +
 1 file changed, 1 insertion(+)

diff --git a/modules/wishbone/wb_lm32/platform/xilinx/jtag_tap.v b/modules/wishbone/wb_lm32/platform/xilinx/jtag_tap.v
index 10a347ad..30641168 100644
--- a/modules/wishbone/wb_lm32/platform/xilinx/jtag_tap.v
+++ b/modules/wishbone/wb_lm32/platform/xilinx/jtag_tap.v
@@ -12,6 +12,7 @@ module jtag_tap(
 
 // Unfortunately the exit1 state for DR (e1dr) is mising
 // We can simulate it by interpretting 'update' as e1dr and delaying 'update'
+wire sel;
 wire g_capture;
 wire g_shift;
 wire g_update;
-- 
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