diff --git a/modules/genrams/altera/Manifest.py b/modules/genrams/altera/Manifest.py
index c86aa8ff89d004160f519e2199c41c586acb25a3..b82d2496ccc3d8cd5f3034381ff97c47f00f3339 100644
--- a/modules/genrams/altera/Manifest.py
+++ b/modules/genrams/altera/Manifest.py
@@ -3,4 +3,5 @@ files = [
 "generic_simple_dpram.vhd",
 "generic_dpram.vhd",
 "generic_spram.vhd",
-"generic_sync_fifo.vhd"]
+"generic_sync_fifo.vhd",
+"gc_shiftreg.vhd"]
diff --git a/modules/genrams/altera/gc_shiftreg.vhd b/modules/genrams/altera/gc_shiftreg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..30386a1e330f52880edebaf22b29fd2fe2212ee3
--- /dev/null
+++ b/modules/genrams/altera/gc_shiftreg.vhd
@@ -0,0 +1,38 @@
+library ieee;
+
+use ieee.STD_LOGIC_1164.all;
+use ieee.NUMERIC_STD.all;
+
+use work.genram_pkg.all;
+
+entity gc_shiftreg is
+  generic (
+    g_size : integer);
+  port (
+    clk_i : in  std_logic;
+    en_i  : in  std_logic;
+    d_i   : in  std_logic;
+    q_o   : out std_logic;
+    a_i   : in  std_logic_vector(f_log2_size(g_size)-1 downto 0));
+end gc_shiftreg;
+
+
+architecture rtl of gc_shiftreg is
+  signal a  : std_logic_vector(4 downto 0);
+  signal sr : std_logic_vector(g_size-1 downto 0);
+begin
+
+  a <= std_logic_vector(resize(unsigned(a_i), 5));
+  
+  p_srl : process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if en_i = '1' then
+        sr <= sr(sr'left - 1 downto 0) & d_i;
+      end if;
+    end if;
+  end process;
+
+  q_o <= sr(TO_INTEGER(unsigned(a_i)));
+
+end rtl;