From 7cd090ee916a43022f8b9c5e967846a7d721a91f Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <w.terpstra@gsi.de>
Date: Thu, 5 Apr 2012 10:09:19 +0200
Subject: [PATCH] Move HDL to a subfolder Add driver stub code

---
 altera_pcie.qip => hdl/altera_pcie.qip        |   0
 altera_pcie.sdc => hdl/altera_pcie.sdc        |   0
 altera_pcie.vhd => hdl/altera_pcie.vhd        |   0
 .../altera_pcie_core.vhd                      |   0
 .../altera_pcie_pll.qip                       |   0
 .../altera_pcie_pll.vhd                       |   0
 .../altera_pcie_serdes.vhd                    |   0
 .../altera_reconfig.qip                       |   0
 .../altera_reconfig.vhd                       |   0
 flash_loader.qip => hdl/flash_loader.qip      |   0
 flash_loader.vhd => hdl/flash_loader.vhd      |   0
 .../altpcie_64b_x1_pipen1b.v                  | Bin
 .../altpcie_64b_x4_pipen1b.v                  | Bin
 .../altpcie_64b_x8_pipen1b.v                  | Bin
 .../altpcie_hip_256_pipen1b.v                 |   0
 .../altpcie_hip_pipen1b.v                     | Bin
 .../altpcie_pclk_align.v                      |   0
 .../altpcie_pclk_pll.v                        |   0
 .../altpcie_phasefifo.v                       |   0
 .../altpcie_pll_100_125.v                     |   0
 .../altpcie_pll_100_250.v                     |   0
 .../altpcie_pll_125_250.v                     |   0
 .../altpcie_pll_15625_125.v                   |   0
 .../altpcie_pll_250_100.v                     |   0
 .../altpcie_pll_phy0.v                        |   0
 .../altpcie_pll_phy1_62p5.v                   |   0
 .../altpcie_pll_phy2.v                        |   0
 .../altpcie_pll_phy3_62p5.v                   |   0
 .../altpcie_pll_phy4_62p5.v                   |   0
 .../altpcie_pll_phy5_62p5.v                   |   0
 .../altpcie_reconfig_3cgx.v                   |   0
 .../altpcie_reconfig_4sgx.v                   |   0
 .../altpcie_rs_serdes.v                       |   0
 .../altpcie_serdes_1sgx_x1_12500.v            |   0
 .../altpcie_serdes_1sgx_x1_15625.v            |   0
 .../altpcie_serdes_1sgx_x4_12500.v            |   0
 .../altpcie_serdes_1sgx_x4_15625.v            |   0
 .../altpcie_serdes_2agx_x1d_gen1_08p.v        |   0
 .../altpcie_serdes_2agx_x1d_gen1_16p.v        |   0
 .../altpcie_serdes_2agx_x4d_gen1_08p.v        |   0
 .../altpcie_serdes_2agx_x4d_gen1_16p.v        |   0
 .../altpcie_serdes_2agx_x8d_gen1_08p.v        |   0
 .../altpcie_serdes_2sgx_x1d_10000.v           |   0
 .../altpcie_serdes_2sgx_x4d_10000.v           |   0
 .../altpcie_serdes_2sgx_x8d_10000.v           |   0
 .../altpcie_serdes_3cgx_x1d_gen1_08p.v        |   0
 .../altpcie_serdes_3cgx_x1d_gen1_16p.v        |   0
 .../altpcie_serdes_3cgx_x2d_gen1_08p.v        |   0
 .../altpcie_serdes_3cgx_x4d_gen1_08p.v        |   0
 .../altpcie_serdes_4sgx_x1d_gen1_08p.v        |   0
 .../altpcie_serdes_4sgx_x1d_gen1_16p.v        |   0
 .../altpcie_serdes_4sgx_x1d_gen2_08p.v        |   0
 .../altpcie_serdes_4sgx_x4d_gen1_08p.v        |   0
 .../altpcie_serdes_4sgx_x4d_gen1_16p.v        |   0
 .../altpcie_serdes_4sgx_x4d_gen2_08p.v        |   0
 .../altpcie_serdes_4sgx_x8d_gen1_08p.v        |   0
 .../altpcie_serdes_4sgx_x8d_gen2_08p.v        |   0
 .../altpcierd_reconfig_clk_pll.v              |   0
 .../pciexp1x125_ltssm.ocp                     | Bin
 .../pciexp4x125_ltssm.ocp                     | Bin
 .../pciexp64_dlink.ocp                        | Bin
 .../pciexp64_dlink.v                          | Bin
 .../pciexp64_trans.v                          | Bin
 .../pciexp_dcram.v                            | Bin
 .../pciexpx8f_confctrl.v                      | Bin
 .../pciexpx8f_ltssm.ocp                       | Bin
 .../pciexpx8f_pexreg.ocp                      | Bin
 pcie_wb.qpf => hdl/pcie_wb.qpf                |   0
 hdl/pcie_wb.qsf                               | 121 ++++++
 pcie_wb.sdc => hdl/pcie_wb.sdc                |   0
 pcie_wb.vhd => hdl/pcie_wb.vhd                |   2 +-
 pow_reset.vhd => hdl/pow_reset.vhd            |   0
 pcie_wb.qsf                                   | 366 ------------------
 73 files changed, 122 insertions(+), 367 deletions(-)
 rename altera_pcie.qip => hdl/altera_pcie.qip (100%)
 rename altera_pcie.sdc => hdl/altera_pcie.sdc (100%)
 rename altera_pcie.vhd => hdl/altera_pcie.vhd (100%)
 rename altera_pcie_core.vhd => hdl/altera_pcie_core.vhd (100%)
 rename altera_pcie_pll.qip => hdl/altera_pcie_pll.qip (100%)
 rename altera_pcie_pll.vhd => hdl/altera_pcie_pll.vhd (100%)
 rename altera_pcie_serdes.vhd => hdl/altera_pcie_serdes.vhd (100%)
 rename altera_reconfig.qip => hdl/altera_reconfig.qip (100%)
 rename altera_reconfig.vhd => hdl/altera_reconfig.vhd (100%)
 rename flash_loader.qip => hdl/flash_loader.qip (100%)
 rename flash_loader.vhd => hdl/flash_loader.vhd (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_64b_x1_pipen1b.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_64b_x4_pipen1b.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_64b_x8_pipen1b.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_hip_256_pipen1b.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_hip_pipen1b.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_pclk_align.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_pclk_pll.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_phasefifo.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_pll_100_125.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_pll_100_250.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_pll_125_250.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_pll_15625_125.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_pll_250_100.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_pll_phy0.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_pll_phy1_62p5.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_pll_phy2.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_pll_phy3_62p5.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_pll_phy4_62p5.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_pll_phy5_62p5.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_reconfig_3cgx.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_reconfig_4sgx.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_rs_serdes.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_1sgx_x1_12500.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_1sgx_x1_15625.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_1sgx_x4_12500.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_1sgx_x4_15625.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_2agx_x1d_gen1_08p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_2agx_x1d_gen1_16p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_2agx_x4d_gen1_08p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_2agx_x4d_gen1_16p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_2agx_x8d_gen1_08p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_2sgx_x1d_10000.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_2sgx_x4d_10000.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_2sgx_x8d_10000.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_3cgx_x1d_gen1_08p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_3cgx_x1d_gen1_16p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_3cgx_x2d_gen1_08p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_3cgx_x4d_gen1_08p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_4sgx_x1d_gen1_08p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_4sgx_x1d_gen1_16p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_4sgx_x1d_gen2_08p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_4sgx_x4d_gen1_08p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_4sgx_x4d_gen1_16p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_4sgx_x4d_gen2_08p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_4sgx_x8d_gen1_08p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcie_serdes_4sgx_x8d_gen2_08p.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/altpcierd_reconfig_clk_pll.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/pciexp1x125_ltssm.ocp (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/pciexp4x125_ltssm.ocp (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/pciexp64_dlink.ocp (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/pciexp64_dlink.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/pciexp64_trans.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/pciexp_dcram.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/pciexpx8f_confctrl.v (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/pciexpx8f_ltssm.ocp (100%)
 rename {ip_compiler_for_pci_express-library => hdl/ip_compiler_for_pci_express-library}/pciexpx8f_pexreg.ocp (100%)
 rename pcie_wb.qpf => hdl/pcie_wb.qpf (100%)
 create mode 100644 hdl/pcie_wb.qsf
 rename pcie_wb.sdc => hdl/pcie_wb.sdc (100%)
 rename pcie_wb.vhd => hdl/pcie_wb.vhd (99%)
 rename pow_reset.vhd => hdl/pow_reset.vhd (100%)
 delete mode 100644 pcie_wb.qsf

diff --git a/altera_pcie.qip b/hdl/altera_pcie.qip
similarity index 100%
rename from altera_pcie.qip
rename to hdl/altera_pcie.qip
diff --git a/altera_pcie.sdc b/hdl/altera_pcie.sdc
similarity index 100%
rename from altera_pcie.sdc
rename to hdl/altera_pcie.sdc
diff --git a/altera_pcie.vhd b/hdl/altera_pcie.vhd
similarity index 100%
rename from altera_pcie.vhd
rename to hdl/altera_pcie.vhd
diff --git a/altera_pcie_core.vhd b/hdl/altera_pcie_core.vhd
similarity index 100%
rename from altera_pcie_core.vhd
rename to hdl/altera_pcie_core.vhd
diff --git a/altera_pcie_pll.qip b/hdl/altera_pcie_pll.qip
similarity index 100%
rename from altera_pcie_pll.qip
rename to hdl/altera_pcie_pll.qip
diff --git a/altera_pcie_pll.vhd b/hdl/altera_pcie_pll.vhd
similarity index 100%
rename from altera_pcie_pll.vhd
rename to hdl/altera_pcie_pll.vhd
diff --git a/altera_pcie_serdes.vhd b/hdl/altera_pcie_serdes.vhd
similarity index 100%
rename from altera_pcie_serdes.vhd
rename to hdl/altera_pcie_serdes.vhd
diff --git a/altera_reconfig.qip b/hdl/altera_reconfig.qip
similarity index 100%
rename from altera_reconfig.qip
rename to hdl/altera_reconfig.qip
diff --git a/altera_reconfig.vhd b/hdl/altera_reconfig.vhd
similarity index 100%
rename from altera_reconfig.vhd
rename to hdl/altera_reconfig.vhd
diff --git a/flash_loader.qip b/hdl/flash_loader.qip
similarity index 100%
rename from flash_loader.qip
rename to hdl/flash_loader.qip
diff --git a/flash_loader.vhd b/hdl/flash_loader.vhd
similarity index 100%
rename from flash_loader.vhd
rename to hdl/flash_loader.vhd
diff --git a/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v b/hdl/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v b/hdl/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v b/hdl/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_hip_256_pipen1b.v b/hdl/ip_compiler_for_pci_express-library/altpcie_hip_256_pipen1b.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_hip_256_pipen1b.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_hip_256_pipen1b.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v b/hdl/ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_pclk_align.v b/hdl/ip_compiler_for_pci_express-library/altpcie_pclk_align.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_pclk_align.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_pclk_align.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_pclk_pll.v b/hdl/ip_compiler_for_pci_express-library/altpcie_pclk_pll.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_pclk_pll.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_pclk_pll.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_phasefifo.v b/hdl/ip_compiler_for_pci_express-library/altpcie_phasefifo.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_phasefifo.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_phasefifo.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_100_125.v b/hdl/ip_compiler_for_pci_express-library/altpcie_pll_100_125.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_pll_100_125.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_pll_100_125.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_100_250.v b/hdl/ip_compiler_for_pci_express-library/altpcie_pll_100_250.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_pll_100_250.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_pll_100_250.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_125_250.v b/hdl/ip_compiler_for_pci_express-library/altpcie_pll_125_250.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_pll_125_250.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_pll_125_250.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_15625_125.v b/hdl/ip_compiler_for_pci_express-library/altpcie_pll_15625_125.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_pll_15625_125.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_pll_15625_125.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_250_100.v b/hdl/ip_compiler_for_pci_express-library/altpcie_pll_250_100.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_pll_250_100.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_pll_250_100.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_phy0.v b/hdl/ip_compiler_for_pci_express-library/altpcie_pll_phy0.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_pll_phy0.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_pll_phy0.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_phy1_62p5.v b/hdl/ip_compiler_for_pci_express-library/altpcie_pll_phy1_62p5.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_pll_phy1_62p5.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_pll_phy1_62p5.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_phy2.v b/hdl/ip_compiler_for_pci_express-library/altpcie_pll_phy2.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_pll_phy2.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_pll_phy2.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_phy3_62p5.v b/hdl/ip_compiler_for_pci_express-library/altpcie_pll_phy3_62p5.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_pll_phy3_62p5.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_pll_phy3_62p5.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v b/hdl/ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_pll_phy5_62p5.v b/hdl/ip_compiler_for_pci_express-library/altpcie_pll_phy5_62p5.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_pll_phy5_62p5.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_pll_phy5_62p5.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v b/hdl/ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_reconfig_4sgx.v b/hdl/ip_compiler_for_pci_express-library/altpcie_reconfig_4sgx.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_reconfig_4sgx.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_reconfig_4sgx.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v b/hdl/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_rs_serdes.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_rs_serdes.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_15625.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_15625.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_15625.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_15625.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_15625.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_15625.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_15625.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_15625.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_08p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_08p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_08p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_08p.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_16p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_16p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_16p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_16p.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_08p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_08p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_08p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_08p.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_16p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_16p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_16p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_16p.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x8d_gen1_08p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x8d_gen1_08p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x8d_gen1_08p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x8d_gen1_08p.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x1d_10000.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x1d_10000.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x1d_10000.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x1d_10000.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x4d_10000.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x4d_10000.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x4d_10000.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x4d_10000.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x8d_10000.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x8d_10000.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x8d_10000.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x8d_10000.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_08p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_08p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_08p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_08p.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_16p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_16p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_16p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_16p.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x2d_gen1_08p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x2d_gen1_08p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x2d_gen1_08p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x2d_gen1_08p.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x4d_gen1_08p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x4d_gen1_08p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x4d_gen1_08p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x4d_gen1_08p.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_08p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_08p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_08p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_08p.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_16p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_16p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_16p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_16p.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen2_08p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen2_08p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen2_08p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen2_08p.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_08p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_08p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_08p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_08p.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_16p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_16p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_16p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_16p.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen2_08p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen2_08p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen2_08p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen2_08p.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen1_08p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen1_08p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen1_08p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen1_08p.v
diff --git a/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen2_08p.v b/hdl/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen2_08p.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen2_08p.v
rename to hdl/ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen2_08p.v
diff --git a/ip_compiler_for_pci_express-library/altpcierd_reconfig_clk_pll.v b/hdl/ip_compiler_for_pci_express-library/altpcierd_reconfig_clk_pll.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/altpcierd_reconfig_clk_pll.v
rename to hdl/ip_compiler_for_pci_express-library/altpcierd_reconfig_clk_pll.v
diff --git a/ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp b/hdl/ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp
similarity index 100%
rename from ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp
rename to hdl/ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp
diff --git a/ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp b/hdl/ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp
similarity index 100%
rename from ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp
rename to hdl/ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp
diff --git a/ip_compiler_for_pci_express-library/pciexp64_dlink.ocp b/hdl/ip_compiler_for_pci_express-library/pciexp64_dlink.ocp
similarity index 100%
rename from ip_compiler_for_pci_express-library/pciexp64_dlink.ocp
rename to hdl/ip_compiler_for_pci_express-library/pciexp64_dlink.ocp
diff --git a/ip_compiler_for_pci_express-library/pciexp64_dlink.v b/hdl/ip_compiler_for_pci_express-library/pciexp64_dlink.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/pciexp64_dlink.v
rename to hdl/ip_compiler_for_pci_express-library/pciexp64_dlink.v
diff --git a/ip_compiler_for_pci_express-library/pciexp64_trans.v b/hdl/ip_compiler_for_pci_express-library/pciexp64_trans.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/pciexp64_trans.v
rename to hdl/ip_compiler_for_pci_express-library/pciexp64_trans.v
diff --git a/ip_compiler_for_pci_express-library/pciexp_dcram.v b/hdl/ip_compiler_for_pci_express-library/pciexp_dcram.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/pciexp_dcram.v
rename to hdl/ip_compiler_for_pci_express-library/pciexp_dcram.v
diff --git a/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v b/hdl/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v
similarity index 100%
rename from ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v
rename to hdl/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v
diff --git a/ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp b/hdl/ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp
similarity index 100%
rename from ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp
rename to hdl/ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp
diff --git a/ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp b/hdl/ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp
similarity index 100%
rename from ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp
rename to hdl/ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp
diff --git a/pcie_wb.qpf b/hdl/pcie_wb.qpf
similarity index 100%
rename from pcie_wb.qpf
rename to hdl/pcie_wb.qpf
diff --git a/hdl/pcie_wb.qsf b/hdl/pcie_wb.qsf
new file mode 100644
index 00000000..6327036c
--- /dev/null
+++ b/hdl/pcie_wb.qsf
@@ -0,0 +1,121 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2011 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Full Version
+# Date created = 11:17:02  March 30, 2012
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		pcie_wb_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Arria II GX"
+set_global_assignment -name DEVICE EP2AGX125DF25C6ES
+set_global_assignment -name TOP_LEVEL_ENTITY pcie_wb
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:17:02  MARCH 30, 2012"
+set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP1"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_location_assignment PIN_D11 -to pcie_clk125_i
+set_location_assignment PIN_U23 -to pcie_refclk_i
+set_location_assignment PIN_W1 -to pcie_rstn_i
+set_location_assignment PIN_N23 -to pcie_rx_i[3]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[3]
+set_location_assignment PIN_N24 -to "pcie_rx_i[3](n)"
+set_location_assignment PIN_R23 -to pcie_rx_i[2]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[2]
+set_location_assignment PIN_R24 -to "pcie_rx_i[2](n)"
+set_location_assignment PIN_W23 -to pcie_rx_i[1]
+set_location_assignment PIN_AA23 -to pcie_rx_i[0]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[0]
+set_location_assignment PIN_AA24 -to "pcie_rx_i[0](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[1]
+set_location_assignment PIN_W24 -to "pcie_rx_i[1](n)"
+set_location_assignment PIN_M21 -to pcie_tx_o[3]
+set_location_assignment PIN_P21 -to pcie_tx_o[2]
+set_location_assignment PIN_V21 -to pcie_tx_o[1]
+set_location_assignment PIN_Y21 -to pcie_tx_o[0]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[0]
+set_location_assignment PIN_Y22 -to "pcie_tx_o[0](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[1]
+set_location_assignment PIN_V22 -to "pcie_tx_o[1](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[2]
+set_location_assignment PIN_P22 -to "pcie_tx_o[2](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[3]
+set_location_assignment PIN_M22 -to "pcie_tx_o[3](n)"
+set_instance_assignment -name IO_STANDARD LVDS -to pcie_clk125_i
+set_location_assignment PIN_C11 -to "pcie_clk125_i(n)"
+set_instance_assignment -name IO_STANDARD HCSL -to pcie_refclk_i
+set_location_assignment PIN_U24 -to "pcie_refclk_i(n)"
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to pcie_rstn_i
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name USE_SIGNALTAP_FILE stp2.stp
+set_location_assignment PIN_AB10 -to led_o[0]
+set_location_assignment PIN_AA10 -to led_o[1]
+set_location_assignment PIN_W10 -to led_o[2]
+set_location_assignment PIN_W9 -to led_o[3]
+set_location_assignment PIN_AB7 -to led_o[4]
+set_location_assignment PIN_AA7 -to led_o[5]
+set_location_assignment PIN_V9 -to led_o[6]
+set_location_assignment PIN_U9 -to led_o[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[7]
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "ACTIVE SERIAL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHZ
+set_global_assignment -name VHDL_FILE pow_reset.vhd
+set_global_assignment -name QIP_FILE altera_pcie.qip
+set_global_assignment -name VHDL_FILE pcie_wb.vhd
+set_global_assignment -name QIP_FILE altera_reconfig.qip
+set_global_assignment -name QIP_FILE altera_pcie_pll.qip
+set_global_assignment -name SDC_FILE pcie_wb.sdc
+set_global_assignment -name SIGNALTAP_FILE stp2.stp
+set_global_assignment -name QIP_FILE flash_loader.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/pcie_wb.sdc b/hdl/pcie_wb.sdc
similarity index 100%
rename from pcie_wb.sdc
rename to hdl/pcie_wb.sdc
diff --git a/pcie_wb.vhd b/hdl/pcie_wb.vhd
similarity index 99%
rename from pcie_wb.vhd
rename to hdl/pcie_wb.vhd
index 3f3b0e56..22e7ec24 100644
--- a/pcie_wb.vhd
+++ b/hdl/pcie_wb.vhd
@@ -207,7 +207,7 @@ architecture rtl of pcie_wb is
   
 begin
 
-	test_in <=  "0000000000000000000000000000000010001000";	-- disable low power state negotiation
+	test_in <=  (others => '0'); -- ))"0000000000000000000000000000000010001000";	-- disable low power state negotiation
 					
 
   reset : pow_reset
diff --git a/pow_reset.vhd b/hdl/pow_reset.vhd
similarity index 100%
rename from pow_reset.vhd
rename to hdl/pow_reset.vhd
diff --git a/pcie_wb.qsf b/pcie_wb.qsf
deleted file mode 100644
index ec70bfd9..00000000
--- a/pcie_wb.qsf
+++ /dev/null
@@ -1,366 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2011 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 32-bit
-# Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Full Version
-# Date created = 11:17:02  March 30, 2012
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		pcie_wb_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Arria II GX"
-set_global_assignment -name DEVICE EP2AGX125DF25C6ES
-set_global_assignment -name TOP_LEVEL_ENTITY pcie_wb
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP1"
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:17:02  MARCH 30, 2012"
-set_global_assignment -name LAST_QUARTUS_VERSION 11.1
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 2
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
-set_location_assignment PIN_D11 -to pcie_clk125_i
-set_location_assignment PIN_U23 -to pcie_refclk_i
-set_location_assignment PIN_W1 -to pcie_rstn_i
-set_location_assignment PIN_N23 -to pcie_rx_i[3]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[3]
-set_location_assignment PIN_N24 -to "pcie_rx_i[3](n)"
-set_location_assignment PIN_R23 -to pcie_rx_i[2]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[2]
-set_location_assignment PIN_R24 -to "pcie_rx_i[2](n)"
-set_location_assignment PIN_W23 -to pcie_rx_i[1]
-set_location_assignment PIN_AA23 -to pcie_rx_i[0]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[0]
-set_location_assignment PIN_AA24 -to "pcie_rx_i[0](n)"
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_rx_i[1]
-set_location_assignment PIN_W24 -to "pcie_rx_i[1](n)"
-set_location_assignment PIN_M21 -to pcie_tx_o[3]
-set_location_assignment PIN_P21 -to pcie_tx_o[2]
-set_location_assignment PIN_V21 -to pcie_tx_o[1]
-set_location_assignment PIN_Y21 -to pcie_tx_o[0]
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[0]
-set_location_assignment PIN_Y22 -to "pcie_tx_o[0](n)"
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[1]
-set_location_assignment PIN_V22 -to "pcie_tx_o[1](n)"
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[2]
-set_location_assignment PIN_P22 -to "pcie_tx_o[2](n)"
-set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to pcie_tx_o[3]
-set_location_assignment PIN_M22 -to "pcie_tx_o[3](n)"
-set_instance_assignment -name IO_STANDARD LVDS -to pcie_clk125_i
-set_location_assignment PIN_C11 -to "pcie_clk125_i(n)"
-set_instance_assignment -name IO_STANDARD HCSL -to pcie_refclk_i
-set_location_assignment PIN_U24 -to "pcie_refclk_i(n)"
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to pcie_rstn_i
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name ENABLE_SIGNALTAP ON
-set_global_assignment -name USE_SIGNALTAP_FILE stp2.stp
-set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "altera_pcie:pcie|core_clk_out" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=M9K" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=512" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=512" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
-set_location_assignment PIN_AB10 -to led_o[0]
-set_location_assignment PIN_AA10 -to led_o[1]
-set_location_assignment PIN_W10 -to led_o[2]
-set_location_assignment PIN_W9 -to led_o[3]
-set_location_assignment PIN_AB7 -to led_o[4]
-set_location_assignment PIN_AA7 -to led_o[5]
-set_location_assignment PIN_V9 -to led_o[6]
-set_location_assignment PIN_U9 -to led_o[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led_o[7]
-set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
-set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "ACTIVE SERIAL"
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHZ
-set_global_assignment -name VHDL_FILE pow_reset.vhd
-set_global_assignment -name QIP_FILE altera_pcie.qip
-set_global_assignment -name VHDL_FILE pcie_wb.vhd
-set_global_assignment -name QIP_FILE altera_reconfig.qip
-set_global_assignment -name QIP_FILE altera_pcie_pll.qip
-set_global_assignment -name SDC_FILE pcie_wb.sdc
-set_global_assignment -name SIGNALTAP_FILE stp2.stp
-set_global_assignment -name QIP_FILE flash_loader.qip
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.CHECK_ADDR_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.CLEAR_WAITREQ_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.CTRL_RD_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.CTRL_WR_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.ERR_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.IDLE_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.MDIO_CLR_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.MDIO_FRAME_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.MDIO_PRE_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.MDIO_START_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|mdio_cycle.MDIO_ADDR" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|mdio_cycle.MDIO_END" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|mdio_cycle.MDIO_READ" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|mdio_cycle.MDIO_WRITE" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "altera_pcie:pcie|altpcie_rs_serdes:rs_serdes|serdes_rst_state.IDLE_ST_CNT" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "altera_pcie:pcie|altpcie_rs_serdes:rs_serdes|serdes_rst_state.STABLE_TX_PLL_ST_CNT" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "altera_pcie:pcie|altpcie_rs_serdes:rs_serdes|serdes_rst_state.STROBE_TXPLL_LOCKED_SD_CNT" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "altera_pcie:pcie|altpcie_rs_serdes:rs_serdes|serdes_rst_state.WAIT_STATE_ST_CNT" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "altera_pcie:pcie|dlup_exit" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "altera_pcie:pcie|hotrst_exit" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "altera_pcie:pcie|l2_exit" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "altera_pcie:pcie|rx_fifo_empty0" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "altera_pcie:pcie|rx_fifo_full0" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "altera_pcie:pcie|rx_st_bardec0[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "altera_pcie:pcie|rx_st_bardec0[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "altera_pcie:pcie|rx_st_bardec0[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "altera_pcie:pcie|rx_st_bardec0[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "altera_pcie:pcie|rx_st_bardec0[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "altera_pcie:pcie|rx_st_bardec0[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "altera_pcie:pcie|rx_st_bardec0[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "altera_pcie:pcie|rx_st_bardec0[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "altera_pcie:pcie|rx_st_data0[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "altera_pcie:pcie|rx_st_data0[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "altera_pcie:pcie|rx_st_data0[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "altera_pcie:pcie|rx_st_data0[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "altera_pcie:pcie|rx_st_data0[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "altera_pcie:pcie|rx_st_data0[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "altera_pcie:pcie|rx_st_data0[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "altera_pcie:pcie|rx_st_data0[16]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "altera_pcie:pcie|rx_st_data0[17]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "altera_pcie:pcie|rx_st_data0[18]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "altera_pcie:pcie|rx_st_data0[19]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "altera_pcie:pcie|rx_st_data0[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "altera_pcie:pcie|rx_st_data0[20]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "altera_pcie:pcie|rx_st_data0[21]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "altera_pcie:pcie|rx_st_data0[22]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "altera_pcie:pcie|rx_st_data0[23]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "altera_pcie:pcie|rx_st_data0[24]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "altera_pcie:pcie|rx_st_data0[25]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "altera_pcie:pcie|rx_st_data0[26]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "altera_pcie:pcie|rx_st_data0[27]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "altera_pcie:pcie|rx_st_data0[28]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "altera_pcie:pcie|rx_st_data0[29]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "altera_pcie:pcie|rx_st_data0[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "altera_pcie:pcie|rx_st_data0[30]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "altera_pcie:pcie|rx_st_data0[31]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "altera_pcie:pcie|rx_st_data0[32]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "altera_pcie:pcie|rx_st_data0[33]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "altera_pcie:pcie|rx_st_data0[34]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "altera_pcie:pcie|rx_st_data0[35]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "altera_pcie:pcie|rx_st_data0[36]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "altera_pcie:pcie|rx_st_data0[37]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "altera_pcie:pcie|rx_st_data0[38]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "altera_pcie:pcie|rx_st_data0[39]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "altera_pcie:pcie|rx_st_data0[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "altera_pcie:pcie|rx_st_data0[40]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "altera_pcie:pcie|rx_st_data0[41]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "altera_pcie:pcie|rx_st_data0[42]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "altera_pcie:pcie|rx_st_data0[43]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "altera_pcie:pcie|rx_st_data0[44]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "altera_pcie:pcie|rx_st_data0[45]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "altera_pcie:pcie|rx_st_data0[46]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "altera_pcie:pcie|rx_st_data0[47]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "altera_pcie:pcie|rx_st_data0[48]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "altera_pcie:pcie|rx_st_data0[49]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "altera_pcie:pcie|rx_st_data0[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "altera_pcie:pcie|rx_st_data0[50]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "altera_pcie:pcie|rx_st_data0[51]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "altera_pcie:pcie|rx_st_data0[52]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "altera_pcie:pcie|rx_st_data0[53]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "altera_pcie:pcie|rx_st_data0[54]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "altera_pcie:pcie|rx_st_data0[55]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "altera_pcie:pcie|rx_st_data0[56]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "altera_pcie:pcie|rx_st_data0[57]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "altera_pcie:pcie|rx_st_data0[58]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "altera_pcie:pcie|rx_st_data0[59]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "altera_pcie:pcie|rx_st_data0[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "altera_pcie:pcie|rx_st_data0[60]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "altera_pcie:pcie|rx_st_data0[61]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "altera_pcie:pcie|rx_st_data0[62]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "altera_pcie:pcie|rx_st_data0[63]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "altera_pcie:pcie|rx_st_data0[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "altera_pcie:pcie|rx_st_data0[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "altera_pcie:pcie|rx_st_data0[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "altera_pcie:pcie|rx_st_data0[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "altera_pcie:pcie|rx_st_eop0" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "altera_pcie:pcie|rx_st_err0" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "altera_pcie:pcie|rx_st_ready0" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "altera_pcie:pcie|rx_st_sop0" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "altera_pcie:pcie|rx_st_valid0" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to crst -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to npor -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to pcie_rstn_i -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to pme_shift[0] -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to pme_shift[1] -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to pme_shift[2] -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to pme_shift[3] -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to pme_shift[4] -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to rst_reg -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to srst -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.CHECK_ADDR_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.CLEAR_WAITREQ_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.CTRL_RD_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.CTRL_WR_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.ERR_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.IDLE_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.MDIO_CLR_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.MDIO_FRAME_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.MDIO_PRE_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|cstate.MDIO_START_ST" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|mdio_cycle.MDIO_ADDR" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|mdio_cycle.MDIO_END" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|mdio_cycle.MDIO_READ" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "altera_pcie:pcie|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|altpcie_pcie_reconfig_bridge:altpcie_pcie_reconfig_bridge0|mdio_cycle.MDIO_WRITE" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "altera_pcie:pcie|altpcie_rs_serdes:rs_serdes|serdes_rst_state.IDLE_ST_CNT" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "altera_pcie:pcie|altpcie_rs_serdes:rs_serdes|serdes_rst_state.STABLE_TX_PLL_ST_CNT" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "altera_pcie:pcie|altpcie_rs_serdes:rs_serdes|serdes_rst_state.STROBE_TXPLL_LOCKED_SD_CNT" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "altera_pcie:pcie|altpcie_rs_serdes:rs_serdes|serdes_rst_state.WAIT_STATE_ST_CNT" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "altera_pcie:pcie|dlup_exit" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "altera_pcie:pcie|hotrst_exit" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "altera_pcie:pcie|l2_exit" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "altera_pcie:pcie|rx_fifo_empty0" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "altera_pcie:pcie|rx_fifo_full0" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "altera_pcie:pcie|rx_st_bardec0[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "altera_pcie:pcie|rx_st_bardec0[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "altera_pcie:pcie|rx_st_bardec0[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "altera_pcie:pcie|rx_st_bardec0[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "altera_pcie:pcie|rx_st_bardec0[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "altera_pcie:pcie|rx_st_bardec0[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "altera_pcie:pcie|rx_st_bardec0[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "altera_pcie:pcie|rx_st_bardec0[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "altera_pcie:pcie|rx_st_data0[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "altera_pcie:pcie|rx_st_data0[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "altera_pcie:pcie|rx_st_data0[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "altera_pcie:pcie|rx_st_data0[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "altera_pcie:pcie|rx_st_data0[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "altera_pcie:pcie|rx_st_data0[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "altera_pcie:pcie|rx_st_data0[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "altera_pcie:pcie|rx_st_data0[16]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "altera_pcie:pcie|rx_st_data0[17]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "altera_pcie:pcie|rx_st_data0[18]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "altera_pcie:pcie|rx_st_data0[19]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "altera_pcie:pcie|rx_st_data0[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "altera_pcie:pcie|rx_st_data0[20]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "altera_pcie:pcie|rx_st_data0[21]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "altera_pcie:pcie|rx_st_data0[22]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "altera_pcie:pcie|rx_st_data0[23]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "altera_pcie:pcie|rx_st_data0[24]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "altera_pcie:pcie|rx_st_data0[25]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "altera_pcie:pcie|rx_st_data0[26]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "altera_pcie:pcie|rx_st_data0[27]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "altera_pcie:pcie|rx_st_data0[28]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "altera_pcie:pcie|rx_st_data0[29]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "altera_pcie:pcie|rx_st_data0[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "altera_pcie:pcie|rx_st_data0[30]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "altera_pcie:pcie|rx_st_data0[31]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "altera_pcie:pcie|rx_st_data0[32]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "altera_pcie:pcie|rx_st_data0[33]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "altera_pcie:pcie|rx_st_data0[34]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "altera_pcie:pcie|rx_st_data0[35]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "altera_pcie:pcie|rx_st_data0[36]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "altera_pcie:pcie|rx_st_data0[37]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "altera_pcie:pcie|rx_st_data0[38]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "altera_pcie:pcie|rx_st_data0[39]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "altera_pcie:pcie|rx_st_data0[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "altera_pcie:pcie|rx_st_data0[40]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "altera_pcie:pcie|rx_st_data0[41]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "altera_pcie:pcie|rx_st_data0[42]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "altera_pcie:pcie|rx_st_data0[43]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "altera_pcie:pcie|rx_st_data0[44]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "altera_pcie:pcie|rx_st_data0[45]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "altera_pcie:pcie|rx_st_data0[46]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "altera_pcie:pcie|rx_st_data0[47]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "altera_pcie:pcie|rx_st_data0[48]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "altera_pcie:pcie|rx_st_data0[49]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "altera_pcie:pcie|rx_st_data0[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "altera_pcie:pcie|rx_st_data0[50]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "altera_pcie:pcie|rx_st_data0[51]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "altera_pcie:pcie|rx_st_data0[52]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "altera_pcie:pcie|rx_st_data0[53]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "altera_pcie:pcie|rx_st_data0[54]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "altera_pcie:pcie|rx_st_data0[55]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "altera_pcie:pcie|rx_st_data0[56]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "altera_pcie:pcie|rx_st_data0[57]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "altera_pcie:pcie|rx_st_data0[58]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "altera_pcie:pcie|rx_st_data0[59]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "altera_pcie:pcie|rx_st_data0[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "altera_pcie:pcie|rx_st_data0[60]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "altera_pcie:pcie|rx_st_data0[61]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "altera_pcie:pcie|rx_st_data0[62]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "altera_pcie:pcie|rx_st_data0[63]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "altera_pcie:pcie|rx_st_data0[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "altera_pcie:pcie|rx_st_data0[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "altera_pcie:pcie|rx_st_data0[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "altera_pcie:pcie|rx_st_data0[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "altera_pcie:pcie|rx_st_eop0" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "altera_pcie:pcie|rx_st_err0" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "altera_pcie:pcie|rx_st_ready0" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "altera_pcie:pcie|rx_st_sop0" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "altera_pcie:pcie|rx_st_valid0" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to crst -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to npor -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to pcie_rstn_i -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to pme_shift[0] -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to pme_shift[1] -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to pme_shift[2] -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to pme_shift[3] -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to pme_shift[4] -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to rst_reg -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to srst -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=110" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=110" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=353" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=5814" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=2632" -section_id auto_signaltap_0
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
-- 
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