diff --git a/modules/wishbone/wb_uart/wb_simple_uart.vhd b/modules/wishbone/wb_uart/wb_simple_uart.vhd
index 59f8308f6dea2fa64a73ae034118b35b2c665244..34c0556b553332512bda3b3ced000ffac19deef2 100644
--- a/modules/wishbone/wb_uart/wb_simple_uart.vhd
+++ b/modules/wishbone/wb_uart/wb_simple_uart.vhd
@@ -36,7 +36,8 @@ entity wb_simple_uart is
     g_with_virtual_uart   : boolean;
     g_with_physical_uart  : boolean;
     g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
-    g_address_granularity : t_wishbone_address_granularity := WORD
+    g_address_granularity : t_wishbone_address_granularity := WORD;
+    g_vuart_fifo_size     : integer := 1024
     );
   port (
 
@@ -61,7 +62,6 @@ end wb_simple_uart;
 architecture syn of wb_simple_uart is
 
   constant c_baud_acc_width  : integer := 16;
-  constant c_vuart_fifo_size : integer := 1024;
 
   component uart_baud_gen
     generic (
@@ -135,7 +135,7 @@ architecture syn of wb_simple_uart is
   signal regs_out : t_UART_out_registers;
 
   signal fifo_empty, fifo_full, fifo_rd, fifo_wr : std_logic;
-  signal fifo_count                              : std_logic_vector(f_log2_size(c_vuart_fifo_size)-1 downto 0);
+  signal fifo_count                              : std_logic_vector(f_log2_size(g_vuart_fifo_size)-1 downto 0);
 
   signal phys_rx_ready, phys_tx_busy : std_logic;
   
@@ -246,7 +246,7 @@ begin  -- syn
     U_VUART_FIFO : generic_sync_fifo
       generic map (
         g_data_width => 8,
-        g_size       => c_vuart_fifo_size,
+        g_size       => g_vuart_fifo_size,
         g_with_count => true)
       port map (
         rst_n_i => rst_n_i,
diff --git a/modules/wishbone/wb_uart/xwb_simple_uart.vhd b/modules/wishbone/wb_uart/xwb_simple_uart.vhd
index c66701fdbfd565ec2595e2ed089c8c6b1b7b518e..a175a7665bf08d98d4dd749cc91153380660fd15 100644
--- a/modules/wishbone/wb_uart/xwb_simple_uart.vhd
+++ b/modules/wishbone/wb_uart/xwb_simple_uart.vhd
@@ -35,7 +35,8 @@ entity xwb_simple_uart is
     g_with_virtual_uart   : boolean := true;
     g_with_physical_uart  : boolean := true;
     g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
-    g_address_granularity : t_wishbone_address_granularity := WORD
+    g_address_granularity : t_wishbone_address_granularity := WORD;
+    g_vuart_fifo_size     : integer := 1024
     );
 
   port(
@@ -61,7 +62,8 @@ architecture rtl of xwb_simple_uart is
       g_with_virtual_uart   : boolean;
       g_with_physical_uart  : boolean;
       g_interface_mode      : t_wishbone_interface_mode;
-      g_address_granularity : t_wishbone_address_granularity);
+      g_address_granularity : t_wishbone_address_granularity;
+      g_vuart_fifo_size     : integer);
     port (
       clk_sys_i  : in  std_logic;
       rst_n_i    : in  std_logic;
@@ -85,7 +87,8 @@ begin  -- rtl
       g_with_virtual_uart   => g_with_virtual_uart,
       g_with_physical_uart  => g_with_physical_uart,
       g_interface_mode      => g_interface_mode,
-      g_address_granularity => g_address_granularity)
+      g_address_granularity => g_address_granularity,
+      g_vuart_fifo_size     => g_vuart_fifo_size)
     port map (
       clk_sys_i  => clk_sys_i,
       rst_n_i    => rst_n_i,
diff --git a/modules/wishbone/wishbone_pkg.vhd b/modules/wishbone/wishbone_pkg.vhd
index 95fffda1d4ef47493c5f57e805fabc06c45c4488..1e6d09164ca7deb157b49e48c63510accb1ced6b 100644
--- a/modules/wishbone/wishbone_pkg.vhd
+++ b/modules/wishbone/wishbone_pkg.vhd
@@ -692,7 +692,8 @@ package wishbone_pkg is
       g_with_virtual_uart   : boolean                        := false;
       g_with_physical_uart  : boolean                        := true;
       g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
-      g_address_granularity : t_wishbone_address_granularity := WORD);
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_vuart_fifo_size     : integer := 1024);
     port (
       clk_sys_i  : in  std_logic;
       rst_n_i    : in  std_logic;
@@ -714,7 +715,8 @@ package wishbone_pkg is
       g_with_virtual_uart   : boolean                        := false;
       g_with_physical_uart  : boolean                        := true;
       g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
-      g_address_granularity : t_wishbone_address_granularity := WORD);
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_vuart_fifo_size     : integer := 1024);
     port (
       clk_sys_i  : in  std_logic;
       rst_n_i    : in  std_logic;