diff --git a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
index 0a5bf91cd4b369ba71b03c2f0b6fe8501f9e666c..97d31001df6526004e36fa24eef49d9f15d76cfc 100644
--- a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
+++ b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
@@ -5,7 +5,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-Co-HT
 -- Created    : 2010-05-18
--- Last update: 2011-04-06
+-- Last update: 2011-06-07
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'87
 -------------------------------------------------------------------------------
@@ -29,28 +29,31 @@ use work.wishbone_pkg.all;
 use work.gencores_pkg.all;
 
 entity wb_gpio_port is
-  generic(g_num_pins : natural := 8     -- number of GPIO pins
-          );
+  generic(
+    g_num_pins               : natural := 8;
+    g_with_builtin_tristates : boolean := false
+    );
   port(
 -- System reset, active low
-    sys_rst_n_i : in std_logic;
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    wb_sel_i : in  std_logic;
+    wb_cyc_i : in  std_logic;
+    wb_stb_i : in  std_logic;
+    wb_we_i  : in  std_logic;
+    wb_adr_i : in  std_logic_vector(2 downto 0);
+    wb_dat_i : in  std_logic_vector(31 downto 0);
+    wb_dat_o : out std_logic_vector(31 downto 0);
+    wb_ack_o : out std_logic;
+
+    gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
+
+    gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
+    gpio_in_i  : in  std_logic_vector(g_num_pins-1 downto 0);
+    gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0)
 
--------------------------------------------------------------------------------
--- Wishbone bus
--------------------------------------------------------------------------------
 
-    wb_clk_i  : in  std_logic;
-    wb_sel_i  : in  std_logic;
-    wb_cyc_i  : in  std_logic;
-    wb_stb_i  : in  std_logic;
-    wb_we_i   : in  std_logic;
-    wb_addr_i : in  std_logic_vector(2 downto 0);
-    wb_data_i : in  std_logic_vector(31 downto 0);
-    wb_data_o : out std_logic_vector(31 downto 0);
-    wb_ack_o  : out std_logic;
-
--- GPIO pin vector
-    gpio_b : inout std_logic_vector(g_num_pins-1 downto 0)
     );
 end wb_gpio_port;
 
@@ -64,6 +67,7 @@ architecture behavioral of wb_gpio_port is
 
 
   signal out_reg, in_reg, dir_reg : std_logic_vector(g_num_pins-1 downto 0);
+  signal gpio_in                  : std_logic_vector(g_num_pins-1 downto 0);
   signal gpio_in_synced           : std_logic_vector(g_num_pins-1 downto 0);
   signal ack_int                  : std_logic;
 
@@ -75,9 +79,9 @@ begin
       generic map (
         g_sync_edge => "positive")
       port map (
-        rst_n_i  => sys_rst_n_i,
-        clk_i    => wb_clk_i,
-        data_i   => gpio_b(i),
+        rst_n_i  => rst_n_i,
+        clk_i    => clk_sys_i,
+        data_i   => gpio_in(i),
         synced_o => gpio_in_synced(i),
         npulse_o => open
         );
@@ -91,33 +95,33 @@ begin
       dir_reg                          <= (others => '0');
       out_reg                          <= (others => '0');
       ack_int                          <= '0';
-      wb_data_o(g_num_pins-1 downto 0) <= (others => '0');
+      wb_dat_o(g_num_pins-1 downto 0) <= (others => '0');
     elsif rising_edge(wb_clk_i) then
       if(ack_int = '1') then
         ack_int <= '0';
       elsif(wb_cyc_i = '1') and (wb_sel_i = '1') and (wb_stb_i = '1') then
         if(wb_we_i = '1') then
-          case wb_addr_i(2 downto 0) is
+          case wb_adr_i(2 downto 0) is
             when c_GPIO_REG_SODR =>
-              out_reg <= out_reg or wb_data_i(g_num_pins-1 downto 0);
+              out_reg <= out_reg or wb_dat_i(g_num_pins-1 downto 0);
               ack_int <= '1';
             when c_GPIO_REG_CODR =>
-              out_reg <= out_reg and (not wb_data_i(g_num_pins-1 downto 0));
+              out_reg <= out_reg and (not wb_dat_i(g_num_pins-1 downto 0));
               ack_int <= '1';
             when c_GPIO_REG_DDR =>
-              dir_reg <= wb_data_i(g_num_pins-1 downto 0);
+              dir_reg <= wb_dat_i(g_num_pins-1 downto 0);
               ack_int <= '1';
             when others =>
               ack_int <= '1';
           end case;
         else
-          case wb_addr_i(2 downto 0) is
+          case wb_adr_i(2 downto 0) is
             when c_GPIO_REG_DDR =>
-              wb_data_o(g_num_pins-1 downto 0) <= dir_reg;
+              wb_dat_o(g_num_pins-1 downto 0) <= dir_reg;
               ack_int                          <= '1';
               
             when c_GPIO_REG_PSR =>
-              wb_data_o(g_num_pins-1 downto 0) <= gpio_in_synced;
+              wb_dat_o(g_num_pins-1 downto 0) <= gpio_in_synced;
               ack_int                          <= '1';
             when others =>
               ack_int <= '1';
@@ -129,17 +133,30 @@ begin
     end if;
   end process;
 
-  gpio_out_tristate : process (out_reg, dir_reg)
-  begin
-    for i in 0 to g_num_pins-1 loop
-      if(dir_reg(i) = '1') then
-        gpio_b(i) <= out_reg(i);
-      else
-        gpio_b(i) <= 'Z';
-      end if;
-      
-    end loop;
-  end process gpio_out_tristate;
+
+  gen_with_tristates : if(g_with_builtin_tristates) generate
+    
+    gpio_out_tristate : process (out_reg, dir_reg)
+    begin
+      for i in 0 to g_num_pins-1 loop
+        if(dir_reg(i) = '1') then
+          gpio_b(i) <= out_reg(i);
+        else
+          gpio_b(i) <= 'Z';
+        end if;
+        
+      end loop;
+    end process gpio_out_tristate;
+
+    gpio_in <= gpio_b;
+    
+  end generate gen_with_tristates;
+
+  gen_without_tristates : if (not g_with_builtin_tristates) generate
+    gpio_out_o <= out_reg;
+    gpio_in    <= gpio_i;
+    gpio_oen_o <= dir_reg;
+  end generate gen_without_tristates;
 
   wb_ack_o <= ack_int;
 end behavioral;