From 73afb30ed88f89de3138028e406c23771f0793bb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tomasz=20W=C5=82ostowski?= <tomasz.wlostowski@cern.ch>
Date: Thu, 19 Jul 2012 16:47:31 +0200
Subject: [PATCH] wishbone/wb_xilinx_fpga_loader: testbench fixes
---
testbench/wishbone/wb_xilinx_fpga_loader/Manifest.py | 2 +-
testbench/wishbone/wb_xilinx_fpga_loader/main.sv | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/testbench/wishbone/wb_xilinx_fpga_loader/Manifest.py b/testbench/wishbone/wb_xilinx_fpga_loader/Manifest.py
index 9e504770..d2ded3e3 100644
--- a/testbench/wishbone/wb_xilinx_fpga_loader/Manifest.py
+++ b/testbench/wishbone/wb_xilinx_fpga_loader/Manifest.py
@@ -1,5 +1,5 @@
action = "simulation"
-
+target = "xilinx"
fetchto="../../../ip_cores"
modules = { "local" : "../../../" };
diff --git a/testbench/wishbone/wb_xilinx_fpga_loader/main.sv b/testbench/wishbone/wb_xilinx_fpga_loader/main.sv
index 38ecc26e..f7c6134e 100644
--- a/testbench/wishbone/wb_xilinx_fpga_loader/main.sv
+++ b/testbench/wishbone/wb_xilinx_fpga_loader/main.sv
@@ -33,6 +33,8 @@ module main;
.clk_sys_i (clk_sys),
.rst_n_i (rst_n),
+ .boot_en_i(1'b1),
+
.wb_adr_i (U_WB.master.adr),
.wb_dat_i (U_WB.master.dat_o),
.wb_dat_o (U_WB.master.dat_i),
--
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