diff --git a/hdl/altera_pcie.qip b/hdl/altera_pcie.qip
index fc19ec9ebb874f9ecf88860fbceddde3d006ddbd..99064b352fc63e25d2bb3bee41e6cad1fa821c84 100644
--- a/hdl/altera_pcie.qip
+++ b/hdl/altera_pcie.qip
@@ -4,62 +4,62 @@ set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altera_pc
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altera_pcie_core.vhd"]
set_global_assignment -name SEARCH_PATH [file join $::quartus(qip_path) "." ]
set_global_assignment -name SEARCH_PATH [file join $::quartus(qip_path) ip_compiler_for_pci_express-library ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcierd_reconfig_clk_pll.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_dlink.ocp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen2_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_hip_256_pipen1b.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pclk_align.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy1_62p5.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_reconfig_4sgx.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_rs_serdes.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_16p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_16p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x4d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x8d_10000.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_dlink.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_100_250.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_15625.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_250_100.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy5_62p5.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_16p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp_dcram.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy0.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pclk_pll.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen2_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_16p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x8d_10000.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_dlink.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_100_125.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_15625.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_hip_256_pipen1b.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen2_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x4d_10000.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_250_100.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy3_62p5.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_125_250.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen2_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_16p.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_16p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy0.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy2.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_16p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_15625_125.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcierd_reconfig_clk_pll.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_rs_serdes.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_trans.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x2d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_16p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen2_08p.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pclk_pll.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp_dcram.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy1_62p5.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x4d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_reconfig_4sgx.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x1d_10000.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_16p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_15625.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_125_250.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy2.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x8d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x2d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_16p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_phasefifo.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_dlink.ocp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_100_250.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_08p.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_15625.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy3_62p5.v ]
+set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pclk_align.v ]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x8d_gen1_08p.v ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.vhd ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_core.cmp ]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_core.vhd ]
diff --git a/hdl/altera_pcie.vhd b/hdl/altera_pcie.vhd
index 917019a3a63563c7564ac3ecfdc8ed46ce1eb7ee..17a141bb68792c1bf7959a4054a34f218487bd6f 100644
--- a/hdl/altera_pcie.vhd
+++ b/hdl/altera_pcie.vhd
@@ -1131,7 +1131,7 @@ end europa;
-- Warning: If you modify this section, IP Compiler for PCI Express Wizard may not be able to reproduce your chosen configuration.
--
-- Retrieval info: <?xml version="1.0"?>
--- Retrieval info: <MEGACORE title="IP Compiler for PCI Express" version="11.1" build="173" iptb_version="1.3.0 Build 173" format_version="120" >
+-- Retrieval info: <MEGACORE title="IP Compiler for PCI Express" version="11.1" build="216" iptb_version="1.3.0 Build 216" format_version="120" >
-- Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.MVCModel" active_core="altpcie_hip_pipen1b" >
-- Retrieval info: <STATIC_SECTION>
-- Retrieval info: <PRIVATES>
@@ -1226,19 +1226,19 @@ end europa;
-- Retrieval info: <PRIVATE name = "p_pci_bar_0_avalon_address" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_0_hardwired" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_0_pci_address" value="0" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pci_bar_0_prefetchable" value="true" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pci_bar_0_prefetchable" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_1_auto_avalon_address" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_1_auto_sized" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_1_avalon_address" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_1_hardwired" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_1_pci_address" value="0" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pci_bar_1_prefetchable" value="true" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pci_bar_1_prefetchable" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_2_auto_avalon_address" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_2_auto_sized" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_2_avalon_address" value="0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_2_hardwired" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_2_pci_address" value="0" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pci_bar_2_prefetchable" value="true" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pci_bar_2_prefetchable" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_3_auto_avalon_address" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_3_auto_sized" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_bar_3_avalon_address" value="0" type="STRING" enable="1" />
@@ -1283,21 +1283,21 @@ end europa;
-- Retrieval info: <PRIVATE name = "p_pcie_altgx_keyParameters_used" value="{p_pcie_enable_hip=1, p_pcie_number_of_lanes=x4, p_pcie_phy=Arria II GX, p_pcie_rate=Gen1 (2.5 Gbps), p_pcie_txrx_clock=100 MHz}" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_app_signal_interface" value="AvalonST" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_avalon_mm_lite" value="0" type="INTEGER" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_0" value="4 GBytes - 32 bits" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_1" value="N/A" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_2" value="N/A" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_0" value="256 Bytes - 8 bits" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_1" value="64 MBytes - 26 bits" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_2" value="64 MBytes - 26 bits" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_3" value="N/A" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_4" value="N/A" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_5" value="N/A" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_0" value="64-bit Prefetchable Memory" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_1" value="N/A" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_2" value="Disable this and all higher BARs" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_0" value="32-bit Non-Prefetchable Memory" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_1" value="32-bit Non-Prefetchable Memory" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_2" value="32-bit Non-Prefetchable Memory" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_3" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_4" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_5" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_0" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_1" value="1" type="BOOLEAN" enable="1" />
--- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_2" value="0" type="BOOLEAN" enable="1" />
+-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_2" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_3" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_4" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_5" value="0" type="BOOLEAN" enable="1" />
@@ -1462,11 +1462,11 @@ end europa;
-- Retrieval info: <PRIVATE name = "uiAvalonHWPCIAddress9" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiAvalonTranslationTable" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar0PCIAddress" value="0x00000000" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "uiBar0Prefetchable" value="true" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "uiBar0Prefetchable" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar1PCIAddress" value="0x00000000" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "uiBar1Prefetchable" value="true" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "uiBar1Prefetchable" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar2PCIAddress" value="0x00000000" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "uiBar2Prefetchable" value="true" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "uiBar2Prefetchable" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar3PCIAddress" value="0x00000000" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar3Prefetchable" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiBar4PCIAddress" value="0x00000000" type="STRING" enable="1" />
@@ -1476,9 +1476,9 @@ end europa;
-- Retrieval info: <PRIVATE name = "uiCRAInfoPanel" value="other" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiExpROMType" value="Select to Enable" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiFixedTable" value="true" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "uiPCIBar0Type" value="64-bit Prefetchable Memory" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "uiPCIBar1Type" value="N/A" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "uiPCIBar2Type" value="Disable this and all higher BARs" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "uiPCIBar0Type" value="32-bit Non-Prefetchable Memory" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "uiPCIBar1Type" value="32-bit Non-Prefetchable Memory" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "uiPCIBar2Type" value="32-bit Non-Prefetchable Memory" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBar3Type" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBar4Type" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBar5Type" value="Disable this and all higher BARs" type="STRING" enable="1" />
@@ -1489,8 +1489,8 @@ end europa;
-- Retrieval info: <PRIVATE name = "uiPCITargetPerformance" value="burstSinglePending" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPaneCount" value="1" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPaneSize" value="20" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "ui_pcie_msix_pba_bir" value="1:0" type="STRING" enable="1" />
--- Retrieval info: <PRIVATE name = "ui_pcie_msix_table_bir" value="1:0" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "ui_pcie_msix_pba_bir" value="0" type="STRING" enable="1" />
+-- Retrieval info: <PRIVATE name = "ui_pcie_msix_table_bir" value="0" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen_enable">
-- Retrieval info: <PRIVATE name = "language" value="VHDL" type="STRING" enable="1" />
diff --git a/hdl/altera_pcie_core.vhd b/hdl/altera_pcie_core.vhd
index 71f5c24c3447421454b637fcef2bd9f98ca49513..e621f4f2743c1046f73f93eba2fd48f82bee96d8 100644
--- a/hdl/altera_pcie_core.vhd
+++ b/hdl/altera_pcie_core.vhd
@@ -1,4 +1,4 @@
--- Generated by IP Compiler for PCI Express 11.1 [Altera, IP Toolbench 1.3.0 Build 173]
+-- Generated by IP Compiler for PCI Express 11.1 [Altera, IP Toolbench 1.3.0 Build 216]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
@@ -301,6 +301,10 @@ ARCHITECTURE SYN OF altera_pcie_core IS
bar1_64bit_mem_space : STRING;
bar1_prefetchable : STRING;
bar1_size_mask : NATURAL;
+ bar2_io_space : STRING;
+ bar2_64bit_mem_space : STRING;
+ bar2_prefetchable : STRING;
+ bar2_size_mask : NATURAL;
enable_ecrc_check : STRING;
enable_ecrc_gen : STRING;
enable_l1_aspm : STRING;
@@ -760,13 +764,17 @@ BEGIN
retry_buffer_last_active_address => "255",
advanced_errors => "false",
bar0_io_space => "false",
- bar0_64bit_mem_space => "true",
- bar0_prefetchable => "true",
- bar0_size_mask => 32,
+ bar0_64bit_mem_space => "false",
+ bar0_prefetchable => "false",
+ bar0_size_mask => 8,
bar1_io_space => "false",
- bar1_64bit_mem_space => "true",
+ bar1_64bit_mem_space => "false",
bar1_prefetchable => "false",
- bar1_size_mask => 0,
+ bar1_size_mask => 26,
+ bar2_io_space => "false",
+ bar2_64bit_mem_space => "false",
+ bar2_prefetchable => "false",
+ bar2_size_mask => 26,
enable_ecrc_check => "false",
enable_ecrc_gen => "false",
enable_l1_aspm => "false",
diff --git a/hdl/altera_pcie_pll.vhd b/hdl/altera_pcie_pll.vhd
index ef9759ef838550d65f63021e9d2a6b820fd11cce..10f73786290f17f21ec51e1a98c272b806538a9a 100644
--- a/hdl/altera_pcie_pll.vhd
+++ b/hdl/altera_pcie_pll.vhd
@@ -14,7 +14,7 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
--- 11.1 Build 173 11/01/2011 SJ Full Version
+-- 11.1 Build 216 11/23/2011 SP 1 SJ Full Version
-- ************************************************************
@@ -45,7 +45,6 @@ ENTITY altera_pcie_pll IS
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
- c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END altera_pcie_pll;
@@ -53,14 +52,13 @@ END altera_pcie_pll;
ARCHITECTURE SYN OF altera_pcie_pll IS
- SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0);
- SIGNAL sub_wire1 : STD_LOGIC ;
+ SIGNAL sub_wire0 : STD_LOGIC ;
+ SIGNAL sub_wire1 : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
- SIGNAL sub_wire4 : STD_LOGIC ;
- SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
- SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
- SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
+ SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
+ SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -71,10 +69,6 @@ ARCHITECTURE SYN OF altera_pcie_pll IS
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
- clk1_divide_by : NATURAL;
- clk1_duty_cycle : NATURAL;
- clk1_multiply_by : NATURAL;
- clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
@@ -137,27 +131,21 @@ ARCHITECTURE SYN OF altera_pcie_pll IS
END COMPONENT;
BEGIN
- sub_wire6_bv(0 DOWNTO 0) <= "0";
- sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
- sub_wire3 <= sub_wire0(0);
- sub_wire1 <= sub_wire0(1);
- c1 <= sub_wire1;
- locked <= sub_wire2;
- c0 <= sub_wire3;
- sub_wire4 <= inclk0;
- sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
+ sub_wire5_bv(0 DOWNTO 0) <= "0";
+ sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
+ locked <= sub_wire0;
+ sub_wire2 <= sub_wire1(0);
+ c0 <= sub_wire2;
+ sub_wire3 <= inclk0;
+ sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
- clk0_divide_by => 25,
+ clk0_divide_by => 5,
clk0_duty_cycle => 50,
- clk0_multiply_by => 8,
+ clk0_multiply_by => 2,
clk0_phase_shift => "0",
- clk1_divide_by => 5,
- clk1_duty_cycle => 50,
- clk1_multiply_by => 2,
- clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 8000,
intended_device_family => "Arria II GX",
@@ -192,7 +180,7 @@ BEGIN
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
- port_clk1 => "PORT_USED",
+ port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
@@ -213,9 +201,9 @@ BEGIN
)
PORT MAP (
areset => areset,
- inclk => sub_wire5,
- clk => sub_wire0,
- locked => sub_wire2
+ inclk => sub_wire4,
+ locked => sub_wire0,
+ clk => sub_wire1
);
@@ -242,11 +230,8 @@ END SYN;
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "5"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "5"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -267,24 +252,17 @@ END SYN;
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -307,24 +285,18 @@ END SYN;
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
@@ -358,7 +330,7 @@ END SYN;
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -380,14 +352,12 @@ END SYN;
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_pcie_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_pcie_pll.ppf TRUE
diff --git a/hdl/altera_pcie_serdes.vhd b/hdl/altera_pcie_serdes.vhd
index 5bb5d381a6534751b70e50c291bbf51960a4e2fc..37de03763eb7986000d650fa85fb93829890887f 100644
--- a/hdl/altera_pcie_serdes.vhd
+++ b/hdl/altera_pcie_serdes.vhd
@@ -14,7 +14,7 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
--- 11.1 Build 173 11/01/2011 SJ Full Version
+-- 11.1 Build 216 11/23/2011 SP 1 SJ Full Version
-- ************************************************************
@@ -34,7 +34,7 @@
--alt4gxb CBX_AUTO_BLACKBOX="ALL" coreclkout_control_width=1 device_family="Arria II GX" effective_data_rate="2500 Mbps" elec_idle_infer_enable="false" enable_0ppm="false" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=1 equalizer_dcgain_setting=1 gen_reconfig_pll="false" gx_channel_type="auto" gxb_analog_power="AUTO" gxb_powerdown_width=1 hip_enable="true" input_clock_frequency="100.0 MHz" intended_device_speed_grade="4" intended_device_variant="ANY" loopback_mode="none" number_of_channels=4 number_of_quads=1 operation_mode="duplex" pll_control_width=1 pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="pcie" rateswitch_control_width=1 receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=1 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="x4" rx_channel_width=8 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_inclock0_period=10000 rx_cru_m_divider=0 rx_cru_n_divider=1 rx_cru_vco_post_scale_divider=2 rx_data_rate=2500 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=3 rx_signal_detect_threshold=4 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="auto" tx_channel_bonding="x4" tx_channel_width=8 tx_clkout_width=4 tx_common_mode="0.65v" tx_data_rate=2500 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_inclk0_period=10000 tx_pll_m_divider=0 tx_pll_n_divider=1 tx_pll_type="CMU" tx_pll_vco_post_scale_divider=2 tx_slew_rate="off" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk coreclkout fixedclk gxb_powerdown hip_tx_clkout pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked pll_powerdown powerdn rateswitch rateswitchbaseclock reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_elecidleinfersel rx_freqlocked rx_patterndetect rx_pll_locked rx_signaldetect rx_syncstatus tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle tx_pipedeemph tx_pipemargin
---VERSION_BEGIN 11.1 cbx_alt4gxb 2011:10:31:21:09:45:SJ cbx_mgl 2011:10:31:21:20:20:SJ cbx_tgx 2011:10:31:21:09:45:SJ VERSION_END
+--VERSION_BEGIN 11.1SP1 cbx_alt4gxb 2011:11:23:21:11:17:SJ cbx_mgl 2011:11:23:21:12:03:SJ cbx_tgx 2011:11:23:21:11:17:SJ VERSION_END
LIBRARY arriaii_hssi;
USE arriaii_hssi.all;
diff --git a/hdl/flash_loader.qip b/hdl/flash_loader.qip
deleted file mode 100644
index 503528d081eb37743fbd60f2e3f15f406aa9dfb3..0000000000000000000000000000000000000000
--- a/hdl/flash_loader.qip
+++ /dev/null
@@ -1,4 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "Serial Flash Loader"
-set_global_assignment -name IP_TOOL_VERSION "11.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "flash_loader.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "flash_loader.cmp"]
diff --git a/hdl/flash_loader.vhd b/hdl/flash_loader.vhd
deleted file mode 100644
index c49fa3594c50e81f47ccb05960f7ffe81f8508b4..0000000000000000000000000000000000000000
--- a/hdl/flash_loader.vhd
+++ /dev/null
@@ -1,102 +0,0 @@
--- megafunction wizard: %Serial Flash Loader%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altserial_flash_loader
-
--- ============================================================
--- File Name: flash_loader.vhd
--- Megafunction Name(s):
--- altserial_flash_loader
---
--- Simulation Library Files(s):
--- altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 11.1 Build 173 11/01/2011 SJ Full Version
--- ************************************************************
-
-
---Copyright (C) 1991-2011 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions
---and other software and tools, and its AMPP partner logic
---functions, and any output files from any of the foregoing
---(including device programming or simulation files), and any
---associated documentation or information are expressly subject
---to the terms and conditions of the Altera Program License
---Subscription Agreement, Altera MegaCore Function License
---Agreement, or other applicable license agreement, including,
---without limitation, that your use is for the sole purpose of
---programming logic devices manufactured by Altera and sold by
---Altera or its authorized distributors. Please refer to the
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY flash_loader IS
- PORT
- (
- noe_in : IN STD_LOGIC
- );
-END flash_loader;
-
-
-ARCHITECTURE SYN OF flash_loader IS
-
-
-
-
- COMPONENT altserial_flash_loader
- GENERIC (
- enable_quad_spi_support : NATURAL;
- enable_shared_access : STRING;
- enhanced_mode : NATURAL;
- intended_device_family : STRING;
- lpm_type : STRING
- );
- PORT (
- noe : IN STD_LOGIC
- );
- END COMPONENT;
-
-BEGIN
-
- altserial_flash_loader_component : altserial_flash_loader
- GENERIC MAP (
- enable_quad_spi_support => 0,
- enable_shared_access => "OFF",
- enhanced_mode => 1,
- intended_device_family => "Arria II GX",
- lpm_type => "altserial_flash_loader"
- )
- PORT MAP (
- noe => noe_in
- );
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: ENABLE_QUAD_SPI_SUPPORT NUMERIC "0"
--- Retrieval info: CONSTANT: ENABLE_SHARED_ACCESS STRING "OFF"
--- Retrieval info: CONSTANT: ENHANCED_MODE NUMERIC "1"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
--- Retrieval info: USED_PORT: noe_in 0 0 0 0 INPUT NODEFVAL "noe_in"
--- Retrieval info: CONNECT: @noe 0 0 0 0 noe_in 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL flash_loader_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
diff --git a/hdl/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v b/hdl/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v
index 0a75b83604e9962903d95fc86dfab6b465150169..088541e1707070c56bfdb33a77e948072292fb1d 100644
Binary files a/hdl/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v and b/hdl/ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v differ
diff --git a/hdl/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v b/hdl/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v
index 7fc92fc50aea7adc150aa5910871faffc50101be..cbd2d4aaf538d07bf9429636c6f16bfc35b72024 100644
Binary files a/hdl/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v and b/hdl/ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v differ
diff --git a/hdl/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v b/hdl/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v
index 22ec7fe4d6ba6749f580ef9c3aa3cdcde61100b2..3073473a52d11cb99379cfa8b6a40be0e3837359 100644
Binary files a/hdl/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v and b/hdl/ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v differ
diff --git a/hdl/ip_compiler_for_pci_express-library/pciexp64_dlink.v b/hdl/ip_compiler_for_pci_express-library/pciexp64_dlink.v
index 2cf35064c0bff0943d36ede96ae16a960ea12275..5d1e77af915715f55ea7867861389714564cc17f 100644
Binary files a/hdl/ip_compiler_for_pci_express-library/pciexp64_dlink.v and b/hdl/ip_compiler_for_pci_express-library/pciexp64_dlink.v differ
diff --git a/hdl/ip_compiler_for_pci_express-library/pciexp64_trans.v b/hdl/ip_compiler_for_pci_express-library/pciexp64_trans.v
index 98c5a074ec65dcd6c3ea5e25b4f7a37498534185..c9f3e76da208e882db14c7219a7c87410418aa2d 100644
Binary files a/hdl/ip_compiler_for_pci_express-library/pciexp64_trans.v and b/hdl/ip_compiler_for_pci_express-library/pciexp64_trans.v differ
diff --git a/hdl/ip_compiler_for_pci_express-library/pciexp_dcram.v b/hdl/ip_compiler_for_pci_express-library/pciexp_dcram.v
index 1dd3693552f6239ec60e7417cfc3b12cb1321f8f..def0ff4d5b1ffb2c403c47d76aff988ab422fa10 100644
Binary files a/hdl/ip_compiler_for_pci_express-library/pciexp_dcram.v and b/hdl/ip_compiler_for_pci_express-library/pciexp_dcram.v differ
diff --git a/hdl/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v b/hdl/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v
index c6bef3e50033745a83f07fbbf706a04e46f0649d..8cb8cdd8d6bde6919c634f332f3044afa3f38a3e 100644
Binary files a/hdl/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v and b/hdl/ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v differ
diff --git a/hdl/pcie_altera.vhd b/hdl/pcie_altera.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ff8343d10eef87ea10efc02f59023de89547cd20
--- /dev/null
+++ b/hdl/pcie_altera.vhd
@@ -0,0 +1,492 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pcie_altera is
+ port(
+ clk125_i : in std_logic; -- 125 MHz, free running
+ cal_clk50_i : in std_logic; -- 50 MHz, shared between all PHYs
+ rstn_i : in std_logic; -- Power on reset
+ rstn_o : out std_logic; -- If PCIe resets
+
+ pcie_refclk_i : in std_logic; -- 100 MHz, must not derive clk125_i or cal_clk50_i
+ pcie_rstn_i : in std_logic; -- PCIe reset pin
+ pcie_rx_i : in std_logic_vector(3 downto 0);
+ pcie_tx_o : out std_logic_vector(3 downto 0);
+
+ cfg_busdev : out std_logic_vector(12 downto 0); -- Configured Bus#:Dev#
+
+ -- Simplified wishbone output stream
+ wb_clk_o : out std_logic;
+
+ rx_wb_stb_o : out std_logic;
+ rx_wb_dat_o : out std_logic_vector(31 downto 0);
+ rx_wb_stall_i : in std_logic;
+
+ tx_wb_stb_i : in std_logic;
+ tx_wb_dat_i : in std_logic_vector(31 downto 0);
+ tx_wb_stall_o : out std_logic);
+end pcie_altera;
+
+architecture rtl of pcie_altera is
+ component altera_reconfig is
+ port(
+ reconfig_clk : in std_logic;
+ reconfig_fromgxb : in std_logic_vector(16 downto 0);
+ busy : out std_logic;
+ reconfig_togxb : out std_logic_vector(3 downto 0));
+ end component;
+
+ component altera_pcie is
+ port (
+ signal app_int_sts : in std_logic;
+ signal app_msi_num : in std_logic_vector (4 downto 0);
+ signal app_msi_req : in std_logic;
+ signal app_msi_tc : in std_logic_vector (2 downto 0);
+ signal busy_altgxb_reconfig : in std_logic;
+ signal cal_blk_clk : in std_logic;
+ signal cpl_err : in std_logic_vector (6 downto 0);
+ signal cpl_pending : in std_logic;
+ signal crst : in std_logic;
+ signal fixedclk_serdes : in std_logic;
+ signal gxb_powerdown : in std_logic;
+ signal hpg_ctrler : in std_logic_vector (4 downto 0);
+ signal lmi_addr : in std_logic_vector (11 downto 0);
+ signal lmi_din : in std_logic_vector (31 downto 0);
+ signal lmi_rden : in std_logic;
+ signal lmi_wren : in std_logic;
+ signal npor : in std_logic;
+ signal pclk_in : in std_logic;
+ signal pex_msi_num : in std_logic_vector (4 downto 0);
+ signal phystatus_ext : in std_logic;
+ signal pipe_mode : in std_logic;
+ signal pld_clk : in std_logic;
+ signal pll_powerdown : in std_logic;
+ signal pm_auxpwr : in std_logic;
+ signal pm_data : in std_logic_vector (9 downto 0);
+ signal pm_event : in std_logic;
+ signal pme_to_cr : in std_logic;
+ signal reconfig_clk : in std_logic;
+ signal reconfig_togxb : in std_logic_vector (3 downto 0);
+ signal refclk : in std_logic;
+ signal rx_in0 : in std_logic;
+ signal rx_in1 : in std_logic;
+ signal rx_in2 : in std_logic;
+ signal rx_in3 : in std_logic;
+ signal rx_st_mask0 : in std_logic;
+ signal rx_st_ready0 : in std_logic;
+ signal rxdata0_ext : in std_logic_vector (7 downto 0);
+ signal rxdata1_ext : in std_logic_vector (7 downto 0);
+ signal rxdata2_ext : in std_logic_vector (7 downto 0);
+ signal rxdata3_ext : in std_logic_vector (7 downto 0);
+ signal rxdatak0_ext : in std_logic;
+ signal rxdatak1_ext : in std_logic;
+ signal rxdatak2_ext : in std_logic;
+ signal rxdatak3_ext : in std_logic;
+ signal rxelecidle0_ext : in std_logic;
+ signal rxelecidle1_ext : in std_logic;
+ signal rxelecidle2_ext : in std_logic;
+ signal rxelecidle3_ext : in std_logic;
+ signal rxstatus0_ext : in std_logic_vector (2 downto 0);
+ signal rxstatus1_ext : in std_logic_vector (2 downto 0);
+ signal rxstatus2_ext : in std_logic_vector (2 downto 0);
+ signal rxstatus3_ext : in std_logic_vector (2 downto 0);
+ signal rxvalid0_ext : in std_logic;
+ signal rxvalid1_ext : in std_logic;
+ signal rxvalid2_ext : in std_logic;
+ signal rxvalid3_ext : in std_logic;
+ signal srst : in std_logic;
+ signal test_in : in std_logic_vector (39 downto 0);
+ signal tx_st_data0 : in std_logic_vector (63 downto 0);
+ signal tx_st_eop0 : in std_logic;
+ signal tx_st_err0 : in std_logic;
+ signal tx_st_sop0 : in std_logic;
+ signal tx_st_valid0 : in std_logic;
+ signal app_int_ack : out std_logic;
+ signal app_msi_ack : out std_logic;
+ signal clk250_out : out std_logic;
+ signal clk500_out : out std_logic;
+ signal core_clk_out : out std_logic;
+ signal derr_cor_ext_rcv0 : out std_logic;
+ signal derr_cor_ext_rpl : out std_logic;
+ signal derr_rpl : out std_logic;
+ signal dlup_exit : out std_logic;
+ signal hotrst_exit : out std_logic;
+ signal ko_cpl_spc_vc0 : out std_logic_vector (19 downto 0);
+ signal l2_exit : out std_logic;
+ signal lane_act : out std_logic_vector (3 downto 0);
+ signal lmi_ack : out std_logic;
+ signal lmi_dout : out std_logic_vector (31 downto 0);
+ signal ltssm : out std_logic_vector (4 downto 0);
+ signal npd_alloc_1cred_vc0 : out std_logic;
+ signal npd_cred_vio_vc0 : out std_logic;
+ signal nph_alloc_1cred_vc0 : out std_logic;
+ signal nph_cred_vio_vc0 : out std_logic;
+ signal pme_to_sr : out std_logic;
+ signal powerdown_ext : out std_logic_vector (1 downto 0);
+ signal r2c_err0 : out std_logic;
+ signal rate_ext : out std_logic;
+ signal rc_pll_locked : out std_logic;
+ signal rc_rx_digitalreset : out std_logic;
+ signal reconfig_fromgxb : out std_logic_vector (16 downto 0);
+ signal reset_status : out std_logic;
+ signal rx_fifo_empty0 : out std_logic;
+ signal rx_fifo_full0 : out std_logic;
+ signal rx_st_bardec0 : out std_logic_vector (7 downto 0);
+ signal rx_st_be0 : out std_logic_vector (7 downto 0);
+ signal rx_st_data0 : out std_logic_vector (63 downto 0);
+ signal rx_st_eop0 : out std_logic;
+ signal rx_st_err0 : out std_logic;
+ signal rx_st_sop0 : out std_logic;
+ signal rx_st_valid0 : out std_logic;
+ signal rxpolarity0_ext : out std_logic;
+ signal rxpolarity1_ext : out std_logic;
+ signal rxpolarity2_ext : out std_logic;
+ signal rxpolarity3_ext : out std_logic;
+ signal suc_spd_neg : out std_logic;
+ signal test_out : out std_logic_vector (8 downto 0);
+ signal tl_cfg_add : out std_logic_vector (3 downto 0);
+ signal tl_cfg_ctl : out std_logic_vector (31 downto 0);
+ signal tl_cfg_ctl_wr : out std_logic;
+ signal tl_cfg_sts : out std_logic_vector (52 downto 0);
+ signal tl_cfg_sts_wr : out std_logic;
+ signal tx_cred0 : out std_logic_vector (35 downto 0);
+ signal tx_fifo_empty0 : out std_logic;
+ signal tx_fifo_full0 : out std_logic;
+ signal tx_fifo_rdptr0 : out std_logic_vector (3 downto 0);
+ signal tx_fifo_wrptr0 : out std_logic_vector (3 downto 0);
+ signal tx_out0 : out std_logic;
+ signal tx_out1 : out std_logic;
+ signal tx_out2 : out std_logic;
+ signal tx_out3 : out std_logic;
+ signal tx_st_ready0 : out std_logic;
+ signal txcompl0_ext : out std_logic;
+ signal txcompl1_ext : out std_logic;
+ signal txcompl2_ext : out std_logic;
+ signal txcompl3_ext : out std_logic;
+ signal txdata0_ext : out std_logic_vector (7 downto 0);
+ signal txdata1_ext : out std_logic_vector (7 downto 0);
+ signal txdata2_ext : out std_logic_vector (7 downto 0);
+ signal txdata3_ext : out std_logic_vector (7 downto 0);
+ signal txdatak0_ext : out std_logic;
+ signal txdatak1_ext : out std_logic;
+ signal txdatak2_ext : out std_logic;
+ signal txdatak3_ext : out std_logic;
+ signal txdetectrx_ext : out std_logic;
+ signal txelecidle0_ext : out std_logic;
+ signal txelecidle1_ext : out std_logic;
+ signal txelecidle2_ext : out std_logic;
+ signal txelecidle3_ext : out std_logic);
+ end component;
+
+ function is_zero(x : std_logic_vector) return std_logic is
+ constant zero : std_logic_vector(x'length-1 downto 0) := (others => '0');
+ begin
+ if x = zero then
+ return '1';
+ else
+ return '0';
+ end if;
+ end is_zero;
+
+ signal core_clk_out : std_logic;
+ signal rstn : std_logic;
+
+ signal reconfig_clk : std_logic;
+ signal reconfig_busy : std_logic;
+ signal reconfig_fromgxb : std_logic_vector(16 downto 0);
+ signal reconfig_togxb : std_logic_vector(3 downto 0);
+
+ signal tl_cfg_add : std_logic_vector(3 downto 0);
+ signal tl_cfg_ctl : std_logic_vector(31 downto 0);
+
+ signal l2_exit, hotrst_exit, dlup_exit : std_logic;
+ signal npor, crst, srst, rst_reg : std_logic;
+ signal pme_shift : std_logic_vector(4 downto 0);
+
+ signal rx_st_ready0, rx_st_valid0 : std_logic;
+ signal rx_st_data0 : std_logic_vector(63 downto 0);
+
+ signal r64_ready : std_logic_vector(1 downto 0); -- length must equal the latency of the Avalon RX bus
+ signal r64_dat, s64_dat : std_logic_vector(63 downto 0);
+ signal s64_need_refill, s64_filling, s64_valid, s64_advance, r64_full : std_logic;
+
+ signal r32_word, s32_word, s32_progress, r32_full, s32_need_refill : std_logic;
+ signal r32_dat0, r32_dat1 : std_logic_vector(31 downto 0);
+begin
+
+ reconfig_clk <= cal_clk50_i;
+ wb_clk_o <= core_clk_out;
+
+ reconfig : altera_reconfig
+ port map(
+ reconfig_clk => reconfig_clk,
+ reconfig_fromgxb => reconfig_fromgxb,
+ busy => reconfig_busy,
+ reconfig_togxb => reconfig_togxb);
+
+ pcie : altera_pcie
+ port map(
+ -- Clocking
+ refclk => pcie_refclk_i,
+ pld_clk => core_clk_out,
+ core_clk_out => core_clk_out,
+ -- Simulation only clocks:
+ pclk_in => pcie_refclk_i,
+ clk250_out => open,
+ clk500_out => open,
+
+ -- Transceiver control
+ cal_blk_clk => cal_clk50_i, -- All transceivers in FPGA must use the same calibration clock
+ reconfig_clk => reconfig_clk,
+ fixedclk_serdes => clk125_i,
+ gxb_powerdown => '0',
+ pll_powerdown => '0',
+ reconfig_togxb => reconfig_togxb,
+ reconfig_fromgxb => reconfig_fromgxb,
+ busy_altgxb_reconfig => reconfig_busy,
+
+ -- PCIe lanes
+ rx_in0 => pcie_rx_i(0),
+ rx_in1 => pcie_rx_i(1),
+ rx_in2 => pcie_rx_i(2),
+ rx_in3 => pcie_rx_i(3),
+ tx_out0 => pcie_tx_o(0),
+ tx_out1 => pcie_tx_o(1),
+ tx_out2 => pcie_tx_o(2),
+ tx_out3 => pcie_tx_o(3),
+
+ -- Avalon RX
+ rx_st_mask0 => '0',
+ rx_st_ready0 => rx_st_ready0,
+ rx_st_bardec0 => open, -- 7 downto 0
+ rx_st_be0 => open, -- 7 downto 0
+ rx_st_data0 => rx_st_data0, -- 63 downto 0
+ rx_st_eop0 => open,
+ rx_st_err0 => open,
+ rx_st_sop0 => open,
+ rx_st_valid0 => rx_st_valid0,
+ rx_fifo_empty0 => open, -- informative/debug only (ignore in real design)
+ rx_fifo_full0 => open, -- informative/debug only (ignore in real design)
+ -- Errors in RX buffer
+ derr_cor_ext_rcv0 => open,
+ derr_cor_ext_rpl => open,
+ derr_rpl => open,
+ r2c_err0 => open,
+
+ -- Avalon TX
+ tx_st_data0 => (others => '0'),
+ tx_st_eop0 => '0',
+ tx_st_err0 => '0',
+ tx_st_sop0 => '0',
+ tx_st_valid0 => '0',
+ tx_st_ready0 => open,
+ tx_fifo_empty0 => open,
+ tx_fifo_full0 => open,
+ tx_fifo_rdptr0 => open, -- 3 downto 0
+ tx_fifo_wrptr0 => open, -- 3 downto 0
+ -- Avalon TX credit management
+ tx_cred0 => open, -- 35 downto 0
+ npd_alloc_1cred_vc0 => open,
+ npd_cred_vio_vc0 => open,
+ nph_alloc_1cred_vc0 => open,
+ nph_cred_vio_vc0 => open,
+
+ -- Report completion error status
+ cpl_err => (others => '0'), -- 6 downto 0
+ cpl_pending => '0',
+ lmi_addr => (others => '0'), -- 11 downto 0
+ lmi_din => (others => '0'), -- 31 downto 0
+ lmi_rden => '0',
+ lmi_wren => '0',
+ lmi_ack => open,
+ lmi_dout => open, -- 31 downto 0
+ ko_cpl_spc_vc0 => open, -- 19 downto 0
+
+ -- External PHY (PIPE). Not used; using altera PHY.
+ pipe_mode => '0',
+ rxdata0_ext => (others => '0'), -- 7 downto 0
+ rxdata1_ext => (others => '0'), -- 7 downto 0
+ rxdata2_ext => (others => '0'), -- 7 downto 0
+ rxdata3_ext => (others => '0'), -- 7 downto 0
+ rxdatak0_ext => '0',
+ rxdatak1_ext => '0',
+ rxdatak2_ext => '0',
+ rxdatak3_ext => '0',
+ rxelecidle0_ext => '0',
+ rxelecidle1_ext => '0',
+ rxelecidle2_ext => '0',
+ rxelecidle3_ext => '0',
+ rxstatus0_ext => (others => '0'), -- 2 downto 0
+ rxstatus1_ext => (others => '0'), -- 2 downto 0
+ rxstatus2_ext => (others => '0'), -- 2 downto 0
+ rxstatus3_ext => (others => '0'), -- 2 downto 0
+ rxvalid0_ext => '0',
+ rxvalid1_ext => '0',
+ rxvalid2_ext => '0',
+ rxvalid3_ext => '0',
+ rxpolarity0_ext => open,
+ rxpolarity1_ext => open,
+ rxpolarity2_ext => open,
+ rxpolarity3_ext => open,
+ txcompl0_ext => open,
+ txcompl1_ext => open,
+ txcompl2_ext => open,
+ txcompl3_ext => open,
+ txdata0_ext => open,
+ txdata1_ext => open, -- 7 downto 0
+ txdata2_ext => open, -- 7 downto 0
+ txdata3_ext => open, -- 7 downto 0
+ txdatak0_ext => open,
+ txdatak1_ext => open,
+ txdatak2_ext => open,
+ txdatak3_ext => open,
+ txdetectrx_ext => open,
+ txelecidle0_ext => open,
+ txelecidle1_ext => open,
+ txelecidle2_ext => open,
+ txelecidle3_ext => open,
+ phystatus_ext => '0',
+ powerdown_ext => open, -- 1 downto 0
+ rate_ext => open,
+
+ -- PCIe interrupts (for endpoint)
+ app_int_sts => '0',
+ app_msi_num => (others => '0'), -- 4 downto 0
+ app_msi_req => '0',
+ app_msi_tc => (others => '0'), -- 2 downto 0
+ pex_msi_num => (others => '0'), -- 4 downto 0
+ app_int_ack => open,
+ app_msi_ack => open,
+
+ -- PCIe configuration space
+ hpg_ctrler => (others => '0'), -- 4 downto 0
+ tl_cfg_add => tl_cfg_add, -- 3 downto 0
+ tl_cfg_ctl => tl_cfg_ctl, -- 31 downto 0
+ tl_cfg_ctl_wr => open,
+ tl_cfg_sts => open, -- 52 downto 0
+ tl_cfg_sts_wr => open,
+
+ -- Power management signals
+ pm_auxpwr => '0',
+ pm_data => (others => '0'), -- 9 downto 0
+ pm_event => '0',
+ pme_to_cr => pme_shift(pme_shift'length-1),
+ pme_to_sr => pme_shift(0),
+
+ -- Reset and link training
+ npor => npor,
+ srst => srst,
+ crst => crst,
+ l2_exit => l2_exit,
+ hotrst_exit => hotrst_exit,
+ dlup_exit => dlup_exit,
+ suc_spd_neg => open,
+ ltssm => open, -- 4 downto 0
+ rc_pll_locked => open,
+ reset_status => open,
+
+ -- Debugging signals
+ lane_act => open, -- 3 downto 0
+ test_in => (others => '0'), -- 39 downto 0
+ test_out => open, -- 8 downto 0
+
+ -- WTF? Not documented
+ rc_rx_digitalreset => open);
+
+
+ reset : process(core_clk_out)
+ begin
+ if rising_edge(core_clk_out) then
+ pme_shift(pme_shift'length-1 downto 1) <= pme_shift(pme_shift'length-2 downto 0);
+
+ if (l2_exit and hotrst_exit and dlup_exit) = '0' then
+ rst_reg <= '1';
+ crst <= '1';
+ srst <= '1';
+ else
+ rst_reg <= '0';
+ crst <= rst_reg;
+ srst <= rst_reg;
+ end if;
+ end if;
+ end process;
+
+ npor <= rstn_i and pcie_rstn_i;
+ rstn <= rstn_i or rst_reg;
+ rstn_o <= rstn;
+
+ -- Recover bus:device IDs from config space
+ cfg : process(core_clk_out)
+ begin
+ if rising_edge(core_clk_out) then
+ if tl_cfg_add = x"f" then
+ cfg_busdev <= tl_cfg_ctl(12 downto 0);
+ end if;
+ end if;
+ end process;
+
+ -- Stream rx data out as wishbone
+ rx_wb_stb_o <= r32_full;
+ rx_wb_dat_o <= r32_dat0;
+
+ -- Advance state if the WB RX bus made progress
+ s32_progress <= r32_full and not rx_wb_stall_i;
+ s32_word <= (not r32_word) when s32_progress = '1' else r32_word;
+
+ -- The 32-bit buffers become empty when transitioning to word0
+ s32_need_refill <= not r32_full or (r32_word and s32_progress);
+
+ -- Grab data when we need data and there is some ready
+ s64_advance <= s64_valid and s32_need_refill;
+
+ rx_data32 : process(core_clk_out)
+ begin
+ if rising_edge(core_clk_out) then
+ if rstn = '0' then
+ r32_word <= '0';
+ r32_full <= '0';
+ else
+ r32_full <= s64_valid or not s32_need_refill;
+ r32_word <= s32_word;
+ end if;
+
+ if s64_advance = '1' then
+ r32_dat0 <= s64_dat(31 downto 0);
+ r32_dat1 <= s64_dat(63 downto 32);
+ end if;
+
+ if s32_word = '1' then
+ r32_dat0 <= r32_dat1;
+ end if;
+ end if;
+ end process;
+
+ -- Is the Avalon bus filling data this cycle?
+ s64_filling <= rx_st_valid0 and r64_ready(r64_ready'length-1);
+ -- Can we provide data to the 32-bit layer on this cycle?
+ s64_valid <= r64_full or s64_filling;
+ -- We need to refill our buffer if we were empty or just got drained
+ s64_need_refill <= s64_advance or not s64_valid;
+
+ -- Supply the 64-bit data to the 32-bit stream with possible asynchronous bypass
+ s64_dat <= r64_dat when r64_full = '1' else rx_st_data0;
+
+ -- Issue a fetch only if we need refill and no fetch is pending
+ rx_st_ready0 <= s64_need_refill and is_zero(r64_ready(r64_ready'length-2 downto 0));
+
+ rx_data64: process(core_clk_out)
+ begin
+ if rising_edge(core_clk_out) then
+ if rstn = '0' then
+ r64_full <= '0';
+ r64_ready <= (others => '0');
+ else
+ r64_full <= not s64_need_refill;
+ r64_ready <= r64_ready(r64_ready'length-2 downto 0) & rx_st_ready0;
+ end if;
+
+ r64_dat <= s64_dat;
+ end if;
+ end process;
+end rtl;
diff --git a/hdl/pcie_wb.qsf b/hdl/pcie_wb.qsf
index 6327036c8db713bfbf42d34f1067fd697dc94dce..a13201e78fd2bd53c0336e8fd7c9254e11d3cabf 100644
--- a/hdl/pcie_wb.qsf
+++ b/hdl/pcie_wb.qsf
@@ -49,7 +49,6 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
-set_location_assignment PIN_D11 -to pcie_clk125_i
set_location_assignment PIN_U23 -to pcie_refclk_i
set_location_assignment PIN_W1 -to pcie_rstn_i
set_location_assignment PIN_N23 -to pcie_rx_i[3]
@@ -110,6 +109,27 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHZ
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=M9K" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
+set_location_assignment PIN_D11 -to clk125_i
+set_global_assignment -name VHDL_FILE pcie_wb_pkg.vhd
+set_global_assignment -name VHDL_FILE pcie_altera.vhd
set_global_assignment -name VHDL_FILE pow_reset.vhd
set_global_assignment -name QIP_FILE altera_pcie.qip
set_global_assignment -name VHDL_FILE pcie_wb.vhd
@@ -117,5 +137,615 @@ set_global_assignment -name QIP_FILE altera_reconfig.qip
set_global_assignment -name QIP_FILE altera_pcie_pll.qip
set_global_assignment -name SDC_FILE pcie_wb.sdc
set_global_assignment -name SIGNALTAP_FILE stp2.stp
-set_global_assignment -name QIP_FILE flash_loader.qip
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_bardec0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_bardec0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_bardec0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_bardec0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_bardec0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_bardec0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_bardec0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_bardec0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_be0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_be0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_be0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_be0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_be0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_be0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_be0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_be0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[32]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[33]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[34]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[35]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[36]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[37]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[38]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[39]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[40]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[41]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[42]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[43]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[44]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[45]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[46]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[47]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[48]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[49]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[50]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[51]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[52]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[53]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[54]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[55]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[56]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[57]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[58]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[59]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[60]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[61]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[62]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[63]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_err0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_ready0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_sop0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_valid0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "pcie_altera:pcie_phy|cfg_busdev[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "pcie_altera:pcie_phy|cfg_busdev[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "pcie_altera:pcie_phy|cfg_busdev[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "pcie_altera:pcie_phy|cfg_busdev[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "pcie_altera:pcie_phy|cfg_busdev[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "pcie_altera:pcie_phy|cfg_busdev[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "pcie_altera:pcie_phy|cfg_busdev[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "pcie_altera:pcie_phy|cfg_busdev[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "pcie_altera:pcie_phy|cfg_busdev[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "pcie_altera:pcie_phy|cfg_busdev[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "pcie_altera:pcie_phy|cfg_busdev[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "pcie_altera:pcie_phy|cfg_busdev[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "pcie_altera:pcie_phy|cfg_busdev[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "pcie_altera:pcie_phy|r32_dat0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "pcie_altera:pcie_phy|r32_dat0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "pcie_altera:pcie_phy|r32_dat0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "pcie_altera:pcie_phy|r32_dat0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "pcie_altera:pcie_phy|r32_dat0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "pcie_altera:pcie_phy|r32_dat0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "pcie_altera:pcie_phy|r32_dat0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "pcie_altera:pcie_phy|r32_dat0[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "pcie_altera:pcie_phy|r32_dat0[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "pcie_altera:pcie_phy|r32_dat0[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "pcie_altera:pcie_phy|r32_dat0[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "pcie_altera:pcie_phy|r32_dat0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "pcie_altera:pcie_phy|r32_dat0[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "pcie_altera:pcie_phy|r32_dat0[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "pcie_altera:pcie_phy|r32_dat0[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "pcie_altera:pcie_phy|r32_dat0[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "pcie_altera:pcie_phy|r32_dat0[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "pcie_altera:pcie_phy|r32_dat0[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "pcie_altera:pcie_phy|r32_dat0[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "pcie_altera:pcie_phy|r32_dat0[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "pcie_altera:pcie_phy|r32_dat0[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "pcie_altera:pcie_phy|r32_dat0[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "pcie_altera:pcie_phy|r32_dat0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "pcie_altera:pcie_phy|r32_dat0[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "pcie_altera:pcie_phy|r32_dat0[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "pcie_altera:pcie_phy|r32_dat0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "pcie_altera:pcie_phy|r32_dat0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "pcie_altera:pcie_phy|r32_dat0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "pcie_altera:pcie_phy|r32_dat0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "pcie_altera:pcie_phy|r32_dat0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "pcie_altera:pcie_phy|r32_dat0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "pcie_altera:pcie_phy|r32_dat0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "pcie_altera:pcie_phy|r32_dat1[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "pcie_altera:pcie_phy|r32_dat1[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "pcie_altera:pcie_phy|r32_dat1[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "pcie_altera:pcie_phy|r32_dat1[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "pcie_altera:pcie_phy|r32_dat1[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "pcie_altera:pcie_phy|r32_dat1[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "pcie_altera:pcie_phy|r32_dat1[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "pcie_altera:pcie_phy|r32_dat1[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "pcie_altera:pcie_phy|r32_dat1[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "pcie_altera:pcie_phy|r32_dat1[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "pcie_altera:pcie_phy|r32_dat1[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "pcie_altera:pcie_phy|r32_dat1[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "pcie_altera:pcie_phy|r32_dat1[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "pcie_altera:pcie_phy|r32_dat1[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "pcie_altera:pcie_phy|r32_dat1[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "pcie_altera:pcie_phy|r32_dat1[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "pcie_altera:pcie_phy|r32_dat1[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "pcie_altera:pcie_phy|r32_dat1[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "pcie_altera:pcie_phy|r32_dat1[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[148] -to "pcie_altera:pcie_phy|r32_dat1[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[149] -to "pcie_altera:pcie_phy|r32_dat1[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[150] -to "pcie_altera:pcie_phy|r32_dat1[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[151] -to "pcie_altera:pcie_phy|r32_dat1[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[152] -to "pcie_altera:pcie_phy|r32_dat1[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[153] -to "pcie_altera:pcie_phy|r32_dat1[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[154] -to "pcie_altera:pcie_phy|r32_dat1[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[155] -to "pcie_altera:pcie_phy|r32_dat1[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[156] -to "pcie_altera:pcie_phy|r32_dat1[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[157] -to "pcie_altera:pcie_phy|r32_dat1[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[158] -to "pcie_altera:pcie_phy|r32_dat1[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[159] -to "pcie_altera:pcie_phy|r32_dat1[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[160] -to "pcie_altera:pcie_phy|r32_dat1[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[161] -to "pcie_altera:pcie_phy|r32_full" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[162] -to "pcie_altera:pcie_phy|r32_word" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[163] -to "pcie_altera:pcie_phy|r64_dat[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[164] -to "pcie_altera:pcie_phy|r64_dat[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[165] -to "pcie_altera:pcie_phy|r64_dat[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[166] -to "pcie_altera:pcie_phy|r64_dat[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[167] -to "pcie_altera:pcie_phy|r64_dat[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[168] -to "pcie_altera:pcie_phy|r64_dat[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[169] -to "pcie_altera:pcie_phy|r64_dat[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[170] -to "pcie_altera:pcie_phy|r64_dat[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[171] -to "pcie_altera:pcie_phy|r64_dat[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[172] -to "pcie_altera:pcie_phy|r64_dat[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[173] -to "pcie_altera:pcie_phy|r64_dat[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[174] -to "pcie_altera:pcie_phy|r64_dat[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[175] -to "pcie_altera:pcie_phy|r64_dat[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[176] -to "pcie_altera:pcie_phy|r64_dat[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[177] -to "pcie_altera:pcie_phy|r64_dat[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[178] -to "pcie_altera:pcie_phy|r64_dat[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[179] -to "pcie_altera:pcie_phy|r64_dat[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[180] -to "pcie_altera:pcie_phy|r64_dat[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[181] -to "pcie_altera:pcie_phy|r64_dat[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[182] -to "pcie_altera:pcie_phy|r64_dat[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[183] -to "pcie_altera:pcie_phy|r64_dat[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[184] -to "pcie_altera:pcie_phy|r64_dat[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[185] -to "pcie_altera:pcie_phy|r64_dat[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[186] -to "pcie_altera:pcie_phy|r64_dat[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[187] -to "pcie_altera:pcie_phy|r64_dat[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[188] -to "pcie_altera:pcie_phy|r64_dat[32]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[189] -to "pcie_altera:pcie_phy|r64_dat[33]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[190] -to "pcie_altera:pcie_phy|r64_dat[34]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[191] -to "pcie_altera:pcie_phy|r64_dat[35]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[192] -to "pcie_altera:pcie_phy|r64_dat[36]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[193] -to "pcie_altera:pcie_phy|r64_dat[37]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[194] -to "pcie_altera:pcie_phy|r64_dat[38]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[195] -to "pcie_altera:pcie_phy|r64_dat[39]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[196] -to "pcie_altera:pcie_phy|r64_dat[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[197] -to "pcie_altera:pcie_phy|r64_dat[40]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[198] -to "pcie_altera:pcie_phy|r64_dat[41]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[199] -to "pcie_altera:pcie_phy|r64_dat[42]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[200] -to "pcie_altera:pcie_phy|r64_dat[43]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[201] -to "pcie_altera:pcie_phy|r64_dat[44]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[202] -to "pcie_altera:pcie_phy|r64_dat[45]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[203] -to "pcie_altera:pcie_phy|r64_dat[46]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[204] -to "pcie_altera:pcie_phy|r64_dat[47]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[205] -to "pcie_altera:pcie_phy|r64_dat[48]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[206] -to "pcie_altera:pcie_phy|r64_dat[49]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[207] -to "pcie_altera:pcie_phy|r64_dat[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[208] -to "pcie_altera:pcie_phy|r64_dat[50]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[209] -to "pcie_altera:pcie_phy|r64_dat[51]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[210] -to "pcie_altera:pcie_phy|r64_dat[52]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[211] -to "pcie_altera:pcie_phy|r64_dat[53]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[212] -to "pcie_altera:pcie_phy|r64_dat[54]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[213] -to "pcie_altera:pcie_phy|r64_dat[55]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[214] -to "pcie_altera:pcie_phy|r64_dat[56]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[215] -to "pcie_altera:pcie_phy|r64_dat[57]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[216] -to "pcie_altera:pcie_phy|r64_dat[58]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[217] -to "pcie_altera:pcie_phy|r64_dat[59]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[218] -to "pcie_altera:pcie_phy|r64_dat[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[219] -to "pcie_altera:pcie_phy|r64_dat[60]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[220] -to "pcie_altera:pcie_phy|r64_dat[61]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[221] -to "pcie_altera:pcie_phy|r64_dat[62]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[222] -to "pcie_altera:pcie_phy|r64_dat[63]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[223] -to "pcie_altera:pcie_phy|r64_dat[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[224] -to "pcie_altera:pcie_phy|r64_dat[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[225] -to "pcie_altera:pcie_phy|r64_dat[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[226] -to "pcie_altera:pcie_phy|r64_dat[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[227] -to "pcie_altera:pcie_phy|r64_full" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[228] -to "pcie_altera:pcie_phy|r64_ready[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[229] -to "pcie_altera:pcie_phy|r64_ready[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[230] -to "pcie_altera:pcie_phy|s32_need_refill" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[231] -to "pcie_altera:pcie_phy|s32_progress" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[232] -to "pcie_altera:pcie_phy|s32_word" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[233] -to "pcie_altera:pcie_phy|s64_advance" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[234] -to "pcie_altera:pcie_phy|s64_dat[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[235] -to "pcie_altera:pcie_phy|s64_dat[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[236] -to "pcie_altera:pcie_phy|s64_dat[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[237] -to "pcie_altera:pcie_phy|s64_dat[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[238] -to "pcie_altera:pcie_phy|s64_dat[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[239] -to "pcie_altera:pcie_phy|s64_dat[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[240] -to "pcie_altera:pcie_phy|s64_dat[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[241] -to "pcie_altera:pcie_phy|s64_dat[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[242] -to "pcie_altera:pcie_phy|s64_dat[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[243] -to "pcie_altera:pcie_phy|s64_dat[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[244] -to "pcie_altera:pcie_phy|s64_dat[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[245] -to "pcie_altera:pcie_phy|s64_dat[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[246] -to "pcie_altera:pcie_phy|s64_dat[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[247] -to "pcie_altera:pcie_phy|s64_dat[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[248] -to "pcie_altera:pcie_phy|s64_dat[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[249] -to "pcie_altera:pcie_phy|s64_dat[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[250] -to "pcie_altera:pcie_phy|s64_dat[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[251] -to "pcie_altera:pcie_phy|s64_dat[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[252] -to "pcie_altera:pcie_phy|s64_dat[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[253] -to "pcie_altera:pcie_phy|s64_dat[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[254] -to "pcie_altera:pcie_phy|s64_dat[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[255] -to "pcie_altera:pcie_phy|s64_dat[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[256] -to "pcie_altera:pcie_phy|s64_dat[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[257] -to "pcie_altera:pcie_phy|s64_dat[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[258] -to "pcie_altera:pcie_phy|s64_dat[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[259] -to "pcie_altera:pcie_phy|s64_dat[32]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[260] -to "pcie_altera:pcie_phy|s64_dat[33]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[261] -to "pcie_altera:pcie_phy|s64_dat[34]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[262] -to "pcie_altera:pcie_phy|s64_dat[35]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[263] -to "pcie_altera:pcie_phy|s64_dat[36]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[264] -to "pcie_altera:pcie_phy|s64_dat[37]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[265] -to "pcie_altera:pcie_phy|s64_dat[38]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[266] -to "pcie_altera:pcie_phy|s64_dat[39]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[267] -to "pcie_altera:pcie_phy|s64_dat[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[268] -to "pcie_altera:pcie_phy|s64_dat[40]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[269] -to "pcie_altera:pcie_phy|s64_dat[41]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[270] -to "pcie_altera:pcie_phy|s64_dat[42]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[271] -to "pcie_altera:pcie_phy|s64_dat[43]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[272] -to "pcie_altera:pcie_phy|s64_dat[44]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[273] -to "pcie_altera:pcie_phy|s64_dat[45]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[274] -to "pcie_altera:pcie_phy|s64_dat[46]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[275] -to "pcie_altera:pcie_phy|s64_dat[47]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[276] -to "pcie_altera:pcie_phy|s64_dat[48]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[277] -to "pcie_altera:pcie_phy|s64_dat[49]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[278] -to "pcie_altera:pcie_phy|s64_dat[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[279] -to "pcie_altera:pcie_phy|s64_dat[50]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[280] -to "pcie_altera:pcie_phy|s64_dat[51]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[281] -to "pcie_altera:pcie_phy|s64_dat[52]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[282] -to "pcie_altera:pcie_phy|s64_dat[53]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[283] -to "pcie_altera:pcie_phy|s64_dat[54]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[284] -to "pcie_altera:pcie_phy|s64_dat[55]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[285] -to "pcie_altera:pcie_phy|s64_dat[56]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[286] -to "pcie_altera:pcie_phy|s64_dat[57]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[287] -to "pcie_altera:pcie_phy|s64_dat[58]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[288] -to "pcie_altera:pcie_phy|s64_dat[59]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[289] -to "pcie_altera:pcie_phy|s64_dat[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[290] -to "pcie_altera:pcie_phy|s64_dat[60]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[291] -to "pcie_altera:pcie_phy|s64_dat[61]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[292] -to "pcie_altera:pcie_phy|s64_dat[62]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[293] -to "pcie_altera:pcie_phy|s64_dat[63]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[294] -to "pcie_altera:pcie_phy|s64_dat[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[295] -to "pcie_altera:pcie_phy|s64_dat[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[296] -to "pcie_altera:pcie_phy|s64_dat[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[297] -to "pcie_altera:pcie_phy|s64_dat[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[298] -to "pcie_altera:pcie_phy|s64_filling" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_bardec0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_bardec0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_bardec0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_bardec0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_bardec0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_bardec0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_bardec0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_bardec0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_be0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_be0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_be0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_be0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_be0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_be0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_be0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_be0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[32]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[33]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[34]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[35]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[36]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[37]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[38]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[39]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[40]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[41]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[42]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[43]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[44]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[45]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[46]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[47]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[48]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[49]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[50]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[51]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[52]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[53]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[54]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[55]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[56]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[57]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[58]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[59]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[60]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[61]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[62]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[63]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_data0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_err0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_ready0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_sop0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "pcie_altera:pcie_phy|altera_pcie:pcie|rx_st_valid0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "pcie_altera:pcie_phy|cfg_busdev[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "pcie_altera:pcie_phy|cfg_busdev[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "pcie_altera:pcie_phy|cfg_busdev[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "pcie_altera:pcie_phy|cfg_busdev[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "pcie_altera:pcie_phy|cfg_busdev[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "pcie_altera:pcie_phy|cfg_busdev[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "pcie_altera:pcie_phy|cfg_busdev[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "pcie_altera:pcie_phy|cfg_busdev[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "pcie_altera:pcie_phy|cfg_busdev[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "pcie_altera:pcie_phy|cfg_busdev[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "pcie_altera:pcie_phy|cfg_busdev[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "pcie_altera:pcie_phy|cfg_busdev[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "pcie_altera:pcie_phy|cfg_busdev[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "pcie_altera:pcie_phy|r32_dat0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "pcie_altera:pcie_phy|r32_dat0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "pcie_altera:pcie_phy|r32_dat0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "pcie_altera:pcie_phy|r32_dat0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "pcie_altera:pcie_phy|r32_dat0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "pcie_altera:pcie_phy|r32_dat0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "pcie_altera:pcie_phy|r32_dat0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "pcie_altera:pcie_phy|r32_dat0[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "pcie_altera:pcie_phy|r32_dat0[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "pcie_altera:pcie_phy|r32_dat0[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "pcie_altera:pcie_phy|r32_dat0[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "pcie_altera:pcie_phy|r32_dat0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "pcie_altera:pcie_phy|r32_dat0[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "pcie_altera:pcie_phy|r32_dat0[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "pcie_altera:pcie_phy|r32_dat0[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "pcie_altera:pcie_phy|r32_dat0[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "pcie_altera:pcie_phy|r32_dat0[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "pcie_altera:pcie_phy|r32_dat0[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "pcie_altera:pcie_phy|r32_dat0[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "pcie_altera:pcie_phy|r32_dat0[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "pcie_altera:pcie_phy|r32_dat0[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "pcie_altera:pcie_phy|r32_dat0[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "pcie_altera:pcie_phy|r32_dat0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "pcie_altera:pcie_phy|r32_dat0[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "pcie_altera:pcie_phy|r32_dat0[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "pcie_altera:pcie_phy|r32_dat0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "pcie_altera:pcie_phy|r32_dat0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "pcie_altera:pcie_phy|r32_dat0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "pcie_altera:pcie_phy|r32_dat0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "pcie_altera:pcie_phy|r32_dat0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "pcie_altera:pcie_phy|r32_dat0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "pcie_altera:pcie_phy|r32_dat0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "pcie_altera:pcie_phy|r32_dat1[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "pcie_altera:pcie_phy|r32_dat1[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "pcie_altera:pcie_phy|r32_dat1[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "pcie_altera:pcie_phy|r32_dat1[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "pcie_altera:pcie_phy|r32_dat1[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "pcie_altera:pcie_phy|r32_dat1[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "pcie_altera:pcie_phy|r32_dat1[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "pcie_altera:pcie_phy|r32_dat1[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "pcie_altera:pcie_phy|r32_dat1[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "pcie_altera:pcie_phy|r32_dat1[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "pcie_altera:pcie_phy|r32_dat1[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "pcie_altera:pcie_phy|r32_dat1[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "pcie_altera:pcie_phy|r32_dat1[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "pcie_altera:pcie_phy|r32_dat1[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "pcie_altera:pcie_phy|r32_dat1[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "pcie_altera:pcie_phy|r32_dat1[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "pcie_altera:pcie_phy|r32_dat1[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "pcie_altera:pcie_phy|r32_dat1[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "pcie_altera:pcie_phy|r32_dat1[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "pcie_altera:pcie_phy|r32_dat1[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "pcie_altera:pcie_phy|r32_dat1[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "pcie_altera:pcie_phy|r32_dat1[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "pcie_altera:pcie_phy|r32_dat1[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "pcie_altera:pcie_phy|r32_dat1[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "pcie_altera:pcie_phy|r32_dat1[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "pcie_altera:pcie_phy|r32_dat1[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "pcie_altera:pcie_phy|r32_dat1[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "pcie_altera:pcie_phy|r32_dat1[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "pcie_altera:pcie_phy|r32_dat1[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "pcie_altera:pcie_phy|r32_dat1[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "pcie_altera:pcie_phy|r32_dat1[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "pcie_altera:pcie_phy|r32_dat1[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "pcie_altera:pcie_phy|r32_full" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "pcie_altera:pcie_phy|r32_word" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "pcie_altera:pcie_phy|r64_dat[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to "pcie_altera:pcie_phy|r64_dat[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to "pcie_altera:pcie_phy|r64_dat[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to "pcie_altera:pcie_phy|r64_dat[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to "pcie_altera:pcie_phy|r64_dat[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to "pcie_altera:pcie_phy|r64_dat[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to "pcie_altera:pcie_phy|r64_dat[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to "pcie_altera:pcie_phy|r64_dat[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to "pcie_altera:pcie_phy|r64_dat[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to "pcie_altera:pcie_phy|r64_dat[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to "pcie_altera:pcie_phy|r64_dat[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to "pcie_altera:pcie_phy|r64_dat[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[175] -to "pcie_altera:pcie_phy|r64_dat[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[176] -to "pcie_altera:pcie_phy|r64_dat[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[177] -to "pcie_altera:pcie_phy|r64_dat[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[178] -to "pcie_altera:pcie_phy|r64_dat[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[179] -to "pcie_altera:pcie_phy|r64_dat[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[180] -to "pcie_altera:pcie_phy|r64_dat[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[181] -to "pcie_altera:pcie_phy|r64_dat[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[182] -to "pcie_altera:pcie_phy|r64_dat[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[183] -to "pcie_altera:pcie_phy|r64_dat[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[184] -to "pcie_altera:pcie_phy|r64_dat[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[185] -to "pcie_altera:pcie_phy|r64_dat[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[186] -to "pcie_altera:pcie_phy|r64_dat[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[187] -to "pcie_altera:pcie_phy|r64_dat[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[188] -to "pcie_altera:pcie_phy|r64_dat[32]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[189] -to "pcie_altera:pcie_phy|r64_dat[33]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[190] -to "pcie_altera:pcie_phy|r64_dat[34]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[191] -to "pcie_altera:pcie_phy|r64_dat[35]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[192] -to "pcie_altera:pcie_phy|r64_dat[36]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[193] -to "pcie_altera:pcie_phy|r64_dat[37]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[194] -to "pcie_altera:pcie_phy|r64_dat[38]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[195] -to "pcie_altera:pcie_phy|r64_dat[39]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[196] -to "pcie_altera:pcie_phy|r64_dat[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[197] -to "pcie_altera:pcie_phy|r64_dat[40]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[198] -to "pcie_altera:pcie_phy|r64_dat[41]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[199] -to "pcie_altera:pcie_phy|r64_dat[42]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[200] -to "pcie_altera:pcie_phy|r64_dat[43]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[201] -to "pcie_altera:pcie_phy|r64_dat[44]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[202] -to "pcie_altera:pcie_phy|r64_dat[45]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[203] -to "pcie_altera:pcie_phy|r64_dat[46]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[204] -to "pcie_altera:pcie_phy|r64_dat[47]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[205] -to "pcie_altera:pcie_phy|r64_dat[48]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[206] -to "pcie_altera:pcie_phy|r64_dat[49]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[207] -to "pcie_altera:pcie_phy|r64_dat[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[208] -to "pcie_altera:pcie_phy|r64_dat[50]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[209] -to "pcie_altera:pcie_phy|r64_dat[51]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[210] -to "pcie_altera:pcie_phy|r64_dat[52]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[211] -to "pcie_altera:pcie_phy|r64_dat[53]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[212] -to "pcie_altera:pcie_phy|r64_dat[54]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[213] -to "pcie_altera:pcie_phy|r64_dat[55]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[214] -to "pcie_altera:pcie_phy|r64_dat[56]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[215] -to "pcie_altera:pcie_phy|r64_dat[57]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[216] -to "pcie_altera:pcie_phy|r64_dat[58]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[217] -to "pcie_altera:pcie_phy|r64_dat[59]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[218] -to "pcie_altera:pcie_phy|r64_dat[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[219] -to "pcie_altera:pcie_phy|r64_dat[60]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[220] -to "pcie_altera:pcie_phy|r64_dat[61]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[221] -to "pcie_altera:pcie_phy|r64_dat[62]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[222] -to "pcie_altera:pcie_phy|r64_dat[63]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[223] -to "pcie_altera:pcie_phy|r64_dat[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[224] -to "pcie_altera:pcie_phy|r64_dat[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[225] -to "pcie_altera:pcie_phy|r64_dat[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[226] -to "pcie_altera:pcie_phy|r64_dat[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[227] -to "pcie_altera:pcie_phy|r64_full" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[228] -to "pcie_altera:pcie_phy|r64_ready[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[229] -to "pcie_altera:pcie_phy|r64_ready[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[230] -to "pcie_altera:pcie_phy|s32_need_refill" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[231] -to "pcie_altera:pcie_phy|s32_progress" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[232] -to "pcie_altera:pcie_phy|s32_word" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[233] -to "pcie_altera:pcie_phy|s64_advance" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[234] -to "pcie_altera:pcie_phy|s64_dat[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[235] -to "pcie_altera:pcie_phy|s64_dat[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[236] -to "pcie_altera:pcie_phy|s64_dat[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[237] -to "pcie_altera:pcie_phy|s64_dat[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[238] -to "pcie_altera:pcie_phy|s64_dat[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[239] -to "pcie_altera:pcie_phy|s64_dat[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[240] -to "pcie_altera:pcie_phy|s64_dat[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[241] -to "pcie_altera:pcie_phy|s64_dat[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[242] -to "pcie_altera:pcie_phy|s64_dat[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[243] -to "pcie_altera:pcie_phy|s64_dat[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[244] -to "pcie_altera:pcie_phy|s64_dat[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[245] -to "pcie_altera:pcie_phy|s64_dat[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[246] -to "pcie_altera:pcie_phy|s64_dat[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[247] -to "pcie_altera:pcie_phy|s64_dat[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[248] -to "pcie_altera:pcie_phy|s64_dat[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[249] -to "pcie_altera:pcie_phy|s64_dat[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[250] -to "pcie_altera:pcie_phy|s64_dat[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[251] -to "pcie_altera:pcie_phy|s64_dat[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[252] -to "pcie_altera:pcie_phy|s64_dat[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[253] -to "pcie_altera:pcie_phy|s64_dat[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[254] -to "pcie_altera:pcie_phy|s64_dat[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[255] -to "pcie_altera:pcie_phy|s64_dat[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[256] -to "pcie_altera:pcie_phy|s64_dat[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[257] -to "pcie_altera:pcie_phy|s64_dat[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[258] -to "pcie_altera:pcie_phy|s64_dat[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[259] -to "pcie_altera:pcie_phy|s64_dat[32]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[260] -to "pcie_altera:pcie_phy|s64_dat[33]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[261] -to "pcie_altera:pcie_phy|s64_dat[34]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[262] -to "pcie_altera:pcie_phy|s64_dat[35]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[263] -to "pcie_altera:pcie_phy|s64_dat[36]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[264] -to "pcie_altera:pcie_phy|s64_dat[37]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[265] -to "pcie_altera:pcie_phy|s64_dat[38]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[266] -to "pcie_altera:pcie_phy|s64_dat[39]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[267] -to "pcie_altera:pcie_phy|s64_dat[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[268] -to "pcie_altera:pcie_phy|s64_dat[40]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[269] -to "pcie_altera:pcie_phy|s64_dat[41]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[270] -to "pcie_altera:pcie_phy|s64_dat[42]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[271] -to "pcie_altera:pcie_phy|s64_dat[43]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[272] -to "pcie_altera:pcie_phy|s64_dat[44]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[273] -to "pcie_altera:pcie_phy|s64_dat[45]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[274] -to "pcie_altera:pcie_phy|s64_dat[46]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[275] -to "pcie_altera:pcie_phy|s64_dat[47]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[276] -to "pcie_altera:pcie_phy|s64_dat[48]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[277] -to "pcie_altera:pcie_phy|s64_dat[49]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[278] -to "pcie_altera:pcie_phy|s64_dat[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[279] -to "pcie_altera:pcie_phy|s64_dat[50]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[280] -to "pcie_altera:pcie_phy|s64_dat[51]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[281] -to "pcie_altera:pcie_phy|s64_dat[52]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[282] -to "pcie_altera:pcie_phy|s64_dat[53]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[283] -to "pcie_altera:pcie_phy|s64_dat[54]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[284] -to "pcie_altera:pcie_phy|s64_dat[55]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[285] -to "pcie_altera:pcie_phy|s64_dat[56]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[286] -to "pcie_altera:pcie_phy|s64_dat[57]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[287] -to "pcie_altera:pcie_phy|s64_dat[58]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[288] -to "pcie_altera:pcie_phy|s64_dat[59]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[289] -to "pcie_altera:pcie_phy|s64_dat[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[290] -to "pcie_altera:pcie_phy|s64_dat[60]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[291] -to "pcie_altera:pcie_phy|s64_dat[61]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[292] -to "pcie_altera:pcie_phy|s64_dat[62]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[293] -to "pcie_altera:pcie_phy|s64_dat[63]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[294] -to "pcie_altera:pcie_phy|s64_dat[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[295] -to "pcie_altera:pcie_phy|s64_dat[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[296] -to "pcie_altera:pcie_phy|s64_dat[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[297] -to "pcie_altera:pcie_phy|s64_dat[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[298] -to "pcie_altera:pcie_phy|s64_filling" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "pcie_altera:pcie_phy|altera_pcie:pcie|altera_pcie_serdes:serdes|altera_pcie_serdes_alt4gxb_td9b:altera_pcie_serdes_alt4gxb_td9b_component|coreclkout[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[299] -to "pcie_altera:pcie_phy|s64_need_refill" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[300] -to "pcie_altera:pcie_phy|s64_valid" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[301] -to stall -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[299] -to "pcie_altera:pcie_phy|s64_need_refill" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[300] -to "pcie_altera:pcie_phy|s64_valid" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[301] -to stall -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=302" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=302" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=927" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=21514" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=8469" -section_id auto_signaltap_0
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/hdl/pcie_wb.sdc b/hdl/pcie_wb.sdc
index 5704e563b53e92fdfab90acf827cf6ca76dba022..7e575fdd555bf9a4978010526e161fd8569d0e4f 100644
--- a/hdl/pcie_wb.sdc
+++ b/hdl/pcie_wb.sdc
@@ -1,4 +1,4 @@
-create_clock -period "125 MHz" -name {pcie_clk125_i} {pcie_clk125_i}
+create_clock -period "125 MHz" -name {clk125_i} {clk125_i}
create_clock -period "100 MHz" -name {pcie_refclk_i} {pcie_refclk_i}
derive_pll_clocks
derive_clock_uncertainty
\ No newline at end of file
diff --git a/hdl/pcie_wb.vhd b/hdl/pcie_wb.vhd
index 22e7ec24e3b2d5274e7ed4be9e510a0e13879cb1..3ead9851feed5c2a1f461b0704fa2132dd694e7d 100644
--- a/hdl/pcie_wb.vhd
+++ b/hdl/pcie_wb.vhd
@@ -2,439 +2,94 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
+library work;
+use work.pcie_wb_pkg.all;
+
entity pcie_wb is
port(
- pcie_clk125_i : in std_logic; -- 125 MHz
- pcie_refclk_i : in std_logic; -- 100 MHz
+ clk125_i : in std_logic; -- 125 MHz, free running
+-- cal_clk50_i : in std_logic; -- 50 MHz, shared between all PHYs
+-- rstn_i : in std_logic;
+
+ pcie_refclk_i : in std_logic; -- 100 MHz, must not derive clk125_i or cal_clk50_i
pcie_rstn_i : in std_logic;
pcie_rx_i : in std_logic_vector(3 downto 0);
pcie_tx_o : out std_logic_vector(3 downto 0);
+
led_o : out std_logic_vector(0 to 7));
end pcie_wb;
architecture rtl of pcie_wb is
- component altera_reconfig is
- port(
- reconfig_clk : in std_logic;
- reconfig_fromgxb : in std_logic_vector(16 downto 0);
- busy : out std_logic;
- reconfig_togxb : out std_logic_vector(3 downto 0));
- end component;
-
component altera_pcie_pll is
port(
areset : in std_logic := '0';
inclk0 : in std_logic := '0';
c0 : out std_logic;
- c1 : out std_logic;
locked : out std_logic);
end component;
- component flash_loader is
- port(
- noe_in : in std_logic
- );
- end component;
-
component pow_reset is
- port (
+ port (
clk : in std_logic; -- 125Mhz
nreset : buffer std_logic
);
end component;
- component altera_pcie is
- port (
- signal app_int_sts : in std_logic;
- signal app_msi_num : in std_logic_vector (4 downto 0);
- signal app_msi_req : in std_logic;
- signal app_msi_tc : in std_logic_vector (2 downto 0);
- signal busy_altgxb_reconfig : in std_logic;
- signal cal_blk_clk : in std_logic;
- signal cpl_err : in std_logic_vector (6 downto 0);
- signal cpl_pending : in std_logic;
- signal crst : in std_logic;
- signal fixedclk_serdes : in std_logic;
- signal gxb_powerdown : in std_logic;
- signal hpg_ctrler : in std_logic_vector (4 downto 0);
- signal lmi_addr : in std_logic_vector (11 downto 0);
- signal lmi_din : in std_logic_vector (31 downto 0);
- signal lmi_rden : in std_logic;
- signal lmi_wren : in std_logic;
- signal npor : in std_logic;
- signal pclk_in : in std_logic;
- signal pex_msi_num : in std_logic_vector (4 downto 0);
- signal phystatus_ext : in std_logic;
- signal pipe_mode : in std_logic;
- signal pld_clk : in std_logic;
- signal pll_powerdown : in std_logic;
- signal pm_auxpwr : in std_logic;
- signal pm_data : in std_logic_vector (9 downto 0);
- signal pm_event : in std_logic;
- signal pme_to_cr : in std_logic;
- signal reconfig_clk : in std_logic;
- signal reconfig_togxb : in std_logic_vector (3 downto 0);
- signal refclk : in std_logic;
- signal rx_in0 : in std_logic;
- signal rx_in1 : in std_logic;
- signal rx_in2 : in std_logic;
- signal rx_in3 : in std_logic;
- signal rx_st_mask0 : in std_logic;
- signal rx_st_ready0 : in std_logic;
- signal rxdata0_ext : in std_logic_vector (7 downto 0);
- signal rxdata1_ext : in std_logic_vector (7 downto 0);
- signal rxdata2_ext : in std_logic_vector (7 downto 0);
- signal rxdata3_ext : in std_logic_vector (7 downto 0);
- signal rxdatak0_ext : in std_logic;
- signal rxdatak1_ext : in std_logic;
- signal rxdatak2_ext : in std_logic;
- signal rxdatak3_ext : in std_logic;
- signal rxelecidle0_ext : in std_logic;
- signal rxelecidle1_ext : in std_logic;
- signal rxelecidle2_ext : in std_logic;
- signal rxelecidle3_ext : in std_logic;
- signal rxstatus0_ext : in std_logic_vector (2 downto 0);
- signal rxstatus1_ext : in std_logic_vector (2 downto 0);
- signal rxstatus2_ext : in std_logic_vector (2 downto 0);
- signal rxstatus3_ext : in std_logic_vector (2 downto 0);
- signal rxvalid0_ext : in std_logic;
- signal rxvalid1_ext : in std_logic;
- signal rxvalid2_ext : in std_logic;
- signal rxvalid3_ext : in std_logic;
- signal srst : in std_logic;
- signal test_in : in std_logic_vector (39 downto 0);
- signal tx_st_data0 : in std_logic_vector (63 downto 0);
- signal tx_st_eop0 : in std_logic;
- signal tx_st_err0 : in std_logic;
- signal tx_st_sop0 : in std_logic;
- signal tx_st_valid0 : in std_logic;
- signal app_int_ack : out std_logic;
- signal app_msi_ack : out std_logic;
- signal clk250_out : out std_logic;
- signal clk500_out : out std_logic;
- signal core_clk_out : out std_logic;
- signal derr_cor_ext_rcv0 : out std_logic;
- signal derr_cor_ext_rpl : out std_logic;
- signal derr_rpl : out std_logic;
- signal dlup_exit : out std_logic;
- signal hotrst_exit : out std_logic;
- signal ko_cpl_spc_vc0 : out std_logic_vector (19 downto 0);
- signal l2_exit : out std_logic;
- signal lane_act : out std_logic_vector (3 downto 0);
- signal lmi_ack : out std_logic;
- signal lmi_dout : out std_logic_vector (31 downto 0);
- signal ltssm : out std_logic_vector (4 downto 0);
- signal npd_alloc_1cred_vc0 : out std_logic;
- signal npd_cred_vio_vc0 : out std_logic;
- signal nph_alloc_1cred_vc0 : out std_logic;
- signal nph_cred_vio_vc0 : out std_logic;
- signal pme_to_sr : out std_logic;
- signal powerdown_ext : out std_logic_vector (1 downto 0);
- signal r2c_err0 : out std_logic;
- signal rate_ext : out std_logic;
- signal rc_pll_locked : out std_logic;
- signal rc_rx_digitalreset : out std_logic;
- signal reconfig_fromgxb : out std_logic_vector (16 downto 0);
- signal reset_status : out std_logic;
- signal rx_fifo_empty0 : out std_logic;
- signal rx_fifo_full0 : out std_logic;
- signal rx_st_bardec0 : out std_logic_vector (7 downto 0);
- signal rx_st_be0 : out std_logic_vector (7 downto 0);
- signal rx_st_data0 : out std_logic_vector (63 downto 0);
- signal rx_st_eop0 : out std_logic;
- signal rx_st_err0 : out std_logic;
- signal rx_st_sop0 : out std_logic;
- signal rx_st_valid0 : out std_logic;
- signal rxpolarity0_ext : out std_logic;
- signal rxpolarity1_ext : out std_logic;
- signal rxpolarity2_ext : out std_logic;
- signal rxpolarity3_ext : out std_logic;
- signal suc_spd_neg : out std_logic;
- signal test_out : out std_logic_vector (8 downto 0);
- signal tl_cfg_add : out std_logic_vector (3 downto 0);
- signal tl_cfg_ctl : out std_logic_vector (31 downto 0);
- signal tl_cfg_ctl_wr : out std_logic;
- signal tl_cfg_sts : out std_logic_vector (52 downto 0);
- signal tl_cfg_sts_wr : out std_logic;
- signal tx_cred0 : out std_logic_vector (35 downto 0);
- signal tx_fifo_empty0 : out std_logic;
- signal tx_fifo_full0 : out std_logic;
- signal tx_fifo_rdptr0 : out std_logic_vector (3 downto 0);
- signal tx_fifo_wrptr0 : out std_logic_vector (3 downto 0);
- signal tx_out0 : out std_logic;
- signal tx_out1 : out std_logic;
- signal tx_out2 : out std_logic;
- signal tx_out3 : out std_logic;
- signal tx_st_ready0 : out std_logic;
- signal txcompl0_ext : out std_logic;
- signal txcompl1_ext : out std_logic;
- signal txcompl2_ext : out std_logic;
- signal txcompl3_ext : out std_logic;
- signal txdata0_ext : out std_logic_vector (7 downto 0);
- signal txdata1_ext : out std_logic_vector (7 downto 0);
- signal txdata2_ext : out std_logic_vector (7 downto 0);
- signal txdata3_ext : out std_logic_vector (7 downto 0);
- signal txdatak0_ext : out std_logic;
- signal txdatak1_ext : out std_logic;
- signal txdatak2_ext : out std_logic;
- signal txdatak3_ext : out std_logic;
- signal txdetectrx_ext : out std_logic;
- signal txelecidle0_ext : out std_logic;
- signal txelecidle1_ext : out std_logic;
- signal txelecidle2_ext : out std_logic;
- signal txelecidle3_ext : out std_logic);
- end component;
-
- signal cal_blk_clk : std_logic;
- signal core_clk_out : std_logic;
-
- signal reconfig_clk : std_logic;
- signal reconfig_fromgxb : std_logic_vector(16 downto 0);
- signal reconfig_togxb : std_logic_vector(3 downto 0);
+ signal cal_blk_clk, wb_clk : std_logic; -- Should be input in final version
signal count : unsigned(26 downto 0) := to_unsigned(0, 27);
signal led_r : std_logic := '0';
- signal locked : std_logic;
-
- signal l2_exit, hotrst_exit, dlup_exit : std_logic;
- signal npor, crst, srst, rst_reg : std_logic;
- signal pme_shift : std_logic_vector(4 downto 0);
- signal ltssm : std_logic_vector(4 downto 0);
+ signal locked, pow_rstn, rstn, stall : std_logic;
- signal nreset: std_logic;
- signal test_in: std_logic_vector(39 downto 0);
- signal busy_reconfig: std_logic;
+ constant stall_pattern : std_logic_vector(15 downto 0) := "1111010110111100";
+ signal stall_idx : unsigned(3 downto 0);
begin
- test_in <= (others => '0'); -- ))"0000000000000000000000000000000010001000"; -- disable low power state negotiation
-
-
reset : pow_reset
port map (
- clk => pcie_clk125_i,
- nreset => nreset
+ clk => clk125_i,
+ nreset => pow_rstn
);
- flash : flash_loader
- port map(
- noe_in => '0');
-
- reconfig : altera_reconfig
- port map(
- reconfig_clk => reconfig_clk,
- reconfig_fromgxb => reconfig_fromgxb,
- busy => busy_reconfig,
- reconfig_togxb => reconfig_togxb);
-
pll : altera_pcie_pll
port map(
areset => '0',
- inclk0 => pcie_clk125_i,
- c0 => reconfig_clk,
- c1 => cal_blk_clk,
+ inclk0 => clk125_i,
+ c0 => cal_blk_clk,
locked => locked);
- pcie : altera_pcie
- port map(
- -- Clocking
- refclk => pcie_refclk_i,
- pld_clk => core_clk_out,
- pclk_in => pcie_refclk_i,
- clk250_out => open,
- clk500_out => open,
- core_clk_out => core_clk_out,
-
- -- Transceiver control
- cal_blk_clk => cal_blk_clk, -- All transceivers in FPGA must use the same calibration clock
- reconfig_clk => reconfig_clk,
- fixedclk_serdes => pcie_clk125_i,
- gxb_powerdown => '0',
- pll_powerdown => '0',
- reconfig_togxb => reconfig_togxb,
- reconfig_fromgxb => reconfig_fromgxb,
- busy_altgxb_reconfig => busy_reconfig,
-
- -- PCIe lanes
- rx_in0 => pcie_rx_i(0),
- rx_in1 => pcie_rx_i(1),
- rx_in2 => pcie_rx_i(2),
- rx_in3 => pcie_rx_i(3),
- tx_out0 => pcie_tx_o(0),
- tx_out1 => pcie_tx_o(1),
- tx_out2 => pcie_tx_o(2),
- tx_out3 => pcie_tx_o(3),
-
- -- Avalon RX
- rx_st_mask0 => '0',
- rx_st_ready0 => '0',
- rx_st_bardec0 => open, -- 7 downto 0
- rx_st_be0 => open, -- 7 downto 0
- rx_st_data0 => open, -- 63 downto 0
- rx_st_eop0 => open,
- rx_st_err0 => open,
- rx_st_sop0 => open,
- rx_st_valid0 => open,
- rx_fifo_empty0 => open,
- rx_fifo_full0 => open,
- -- Errors in RX buffer
- derr_cor_ext_rcv0 => open,
- derr_cor_ext_rpl => open,
- derr_rpl => open,
- r2c_err0 => open,
-
- -- Avalon TX
- tx_st_data0 => (others => '0'),
- tx_st_eop0 => '0',
- tx_st_err0 => '0',
- tx_st_sop0 => '0',
- tx_st_valid0 => '0',
- tx_st_ready0 => open,
- tx_fifo_empty0 => open,
- tx_fifo_full0 => open,
- tx_fifo_rdptr0 => open, -- 3 downto 0
- tx_fifo_wrptr0 => open, -- 3 downto 0
- -- Avalon TX credit management
- tx_cred0 => open, -- 35 downto 0
- npd_alloc_1cred_vc0 => open,
- npd_cred_vio_vc0 => open,
- nph_alloc_1cred_vc0 => open,
- nph_cred_vio_vc0 => open,
-
- -- Report completion error status
- cpl_err => (others => '0'), -- 6 downto 0
- cpl_pending => '0',
- lmi_addr => (others => '0'), -- 11 downto 0
- lmi_din => (others => '0'), -- 31 downto 0
- lmi_rden => '0',
- lmi_wren => '0',
- lmi_ack => open,
- lmi_dout => open, -- 31 downto 0
- ko_cpl_spc_vc0 => open, -- 19 downto 0
-
- -- External PHY (PIPE). Not used; using altera PHY.
- pipe_mode => '0',
- rxdata0_ext => (others => '0'), -- 7 downto 0
- rxdata1_ext => (others => '0'), -- 7 downto 0
- rxdata2_ext => (others => '0'), -- 7 downto 0
- rxdata3_ext => (others => '0'), -- 7 downto 0
- rxdatak0_ext => '0',
- rxdatak1_ext => '0',
- rxdatak2_ext => '0',
- rxdatak3_ext => '0',
- rxelecidle0_ext => '0',
- rxelecidle1_ext => '0',
- rxelecidle2_ext => '0',
- rxelecidle3_ext => '0',
- rxstatus0_ext => (others => '0'), -- 2 downto 0
- rxstatus1_ext => (others => '0'), -- 2 downto 0
- rxstatus2_ext => (others => '0'), -- 2 downto 0
- rxstatus3_ext => (others => '0'), -- 2 downto 0
- rxvalid0_ext => '0',
- rxvalid1_ext => '0',
- rxvalid2_ext => '0',
- rxvalid3_ext => '0',
- rxpolarity0_ext => open,
- rxpolarity1_ext => open,
- rxpolarity2_ext => open,
- rxpolarity3_ext => open,
- txcompl0_ext => open,
- txcompl1_ext => open,
- txcompl2_ext => open,
- txcompl3_ext => open,
- txdata0_ext => open,
- txdata1_ext => open, -- 7 downto 0
- txdata2_ext => open, -- 7 downto 0
- txdata3_ext => open, -- 7 downto 0
- txdatak0_ext => open,
- txdatak1_ext => open,
- txdatak2_ext => open,
- txdatak3_ext => open,
- txdetectrx_ext => open,
- txelecidle0_ext => open,
- txelecidle1_ext => open,
- txelecidle2_ext => open,
- txelecidle3_ext => open,
- phystatus_ext => '0',
- powerdown_ext => open, -- 1 downto 0
- rate_ext => open,
-
- -- PCIe interrupts (for endpoint)
- app_int_sts => '0',
- app_msi_num => (others => '0'), -- 4 downto 0
- app_msi_req => '0',
- app_msi_tc => (others => '0'), -- 2 downto 0
- pex_msi_num => (others => '0'), -- 4 downto 0
- app_int_ack => open,
- app_msi_ack => open,
-
- -- PCIe configuration space
- hpg_ctrler => (others => '0'), -- 4 downto 0
- tl_cfg_add => open, -- 3 downto 0
- tl_cfg_ctl => open, -- 31 downto 0
- tl_cfg_ctl_wr => open,
- tl_cfg_sts => open, -- 52 downto 0
- tl_cfg_sts_wr => open,
-
- -- Power management signals
- pm_auxpwr => '0',
- pm_data => (others => '0'), -- 9 downto 0
- pm_event => '0',
- pme_to_cr => pme_shift(pme_shift'length-1),
- pme_to_sr => pme_shift(0),
-
- -- Reset and link training
- npor => npor,
- srst => srst,
- crst => crst,
- l2_exit => l2_exit,
- hotrst_exit => hotrst_exit,
- dlup_exit => dlup_exit,
- suc_spd_neg => open,
- ltssm => ltssm, -- 4 downto 0
- rc_pll_locked => open,
- reset_status => open,
-
- -- Debugging signals
- lane_act => open, -- 3 downto 0
- test_in => test_in, -- 39 downto 0
- test_out => open, -- 8 downto 0
-
- -- WTF? Not documented
- rc_rx_digitalreset => open);
-
+ rstn <= pow_rstn and locked;
- pme_shifter : process(core_clk_out)
- begin
- if rising_edge(core_clk_out) then
- pme_shift(pme_shift'length-1 downto 1) <= pme_shift(pme_shift'length-2 downto 0);
-
- if (l2_exit and hotrst_exit and dlup_exit) = '0' then
- rst_reg <= '1';
- crst <= '1';
- srst <= '1';
- else
- rst_reg <= '0';
- crst <= rst_reg;
- srst <= rst_reg;
- end if;
- end if;
- end process;
- --npor <= pcie_rstn_i and locked;
- npor <= nreset and locked;
+ pcie_phy : pcie_altera port map(
+ clk125_i => clk125_i,
+ cal_clk50_i => cal_blk_clk,
+ rstn_i => rstn,
+ rstn_o => open,
+ pcie_refclk_i => pcie_refclk_i,
+ pcie_rstn_i => pcie_rstn_i,
+ pcie_rx_i => pcie_rx_i,
+ pcie_tx_o => pcie_tx_o,
+ -- rest open for now
+ wb_clk_o => wb_clk,
+ rx_wb_stall_i => stall,
+ tx_wb_stb_i => '0',
+ tx_wb_dat_i => (others => '0')
+ );
- blink : process(pcie_clk125_i)
+ blink : process(wb_clk)
begin
- if rising_edge(pcie_clk125_i) then
+ if rising_edge(wb_clk) then
count <= count + to_unsigned(1, count'length);
if count = 0 then
led_r <= not led_r;
end if;
+
+ stall <= stall_pattern(to_integer(stall_idx));
+ stall_idx <= stall_idx + 1;
end if;
end process;
- led_o(0) <= led_r;
- led_o(1 to 2) <= (others => '1');
-
- led_o(3 to 7) <= not ltssm;
+ led_o(0) <= led_r;
+ led_o(1 to 7) <= (others => '1');
end rtl;
diff --git a/hdl/pcie_wb_pkg.vhd b/hdl/pcie_wb_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5cbc9a1ec096592b7ee55f679b6d237af97d7b9a
--- /dev/null
+++ b/hdl/pcie_wb_pkg.vhd
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package pcie_wb_pkg is
+ component pcie_altera is
+ port(
+ clk125_i : in std_logic; -- 125 MHz, free running
+ cal_clk50_i : in std_logic; -- 50 MHz, shared between all PHYs
+ rstn_i : in std_logic; -- Logical reset
+ rstn_o : out std_logic; -- If PCIe resets
+
+ pcie_refclk_i : in std_logic; -- 100 MHz, must not derive clk125_i or cal_clk50_i
+ pcie_rstn_i : in std_logic; -- PCIe reset pin
+ pcie_rx_i : in std_logic_vector(3 downto 0);
+ pcie_tx_o : out std_logic_vector(3 downto 0);
+
+ cfg_busdev : out std_logic_vector(12 downto 0); -- Configured Bus#:Dev#
+
+ -- Simplified wishbone output stream
+ wb_clk_o : out std_logic;
+
+ rx_wb_stb_o : out std_logic;
+ rx_wb_dat_o : out std_logic_vector(31 downto 0);
+ rx_wb_stall_i : in std_logic;
+
+ tx_wb_stb_i : in std_logic;
+ tx_wb_dat_i : in std_logic_vector(31 downto 0);
+ tx_wb_stall_o : out std_logic);
+ end component;
+end pcie_wb_pkg;