From 5bcd087d993559abe984e0951d84145e9abde8ec Mon Sep 17 00:00:00 2001
From: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
Date: Tue, 4 Oct 2011 14:04:00 +0200
Subject: [PATCH] wishbone: wb_conmax: removed module from the Manifest (no
longer used, kept for legacy designs)
---
modules/wishbone/Manifest.py | 2 +-
modules/wishbone/wb_conmax/Manifest.py | 2 +-
.../wb_conmax/wb_conmax_master_if.vhd | 188 +++++++------
modules/wishbone/wb_conmax/wb_conmax_rf.vhd | 97 ++++---
.../wishbone/wb_conmax/wb_conmax_slave_if.vhd | 263 +++++++++---------
modules/wishbone/wb_conmax/wb_conmax_top.vhd | 7 +-
modules/wishbone/wb_conmax/wbconmax_pkg.vhd | 37 +--
modules/wishbone/wb_conmax/xwb_conmax.vhd | 242 ++++++++++++++++
8 files changed, 532 insertions(+), 306 deletions(-)
create mode 100644 modules/wishbone/wb_conmax/xwb_conmax.vhd
diff --git a/modules/wishbone/Manifest.py b/modules/wishbone/Manifest.py
index e5452b42..68c3aaa5 100644
--- a/modules/wishbone/Manifest.py
+++ b/modules/wishbone/Manifest.py
@@ -5,7 +5,7 @@ modules = { "local" :
"wb_onewire_master",
"wb_i2c_master",
"wb_bus_fanout",
- "wb_conmax",
+# "wb_conmax",
"wb_dpram",
"wb_gpio_port",
"wb_simple_timer",
diff --git a/modules/wishbone/wb_conmax/Manifest.py b/modules/wishbone/wb_conmax/Manifest.py
index b4dc1c43..9a028fe9 100644
--- a/modules/wishbone/wb_conmax/Manifest.py
+++ b/modules/wishbone/wb_conmax/Manifest.py
@@ -1,3 +1,3 @@
files = ["wb_conmax_pri_dec.vhd", "wb_conmax_pri_enc.vhd", "wb_conmax_arb.vhd", "wb_conmax_msel.vhd",
"wbconmax_pkg.vhd", "wb_conmax_slave_if.vhd", "wb_conmax_master_if.vhd", "wb_conmax_rf.vhd",
- "wb_conmax_top.vhd" ];
+ "xwb_conmax.vhd" ];
diff --git a/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd b/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd
index 1862520f..31db7650 100644
--- a/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd
+++ b/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd
@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
--- Last update: 2010-02-16
+-- Last update: 2011-09-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
@@ -36,74 +36,80 @@ use ieee.numeric_std.all;
library work;
use work.wbconmax_pkg.all;
+use work.wishbone_pkg.all;
entity wb_conmax_master_if is
+ generic(
+ g_adr_width : integer;
+ g_sel_width : integer;
+ g_dat_width : integer);
port(
clk_i : in std_logic;
rst_i : in std_logic;
--Master interface
- wb_master_i : in t_wb_i;
- wb_master_o : out t_wb_o;
+ wb_master_i : in t_wishbone_slave_in;
+ wb_master_o : out t_wishbone_slave_out;
--Slaves(0 to 15) interface
- wb_slaves_i : in t_conmax_slaves_i;
- wb_slaves_o : out t_conmax_slaves_o
- );
+ wb_slaves_i : in t_wishbone_master_in_array(0 to 15);
+ wb_slaves_o : out t_wishbone_master_out_array(0 to 15)
+ );
end wb_conmax_master_if;
architecture behaviour of wb_conmax_master_if is
- signal s_slv_sel : std_logic_vector(3 downto 0);
+
+ signal s_slv_sel : std_logic_vector(3 downto 0);
signal s_cyc_o_next : std_logic_vector(15 downto 0);
- signal s_cyc_o : std_logic_vector(15 downto 0);
+ signal s_cyc_o : std_logic_vector(15 downto 0);
begin
--Select logic
- s_slv_sel <= wb_master_i.addr(c_aw-1 downto c_aw-4);
+ s_slv_sel <= wb_master_i.adr(g_adr_width-1 downto g_adr_width-4);
--Address & Data Pass
- GEN_OUTS:
- for I in 0 to 15 generate
- wb_slaves_o(I).addr <= wb_master_i.addr;
- wb_slaves_o(I).sel <= wb_master_i.sel;
- wb_slaves_o(I).data <= wb_master_i.data;
- wb_slaves_o(I).we <= wb_master_i.we;
- wb_slaves_o(I).cyc <= s_cyc_o(I);
- wb_slaves_o(I).stb <= wb_master_i.stb when(s_slv_sel=std_logic_vector(
- to_unsigned(I, 4)) ) else '0';
- end generate;
-
- wb_master_o.data <= wb_slaves_i( 0).data when(s_slv_sel="0000") else
- wb_slaves_i( 1).data when(s_slv_sel="0001") else
- wb_slaves_i( 2).data when(s_slv_sel="0010") else
- wb_slaves_i( 3).data when(s_slv_sel="0011") else
- wb_slaves_i( 4).data when(s_slv_sel="0100") else
- wb_slaves_i( 5).data when(s_slv_sel="0101") else
- wb_slaves_i( 6).data when(s_slv_sel="0110") else
- wb_slaves_i( 7).data when(s_slv_sel="0111") else
- wb_slaves_i( 8).data when(s_slv_sel="1000") else
- wb_slaves_i( 9).data when(s_slv_sel="1001") else
- wb_slaves_i(10).data when(s_slv_sel="1010") else
- wb_slaves_i(11).data when(s_slv_sel="1011") else
- wb_slaves_i(12).data when(s_slv_sel="1100") else
- wb_slaves_i(13).data when(s_slv_sel="1101") else
- wb_slaves_i(14).data when(s_slv_sel="1110") else
- wb_slaves_i(15).data when(s_slv_sel="1111") else
- (others=>'0');
+ GEN_OUTS :
+ for I in 0 to 15 generate
+ wb_slaves_o(I).adr <= wb_master_i.adr;
+ wb_slaves_o(I).sel <= wb_master_i.sel;
+ wb_slaves_o(I).dat <= wb_master_i.dat;
+ wb_slaves_o(I).we <= wb_master_i.we;
+ wb_slaves_o(I).cyc <= s_cyc_o(I);
+ wb_slaves_o(I).stb <= wb_master_i.stb when(s_slv_sel = std_logic_vector(
+ to_unsigned(I, 4)) ) else '0';
+ end generate;
+
+ wb_master_o.dat <= wb_slaves_i(0).dat when(s_slv_sel = "0000") else
+ wb_slaves_i(1).dat when(s_slv_sel = "0001") else
+ wb_slaves_i(2).dat when(s_slv_sel = "0010") else
+ wb_slaves_i(3).dat when(s_slv_sel = "0011") else
+ wb_slaves_i(4).dat when(s_slv_sel = "0100") else
+ wb_slaves_i(5).dat when(s_slv_sel = "0101") else
+ wb_slaves_i(6).dat when(s_slv_sel = "0110") else
+ wb_slaves_i(7).dat when(s_slv_sel = "0111") else
+ wb_slaves_i(8).dat when(s_slv_sel = "1000") else
+ wb_slaves_i(9).dat when(s_slv_sel = "1001") else
+ wb_slaves_i(10).dat when(s_slv_sel = "1010") else
+ wb_slaves_i(11).dat when(s_slv_sel = "1011") else
+ wb_slaves_i(12).dat when(s_slv_sel = "1100") else
+ wb_slaves_i(13).dat when(s_slv_sel = "1101") else
+ wb_slaves_i(14).dat when(s_slv_sel = "1110") else
+ wb_slaves_i(15).dat when(s_slv_sel = "1111") else
+ (others => '0');
--Control Signal Pass
- G1: for I in 0 to 15 generate
- s_cyc_o_next(I) <= s_cyc_o(I) when ( wb_master_i.cyc='1' and wb_master_i.stb='0') else
- wb_master_i.cyc when ( s_slv_sel=std_logic_vector(to_unsigned(I, 4)) ) else
- '0';
+ G1 : for I in 0 to 15 generate
+ s_cyc_o_next(I) <= s_cyc_o(I) when (wb_master_i.cyc = '1' and wb_master_i.stb = '0') else
+ wb_master_i.cyc when (s_slv_sel = std_logic_vector(to_unsigned(I, 4))) else
+ '0';
end generate;
process(clk_i)
begin
- if( clk_i'event and clk_i='1') then
- if(rst_i='1') then
+ if(clk_i'event and clk_i = '1') then
+ if(rst_i = '1') then
s_cyc_o(15 downto 0) <= (others => '0');
else
s_cyc_o(15 downto 0) <= s_cyc_o_next(15 downto 0);
@@ -111,58 +117,58 @@ begin
end if;
end process;
- wb_master_o.ack <= wb_slaves_i( 0).ack when(s_slv_sel="0000") else
- wb_slaves_i( 1).ack when(s_slv_sel="0001") else
- wb_slaves_i( 2).ack when(s_slv_sel="0010") else
- wb_slaves_i( 3).ack when(s_slv_sel="0011") else
- wb_slaves_i( 4).ack when(s_slv_sel="0100") else
- wb_slaves_i( 5).ack when(s_slv_sel="0101") else
- wb_slaves_i( 6).ack when(s_slv_sel="0110") else
- wb_slaves_i( 7).ack when(s_slv_sel="0111") else
- wb_slaves_i( 8).ack when(s_slv_sel="1000") else
- wb_slaves_i( 9).ack when(s_slv_sel="1001") else
- wb_slaves_i(10).ack when(s_slv_sel="1010") else
- wb_slaves_i(11).ack when(s_slv_sel="1011") else
- wb_slaves_i(12).ack when(s_slv_sel="1100") else
- wb_slaves_i(13).ack when(s_slv_sel="1101") else
- wb_slaves_i(14).ack when(s_slv_sel="1110") else
- wb_slaves_i(15).ack when(s_slv_sel="1111") else
+ wb_master_o.ack <= wb_slaves_i(0).ack when(s_slv_sel = "0000") else
+ wb_slaves_i(1).ack when(s_slv_sel = "0001") else
+ wb_slaves_i(2).ack when(s_slv_sel = "0010") else
+ wb_slaves_i(3).ack when(s_slv_sel = "0011") else
+ wb_slaves_i(4).ack when(s_slv_sel = "0100") else
+ wb_slaves_i(5).ack when(s_slv_sel = "0101") else
+ wb_slaves_i(6).ack when(s_slv_sel = "0110") else
+ wb_slaves_i(7).ack when(s_slv_sel = "0111") else
+ wb_slaves_i(8).ack when(s_slv_sel = "1000") else
+ wb_slaves_i(9).ack when(s_slv_sel = "1001") else
+ wb_slaves_i(10).ack when(s_slv_sel = "1010") else
+ wb_slaves_i(11).ack when(s_slv_sel = "1011") else
+ wb_slaves_i(12).ack when(s_slv_sel = "1100") else
+ wb_slaves_i(13).ack when(s_slv_sel = "1101") else
+ wb_slaves_i(14).ack when(s_slv_sel = "1110") else
+ wb_slaves_i(15).ack when(s_slv_sel = "1111") else
'0';
- wb_master_o.err <= wb_slaves_i( 0).err when(s_slv_sel="0000") else
- wb_slaves_i( 1).err when(s_slv_sel="0001") else
- wb_slaves_i( 2).err when(s_slv_sel="0010") else
- wb_slaves_i( 3).err when(s_slv_sel="0011") else
- wb_slaves_i( 4).err when(s_slv_sel="0100") else
- wb_slaves_i( 5).err when(s_slv_sel="0101") else
- wb_slaves_i( 6).err when(s_slv_sel="0110") else
- wb_slaves_i( 7).err when(s_slv_sel="0111") else
- wb_slaves_i( 8).err when(s_slv_sel="1000") else
- wb_slaves_i( 9).err when(s_slv_sel="1001") else
- wb_slaves_i(10).err when(s_slv_sel="1010") else
- wb_slaves_i(11).err when(s_slv_sel="1011") else
- wb_slaves_i(12).err when(s_slv_sel="1100") else
- wb_slaves_i(13).err when(s_slv_sel="1101") else
- wb_slaves_i(14).err when(s_slv_sel="1110") else
- wb_slaves_i(15).err when(s_slv_sel="1111") else
+ wb_master_o.err <= wb_slaves_i(0).err when(s_slv_sel = "0000") else
+ wb_slaves_i(1).err when(s_slv_sel = "0001") else
+ wb_slaves_i(2).err when(s_slv_sel = "0010") else
+ wb_slaves_i(3).err when(s_slv_sel = "0011") else
+ wb_slaves_i(4).err when(s_slv_sel = "0100") else
+ wb_slaves_i(5).err when(s_slv_sel = "0101") else
+ wb_slaves_i(6).err when(s_slv_sel = "0110") else
+ wb_slaves_i(7).err when(s_slv_sel = "0111") else
+ wb_slaves_i(8).err when(s_slv_sel = "1000") else
+ wb_slaves_i(9).err when(s_slv_sel = "1001") else
+ wb_slaves_i(10).err when(s_slv_sel = "1010") else
+ wb_slaves_i(11).err when(s_slv_sel = "1011") else
+ wb_slaves_i(12).err when(s_slv_sel = "1100") else
+ wb_slaves_i(13).err when(s_slv_sel = "1101") else
+ wb_slaves_i(14).err when(s_slv_sel = "1110") else
+ wb_slaves_i(15).err when(s_slv_sel = "1111") else
'0';
- wb_master_o.rty <= wb_slaves_i( 0).rty when(s_slv_sel="0000") else
- wb_slaves_i( 1).rty when(s_slv_sel="0001") else
- wb_slaves_i( 2).rty when(s_slv_sel="0010") else
- wb_slaves_i( 3).rty when(s_slv_sel="0011") else
- wb_slaves_i( 4).rty when(s_slv_sel="0100") else
- wb_slaves_i( 5).rty when(s_slv_sel="0101") else
- wb_slaves_i( 6).rty when(s_slv_sel="0110") else
- wb_slaves_i( 7).rty when(s_slv_sel="0111") else
- wb_slaves_i( 8).rty when(s_slv_sel="1000") else
- wb_slaves_i( 9).rty when(s_slv_sel="1001") else
- wb_slaves_i(10).rty when(s_slv_sel="1010") else
- wb_slaves_i(11).rty when(s_slv_sel="1011") else
- wb_slaves_i(12).rty when(s_slv_sel="1100") else
- wb_slaves_i(13).rty when(s_slv_sel="1101") else
- wb_slaves_i(14).rty when(s_slv_sel="1110") else
- wb_slaves_i(15).rty when(s_slv_sel="1111") else
+ wb_master_o.rty <= wb_slaves_i(0).rty when(s_slv_sel = "0000") else
+ wb_slaves_i(1).rty when(s_slv_sel = "0001") else
+ wb_slaves_i(2).rty when(s_slv_sel = "0010") else
+ wb_slaves_i(3).rty when(s_slv_sel = "0011") else
+ wb_slaves_i(4).rty when(s_slv_sel = "0100") else
+ wb_slaves_i(5).rty when(s_slv_sel = "0101") else
+ wb_slaves_i(6).rty when(s_slv_sel = "0110") else
+ wb_slaves_i(7).rty when(s_slv_sel = "0111") else
+ wb_slaves_i(8).rty when(s_slv_sel = "1000") else
+ wb_slaves_i(9).rty when(s_slv_sel = "1001") else
+ wb_slaves_i(10).rty when(s_slv_sel = "1010") else
+ wb_slaves_i(11).rty when(s_slv_sel = "1011") else
+ wb_slaves_i(12).rty when(s_slv_sel = "1100") else
+ wb_slaves_i(13).rty when(s_slv_sel = "1101") else
+ wb_slaves_i(14).rty when(s_slv_sel = "1110") else
+ wb_slaves_i(15).rty when(s_slv_sel = "1111") else
'0';
end behaviour;
diff --git a/modules/wishbone/wb_conmax/wb_conmax_rf.vhd b/modules/wishbone/wb_conmax/wb_conmax_rf.vhd
index 430b17e0..c26843c6 100644
--- a/modules/wishbone/wb_conmax/wb_conmax_rf.vhd
+++ b/modules/wishbone/wb_conmax/wb_conmax_rf.vhd
@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
--- Last update: 2010-02-16
+-- Last update: 2011-09-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
@@ -37,24 +37,29 @@ use ieee.numeric_std.all;
library work;
use work.wbconmax_pkg.all;
+use work.wishbone_pkg.all;
+
entity wb_conmax_rf is
generic(
- g_rf_addr : integer range 0 to 15 := 15 --0xF
- );
+ g_rf_addr : integer range 0 to 15 := 15; --0xF
+ g_adr_width : integer;
+ g_sel_width : integer;
+ g_dat_width : integer);
+
port(
clk_i : in std_logic;
rst_i : in std_logic;
--Internal WB interface
- int_wb_i : in t_wb_i;
- int_wb_o : out t_wb_o;
+ int_wb_i : in t_wishbone_slave_in;
+ int_wb_o : out t_wishbone_slave_out;
--External WB interface
- ext_wb_i : in t_wb_o;
- ext_wb_o : out t_wb_i;
+ ext_wb_i : in t_wishbone_master_in;
+ ext_wb_o : out t_wishbone_master_out;
--Configuration regs
- conf_o : out t_rf_conf
+ conf_o : out t_conmax_rf_conf
);
end wb_conmax_rf;
@@ -65,14 +70,14 @@ architecture behaviour of wb_conmax_rf is
signal s_rf_ack : std_logic;
signal s_rf_we : std_logic;
- signal s_conf : t_rf_conf;
+ signal s_conf : t_conmax_rf_conf;
signal s_rf_addr : std_logic_vector(3 downto 0);
begin
--Register File select logic
s_rf_addr <= std_logic_vector(to_unsigned(g_rf_addr, 4));
- s_rf_sel <= int_wb_i.cyc and int_wb_i.stb when(int_wb_i.addr(c_aw-5 downto c_aw-8) = s_rf_addr )
+ s_rf_sel <= int_wb_i.cyc and int_wb_i.stb when(int_wb_i.adr(g_adr_width-5 downto g_adr_width-8) = s_rf_addr )
else '0';
@@ -94,22 +99,22 @@ begin
s_conf <= (others=> (others=>'0'));
elsif(s_rf_we='1') then
- if (int_wb_i.addr(5 downto 2)=x"0") then s_conf(0) <= int_wb_i.data(15 downto 0);
- elsif(int_wb_i.addr(5 downto 2)=x"1") then s_conf(1) <= int_wb_i.data(15 downto 0);
- elsif(int_wb_i.addr(5 downto 2)=x"2") then s_conf(2) <= int_wb_i.data(15 downto 0);
- elsif(int_wb_i.addr(5 downto 2)=x"3") then s_conf(3) <= int_wb_i.data(15 downto 0);
- elsif(int_wb_i.addr(5 downto 2)=x"4") then s_conf(4) <= int_wb_i.data(15 downto 0);
- elsif(int_wb_i.addr(5 downto 2)=x"5") then s_conf(5) <= int_wb_i.data(15 downto 0);
- elsif(int_wb_i.addr(5 downto 2)=x"6") then s_conf(6) <= int_wb_i.data(15 downto 0);
- elsif(int_wb_i.addr(5 downto 2)=x"7") then s_conf(7) <= int_wb_i.data(15 downto 0);
- elsif(int_wb_i.addr(5 downto 2)=x"8") then s_conf(8) <= int_wb_i.data(15 downto 0);
- elsif(int_wb_i.addr(5 downto 2)=x"9") then s_conf(9) <= int_wb_i.data(15 downto 0);
- elsif(int_wb_i.addr(5 downto 2)=x"a") then s_conf(10) <= int_wb_i.data(15 downto 0);
- elsif(int_wb_i.addr(5 downto 2)=x"b") then s_conf(11) <= int_wb_i.data(15 downto 0);
- elsif(int_wb_i.addr(5 downto 2)=x"c") then s_conf(12) <= int_wb_i.data(15 downto 0);
- elsif(int_wb_i.addr(5 downto 2)=x"d") then s_conf(13) <= int_wb_i.data(15 downto 0);
- elsif(int_wb_i.addr(5 downto 2)=x"e") then s_conf(14) <= int_wb_i.data(15 downto 0);
- elsif(int_wb_i.addr(5 downto 2)=x"f") then s_conf(15) <= int_wb_i.data(15 downto 0);
+ if (int_wb_i.adr(5 downto 2)=x"0") then s_conf(0) <= int_wb_i.dat(15 downto 0);
+ elsif(int_wb_i.adr(5 downto 2)=x"1") then s_conf(1) <= int_wb_i.dat(15 downto 0);
+ elsif(int_wb_i.adr(5 downto 2)=x"2") then s_conf(2) <= int_wb_i.dat(15 downto 0);
+ elsif(int_wb_i.adr(5 downto 2)=x"3") then s_conf(3) <= int_wb_i.dat(15 downto 0);
+ elsif(int_wb_i.adr(5 downto 2)=x"4") then s_conf(4) <= int_wb_i.dat(15 downto 0);
+ elsif(int_wb_i.adr(5 downto 2)=x"5") then s_conf(5) <= int_wb_i.dat(15 downto 0);
+ elsif(int_wb_i.adr(5 downto 2)=x"6") then s_conf(6) <= int_wb_i.dat(15 downto 0);
+ elsif(int_wb_i.adr(5 downto 2)=x"7") then s_conf(7) <= int_wb_i.dat(15 downto 0);
+ elsif(int_wb_i.adr(5 downto 2)=x"8") then s_conf(8) <= int_wb_i.dat(15 downto 0);
+ elsif(int_wb_i.adr(5 downto 2)=x"9") then s_conf(9) <= int_wb_i.dat(15 downto 0);
+ elsif(int_wb_i.adr(5 downto 2)=x"a") then s_conf(10) <= int_wb_i.dat(15 downto 0);
+ elsif(int_wb_i.adr(5 downto 2)=x"b") then s_conf(11) <= int_wb_i.dat(15 downto 0);
+ elsif(int_wb_i.adr(5 downto 2)=x"c") then s_conf(12) <= int_wb_i.dat(15 downto 0);
+ elsif(int_wb_i.adr(5 downto 2)=x"d") then s_conf(13) <= int_wb_i.dat(15 downto 0);
+ elsif(int_wb_i.adr(5 downto 2)=x"e") then s_conf(14) <= int_wb_i.dat(15 downto 0);
+ elsif(int_wb_i.adr(5 downto 2)=x"f") then s_conf(15) <= int_wb_i.dat(15 downto 0);
end if;
end if;
@@ -125,22 +130,22 @@ begin
s_rf_dout <= x"0000";
else
- if ( int_wb_i.addr(5 downto 2)=x"0" ) then s_rf_dout <= s_conf(0);
- elsif( int_wb_i.addr(5 downto 2)=x"1" ) then s_rf_dout <= s_conf(1);
- elsif( int_wb_i.addr(5 downto 2)=x"2" ) then s_rf_dout <= s_conf(2);
- elsif( int_wb_i.addr(5 downto 2)=x"3" ) then s_rf_dout <= s_conf(3);
- elsif( int_wb_i.addr(5 downto 2)=x"4" ) then s_rf_dout <= s_conf(4);
- elsif( int_wb_i.addr(5 downto 2)=x"5" ) then s_rf_dout <= s_conf(5);
- elsif( int_wb_i.addr(5 downto 2)=x"6" ) then s_rf_dout <= s_conf(6);
- elsif( int_wb_i.addr(5 downto 2)=x"7" ) then s_rf_dout <= s_conf(7);
- elsif( int_wb_i.addr(5 downto 2)=x"8" ) then s_rf_dout <= s_conf(8);
- elsif( int_wb_i.addr(5 downto 2)=x"9" ) then s_rf_dout <= s_conf(9);
- elsif( int_wb_i.addr(5 downto 2)=x"A" ) then s_rf_dout <= s_conf(10);
- elsif( int_wb_i.addr(5 downto 2)=x"B" ) then s_rf_dout <= s_conf(11);
- elsif( int_wb_i.addr(5 downto 2)=x"C" ) then s_rf_dout <= s_conf(12);
- elsif( int_wb_i.addr(5 downto 2)=x"D" ) then s_rf_dout <= s_conf(13);
- elsif( int_wb_i.addr(5 downto 2)=x"E" ) then s_rf_dout <= s_conf(14);
- elsif( int_wb_i.addr(5 downto 2)=x"F" ) then s_rf_dout <= s_conf(15);
+ if ( int_wb_i.adr(5 downto 2)=x"0" ) then s_rf_dout <= s_conf(0);
+ elsif( int_wb_i.adr(5 downto 2)=x"1" ) then s_rf_dout <= s_conf(1);
+ elsif( int_wb_i.adr(5 downto 2)=x"2" ) then s_rf_dout <= s_conf(2);
+ elsif( int_wb_i.adr(5 downto 2)=x"3" ) then s_rf_dout <= s_conf(3);
+ elsif( int_wb_i.adr(5 downto 2)=x"4" ) then s_rf_dout <= s_conf(4);
+ elsif( int_wb_i.adr(5 downto 2)=x"5" ) then s_rf_dout <= s_conf(5);
+ elsif( int_wb_i.adr(5 downto 2)=x"6" ) then s_rf_dout <= s_conf(6);
+ elsif( int_wb_i.adr(5 downto 2)=x"7" ) then s_rf_dout <= s_conf(7);
+ elsif( int_wb_i.adr(5 downto 2)=x"8" ) then s_rf_dout <= s_conf(8);
+ elsif( int_wb_i.adr(5 downto 2)=x"9" ) then s_rf_dout <= s_conf(9);
+ elsif( int_wb_i.adr(5 downto 2)=x"A" ) then s_rf_dout <= s_conf(10);
+ elsif( int_wb_i.adr(5 downto 2)=x"B" ) then s_rf_dout <= s_conf(11);
+ elsif( int_wb_i.adr(5 downto 2)=x"C" ) then s_rf_dout <= s_conf(12);
+ elsif( int_wb_i.adr(5 downto 2)=x"D" ) then s_rf_dout <= s_conf(13);
+ elsif( int_wb_i.adr(5 downto 2)=x"E" ) then s_rf_dout <= s_conf(14);
+ elsif( int_wb_i.adr(5 downto 2)=x"F" ) then s_rf_dout <= s_conf(15);
end if;
end if;
@@ -149,15 +154,15 @@ begin
--Register File bypass logic
- ext_wb_o.addr <= int_wb_i.addr;
+ ext_wb_o.adr <= int_wb_i.adr;
ext_wb_o.sel <= int_wb_i.sel;
- ext_wb_o.data <= int_wb_i.data;
+ ext_wb_o.dat <= int_wb_i.dat;
ext_wb_o.cyc <= int_wb_i.cyc when(s_rf_sel='0') else '0';
ext_wb_o.stb <= int_wb_i.stb;
ext_wb_o.we <= int_wb_i.we;
- int_wb_o.data <= ( (c_dw-1 downto 16 => '0') & s_rf_dout ) when(s_rf_sel='1')
- else ext_wb_i.data;
+ int_wb_o.dat <= ( (g_dat_width-1 downto 16 => '0') & s_rf_dout ) when(s_rf_sel='1')
+ else ext_wb_i.dat;
int_wb_o.ack <= s_rf_ack when(s_rf_sel='1') else ext_wb_i.ack;
int_wb_o.err <= '0' when(s_rf_sel='1') else ext_wb_i.err;
int_wb_o.rty <= '0' when(s_rf_sel='1') else ext_wb_i.rty;
diff --git a/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd b/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd
index 945f85ae..34e07487 100644
--- a/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd
+++ b/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd
@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
--- Last update: 2010-02-16
+-- Last update: 2011-09-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
@@ -34,24 +34,25 @@ use ieee.numeric_std.all;
library work;
use work.wbconmax_pkg.all;
+use work.wishbone_pkg.all;
entity wb_conmax_slave_if is
generic(
g_pri_sel : integer := 2
- );
+ );
port(
- clk_i : in std_logic;
- rst_i : in std_logic;
- conf_i : in std_logic_vector(15 downto 0);
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ conf_i : in std_logic_vector(15 downto 0);
--Slave interface
- wb_slave_i : in t_wb_o;
- wb_slave_o : out t_wb_i;
+ wb_slave_i : in t_wishbone_master_in;
+ wb_slave_o : out t_wishbone_master_out;
--Master (0 to 7) interfaces
- wb_masters_i : in t_conmax_masters_i;
- wb_masters_o : out t_conmax_masters_o
- );
+ wb_masters_i : in t_wishbone_slave_in_array(0 to 7);
+ wb_masters_o : out t_wishbone_slave_out_array(0 to 7)
+ );
end wb_conmax_slave_if;
architecture bahaviour of wb_conmax_slave_if is
@@ -60,45 +61,45 @@ architecture bahaviour of wb_conmax_slave_if is
port(
clk_i : in std_logic;
rst_i : in std_logic;
-
- req_i : in std_logic_vector(7 downto 0);
+
+ req_i : in std_logic_vector(7 downto 0);
gnt_o : out std_logic_vector(2 downto 0);
-
- next_i : in std_logic
- );
+
+ next_i : in std_logic
+ );
end component;
component wb_conmax_msel is
generic(
g_pri_sel : integer := 0
- );
+ );
port(
clk_i : in std_logic;
rst_i : in std_logic;
-
- conf_i : in std_logic_vector(15 downto 0);
- req_i : in std_logic_vector(7 downto 0);
- next_i : in std_logic;
-
- sel : out std_logic_vector(2 downto 0)
- );
+
+ conf_i : in std_logic_vector(15 downto 0);
+ req_i : in std_logic_vector(7 downto 0);
+ next_i : in std_logic;
+
+ sel : out std_logic_vector(2 downto 0)
+ );
end component;
- signal s_wb_cyc_o : std_logic;
+ signal s_wb_cyc_o : std_logic;
signal s_msel_simple, s_msel_pe, s_msel : std_logic_vector(2 downto 0);
- signal s_next : std_logic;
- signal s_mcyc : std_logic_vector(7 downto 0);
- signal s_arb_req_i : std_logic_vector(7 downto 0);
+ signal s_next : std_logic;
+ signal s_mcyc : std_logic_vector(7 downto 0);
+ signal s_arb_req_i : std_logic_vector(7 downto 0);
begin
- wb_slave_o.cyc <= s_wb_cyc_o;
+ wb_slave_o.cyc <= s_wb_cyc_o;
process(clk_i)
begin
- if(clk_i'event and clk_i='1') then
+ if(clk_i'event and clk_i = '1') then
s_next <= not(s_wb_cyc_o);
end if;
end process;
@@ -107,120 +108,120 @@ begin
wb_masters_i(4).cyc & wb_masters_i(3).cyc & wb_masters_i(2).cyc &
wb_masters_i(1).cyc & wb_masters_i(0).cyc;
--Prioritizing Arbiter
- ARB: wb_conmax_arb
+ ARB : wb_conmax_arb
port map(
clk_i => clk_i,
rst_i => rst_i,
-
- req_i => s_arb_req_i,
- gnt_o => s_msel_simple,
- next_i=> '0' --no round robin
- );
-
- MSEL: wb_conmax_msel
+
+ req_i => s_arb_req_i,
+ gnt_o => s_msel_simple,
+ next_i => '0' --no round robin
+ );
+
+ MSEL : wb_conmax_msel
generic map(
g_pri_sel => g_pri_sel
- )
+ )
port map(
clk_i => clk_i,
rst_i => rst_i,
-
+
conf_i => conf_i,
req_i => s_arb_req_i,
next_i => s_next,
sel => s_msel_pe
- );
-
- G1: if(g_pri_sel=0) generate
- s_msel <= s_msel_simple;
- end generate;
- G2: if(g_pri_sel/=0) generate
- s_msel <= s_msel_pe;
- end generate;
-
-
- -------------------------------------
- --Address & Data Pass
- wb_slave_o.addr <= wb_masters_i(0).addr when(s_msel="000") else
- wb_masters_i(1).addr when(s_msel="001") else
- wb_masters_i(2).addr when(s_msel="010") else
- wb_masters_i(3).addr when(s_msel="011") else
- wb_masters_i(4).addr when(s_msel="100") else
- wb_masters_i(5).addr when(s_msel="101") else
- wb_masters_i(6).addr when(s_msel="110") else
- wb_masters_i(7).addr when(s_msel="111") else
- (others=>'0');
-
- wb_slave_o.sel <= wb_masters_i(0).sel when(s_msel="000") else
- wb_masters_i(1).sel when(s_msel="001") else
- wb_masters_i(2).sel when(s_msel="010") else
- wb_masters_i(3).sel when(s_msel="011") else
- wb_masters_i(4).sel when(s_msel="100") else
- wb_masters_i(5).sel when(s_msel="101") else
- wb_masters_i(6).sel when(s_msel="110") else
- wb_masters_i(7).sel when(s_msel="111") else
- (others=>'0');
-
- wb_slave_o.data <= wb_masters_i(0).data when(s_msel="000") else
- wb_masters_i(1).data when(s_msel="001") else
- wb_masters_i(2).data when(s_msel="010") else
- wb_masters_i(3).data when(s_msel="011") else
- wb_masters_i(4).data when(s_msel="100") else
- wb_masters_i(5).data when(s_msel="101") else
- wb_masters_i(6).data when(s_msel="110") else
- wb_masters_i(7).data when(s_msel="111") else
- (others=>'0');
+ );
+
+ G1 : if(g_pri_sel = 0) generate
+ s_msel <= s_msel_simple;
+ end generate;
+ G2 : if(g_pri_sel /= 0) generate
+ s_msel <= s_msel_pe;
+ end generate;
+
+
+ -------------------------------------
+ --Address & Data Pass
+ wb_slave_o.adr <= wb_masters_i(0).adr when(s_msel = "000") else
+ wb_masters_i(1).adr when(s_msel = "001") else
+ wb_masters_i(2).adr when(s_msel = "010") else
+ wb_masters_i(3).adr when(s_msel = "011") else
+ wb_masters_i(4).adr when(s_msel = "100") else
+ wb_masters_i(5).adr when(s_msel = "101") else
+ wb_masters_i(6).adr when(s_msel = "110") else
+ wb_masters_i(7).adr when(s_msel = "111") else
+ (others => '0');
+
+ wb_slave_o.sel <= wb_masters_i(0).sel when(s_msel = "000") else
+ wb_masters_i(1).sel when(s_msel = "001") else
+ wb_masters_i(2).sel when(s_msel = "010") else
+ wb_masters_i(3).sel when(s_msel = "011") else
+ wb_masters_i(4).sel when(s_msel = "100") else
+ wb_masters_i(5).sel when(s_msel = "101") else
+ wb_masters_i(6).sel when(s_msel = "110") else
+ wb_masters_i(7).sel when(s_msel = "111") else
+ (others => '0');
+
+ wb_slave_o.dat <= wb_masters_i(0).dat when(s_msel = "000") else
+ wb_masters_i(1).dat when(s_msel = "001") else
+ wb_masters_i(2).dat when(s_msel = "010") else
+ wb_masters_i(3).dat when(s_msel = "011") else
+ wb_masters_i(4).dat when(s_msel = "100") else
+ wb_masters_i(5).dat when(s_msel = "101") else
+ wb_masters_i(6).dat when(s_msel = "110") else
+ wb_masters_i(7).dat when(s_msel = "111") else
+ (others => '0');
- G_OUT: for I in 0 to 7 generate
- wb_masters_o(I).data <= wb_slave_i.data;
- wb_masters_o(I).ack <= wb_slave_i.ack when(s_msel= std_logic_vector(
- to_unsigned(I, 3)) ) else '0';
- wb_masters_o(I).err <= wb_slave_i.err when(s_msel= std_logic_vector(
- to_unsigned(I, 3)) ) else '0';
- wb_masters_o(I).rty <= wb_slave_i.rty when(s_msel= std_logic_vector(
- to_unsigned(I, 3)) ) else '0';
- end generate;
-
- ------------------------------------
- --Control Signal Pass
- wb_slave_o.we <= wb_masters_i(0).we when(s_msel="000") else
- wb_masters_i(1).we when(s_msel="001") else
- wb_masters_i(2).we when(s_msel="010") else
- wb_masters_i(3).we when(s_msel="011") else
- wb_masters_i(4).we when(s_msel="100") else
- wb_masters_i(5).we when(s_msel="101") else
- wb_masters_i(6).we when(s_msel="110") else
- wb_masters_i(7).we when(s_msel="111") else
- '0';
-
- process(clk_i)
- begin
- if(clk_i'event and clk_i='1') then
- s_mcyc(7 downto 0) <= wb_masters_i(7).cyc & wb_masters_i(6).cyc &
- wb_masters_i(5).cyc & wb_masters_i(4).cyc & wb_masters_i(3).cyc &
- wb_masters_i(2).cyc & wb_masters_i(1).cyc & wb_masters_i(0).cyc;
-
- end if;
- end process;
-
- s_wb_cyc_o <= wb_masters_i(0).cyc and s_mcyc(0) when(s_msel="000") else
- wb_masters_i(1).cyc and s_mcyc(1) when(s_msel="001") else
- wb_masters_i(2).cyc and s_mcyc(2) when(s_msel="010") else
- wb_masters_i(3).cyc and s_mcyc(3) when(s_msel="011") else
- wb_masters_i(4).cyc and s_mcyc(4) when(s_msel="100") else
- wb_masters_i(5).cyc and s_mcyc(5) when(s_msel="101") else
- wb_masters_i(6).cyc and s_mcyc(6) when(s_msel="110") else
- wb_masters_i(7).cyc and s_mcyc(7) when(s_msel="111") else
- '0';
-
- wb_slave_o.stb <= wb_masters_i(0).stb when(s_msel="000") else
- wb_masters_i(1).stb when(s_msel="001") else
- wb_masters_i(2).stb when(s_msel="010") else
- wb_masters_i(3).stb when(s_msel="011") else
- wb_masters_i(4).stb when(s_msel="100") else
- wb_masters_i(5).stb when(s_msel="101") else
- wb_masters_i(6).stb when(s_msel="110") else
- wb_masters_i(7).stb when(s_msel="111") else
- '0';
+ G_OUT : for I in 0 to 7 generate
+ wb_masters_o(I).dat <= wb_slave_i.dat;
+ wb_masters_o(I).ack <= wb_slave_i.ack when(s_msel = std_logic_vector(
+ to_unsigned(I, 3)) ) else '0';
+ wb_masters_o(I).err <= wb_slave_i.err when(s_msel = std_logic_vector(
+ to_unsigned(I, 3)) ) else '0';
+ wb_masters_o(I).rty <= wb_slave_i.rty when(s_msel = std_logic_vector(
+ to_unsigned(I, 3)) ) else '0';
+ end generate;
+
+ ------------------------------------
+ --Control Signal Pass
+ wb_slave_o.we <= wb_masters_i(0).we when(s_msel = "000") else
+ wb_masters_i(1).we when(s_msel = "001") else
+ wb_masters_i(2).we when(s_msel = "010") else
+ wb_masters_i(3).we when(s_msel = "011") else
+ wb_masters_i(4).we when(s_msel = "100") else
+ wb_masters_i(5).we when(s_msel = "101") else
+ wb_masters_i(6).we when(s_msel = "110") else
+ wb_masters_i(7).we when(s_msel = "111") else
+ '0';
+
+ process(clk_i)
+ begin
+ if(clk_i'event and clk_i = '1') then
+ s_mcyc(7 downto 0) <= wb_masters_i(7).cyc & wb_masters_i(6).cyc &
+ wb_masters_i(5).cyc & wb_masters_i(4).cyc & wb_masters_i(3).cyc &
+ wb_masters_i(2).cyc & wb_masters_i(1).cyc & wb_masters_i(0).cyc;
+
+ end if;
+ end process;
+
+ s_wb_cyc_o <= wb_masters_i(0).cyc and s_mcyc(0) when(s_msel = "000") else
+ wb_masters_i(1).cyc and s_mcyc(1) when(s_msel = "001") else
+ wb_masters_i(2).cyc and s_mcyc(2) when(s_msel = "010") else
+ wb_masters_i(3).cyc and s_mcyc(3) when(s_msel = "011") else
+ wb_masters_i(4).cyc and s_mcyc(4) when(s_msel = "100") else
+ wb_masters_i(5).cyc and s_mcyc(5) when(s_msel = "101") else
+ wb_masters_i(6).cyc and s_mcyc(6) when(s_msel = "110") else
+ wb_masters_i(7).cyc and s_mcyc(7) when(s_msel = "111") else
+ '0';
+
+ wb_slave_o.stb <= wb_masters_i(0).stb when(s_msel = "000") else
+ wb_masters_i(1).stb when(s_msel = "001") else
+ wb_masters_i(2).stb when(s_msel = "010") else
+ wb_masters_i(3).stb when(s_msel = "011") else
+ wb_masters_i(4).stb when(s_msel = "100") else
+ wb_masters_i(5).stb when(s_msel = "101") else
+ wb_masters_i(6).stb when(s_msel = "110") else
+ wb_masters_i(7).stb when(s_msel = "111") else
+ '0';
end bahaviour;
diff --git a/modules/wishbone/wb_conmax/wb_conmax_top.vhd b/modules/wishbone/wb_conmax/wb_conmax_top.vhd
index 377485eb..78c21e5d 100644
--- a/modules/wishbone/wb_conmax/wb_conmax_top.vhd
+++ b/modules/wishbone/wb_conmax/wb_conmax_top.vhd
@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-12
--- Last update: 2010-02-16
+-- Last update: 2011-09-14
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
@@ -106,8 +106,9 @@ architecture struct of wb_conmax_top is
end component;
- signal intwb_s15_i : t_wb_o;
- signal intwb_s15_o : t_wb_i;
+ signal intwb_s15_i : t_wishbone_master_in;
+ signal intwb_s15_o : t_wishbone_master_out;
+
--M0Sx
signal m0_slaves_i : t_conmax_slaves_i;
diff --git a/modules/wishbone/wb_conmax/wbconmax_pkg.vhd b/modules/wishbone/wb_conmax/wbconmax_pkg.vhd
index a3497ce2..c1d90b3c 100644
--- a/modules/wishbone/wb_conmax/wbconmax_pkg.vhd
+++ b/modules/wishbone/wb_conmax/wbconmax_pkg.vhd
@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk
-- Company : Elproma
-- Created : 2011-02-16
--- Last update: 2010-02-16
+-- Last update: 2011-09-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
@@ -26,38 +26,9 @@ use ieee.std_logic_1164.all;
package wbconmax_pkg is
- type t_rf_conf is array(0 to 15) of std_logic_vector(15 downto 0);
+ type t_conmax_rf_conf is array(0 to 15) of std_logic_vector(15 downto 0);
+ type t_conmax_pri_sel is array(0 to 15) of integer range 0 to 3;
- constant c_dw : integer := 32; --data width
- constant c_aw : integer := 18; --address width = max 14b (for dpram) + 4b
- --for wb_intercom (Mst selects Slave)
- constant c_sw : integer := 4; -- c_dw/8
-
- --g_pri_selx := 0 (1 priority level), 1 (2 pri levels) or 2 (4 pri levels).
- type t_pri_sels is array(0 to 15) of integer range 0 to 3;
- constant g_pri_sel : t_pri_sels := (2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
-
- --as in original WB conmax spec and implementation, those are
- --inputs fed by WB Master from outside
- type t_wb_i is record
- data : std_logic_vector(c_dw-1 downto 0);
- addr : std_logic_vector(c_aw-1 downto 0);
- sel : std_logic_vector(c_sw-1 downto 0);
- we : std_logic;
- cyc : std_logic;
- stb : std_logic;
- end record;
-
- type t_wb_o is record
- data : std_logic_vector(c_dw-1 downto 0);
- ack : std_logic;
- err : std_logic;
- rty : std_logic;
- end record;
-
- type t_conmax_masters_i is array(0 to 7) of t_wb_i;
- type t_conmax_masters_o is array(0 to 7) of t_wb_o;
- type t_conmax_slaves_i is array(0 to 15) of t_wb_o;
- type t_conmax_slaves_o is array(0 to 15) of t_wb_i;
+ constant c_conmax_default_pri_sel : t_conmax_pri_sel := (2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
end wbconmax_pkg;
diff --git a/modules/wishbone/wb_conmax/xwb_conmax.vhd b/modules/wishbone/wb_conmax/xwb_conmax.vhd
new file mode 100644
index 00000000..fec1e80b
--- /dev/null
+++ b/modules/wishbone/wb_conmax/xwb_conmax.vhd
@@ -0,0 +1,242 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wishbone_pkg.all;
+use work.wbconmax_pkg.all;
+
+entity xwb_conmax is
+
+ generic (
+ g_rf_addr : integer := 15;
+ g_num_slaves : integer;
+ g_num_masters : integer;
+ g_adr_width : integer;
+ g_sel_width : integer;
+ g_dat_width : integer;
+ g_priority_sel : t_conmax_pri_sel := c_conmax_default_pri_sel);
+
+ port(
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ slave_i : in t_wishbone_slave_in_array(0 to g_num_slaves-1);
+ slave_o : out t_wishbone_slave_out_array(0 to g_num_slaves-1);
+
+ master_i : in t_wishbone_master_in_array(0 to g_num_masters-1);
+ master_o : out t_wishbone_master_out_array(0 to g_num_masters-1)
+ );
+end xwb_conmax;
+
+architecture rtl of xwb_conmax is
+
+ component wb_conmax_master_if
+ generic (
+ g_adr_width : integer;
+ g_sel_width : integer;
+ g_dat_width : integer);
+ port (
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ wb_master_i : in t_wishbone_slave_in;
+ wb_master_o : out t_wishbone_slave_out;
+ wb_slaves_i : in t_wishbone_master_in_array(0 to 15);
+ wb_slaves_o : out t_wishbone_master_out_array(0 to 15));
+ end component;
+
+ component wb_conmax_slave_if
+ generic (
+ g_pri_sel : integer);
+ port (
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ conf_i : in std_logic_vector(15 downto 0);
+ wb_slave_i : in t_wishbone_master_in;
+ wb_slave_o : out t_wishbone_master_out;
+ wb_masters_i : in t_wishbone_slave_in_array(0 to 7);
+ wb_masters_o : out t_wishbone_slave_out_array(0 to 7));
+ end component;
+
+
+ component wb_conmax_rf
+ generic (
+ g_rf_addr : integer range 0 to 15;
+ g_adr_width : integer;
+ g_sel_width : integer;
+ g_dat_width : integer);
+ port (
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ int_wb_i : in t_wishbone_slave_in;
+ int_wb_o : out t_wishbone_slave_out;
+ ext_wb_i : in t_wishbone_master_in;
+ ext_wb_o : out t_wishbone_master_out;
+ conf_o : out t_conmax_rf_conf);
+ end component;
+
+ signal intwb_s15_i : t_wishbone_master_in;
+ signal intwb_s15_o : t_wishbone_master_out;
+
+ type t_conmax_slave_mux_in_array is array(integer range <>) of t_wishbone_master_in_array(0 to 15);
+
+ type t_conmax_slave_mux_out_array is array(integer range <>) of t_wishbone_master_out_array(0 to 15);
+
+ --M0Sx
+ signal m_slaves_in : t_conmax_slave_mux_in_array(0 to 7);
+ signal m_slaves_out : t_conmax_slave_mux_out_array(0 to 7);
+
+
+ signal s_conf : t_conmax_rf_conf;
+
+ signal s15_wb_masters_i : t_wishbone_slave_in_array(0 to 7);
+ signal s15_wb_masters_o : t_wishbone_slave_out_array(0 to 7);
+
+ signal rst : std_logic;
+
+ signal slave_i_int : t_wishbone_slave_in_array(0 to 7);
+ signal slave_o_int : t_wishbone_slave_out_array(0 to 7);
+ signal master_i_int : t_wishbone_master_in_array(0 to 15);
+ signal master_o_int : t_wishbone_master_out_array(0 to 15);
+
+begin -- rtl
+
+ rst <= not rst_n_i;
+
+
+ gen_real_masters : for i in 0 to g_num_slaves-1 generate
+ slave_i_int(i) <= slave_i(i);
+ slave_o(i) <= slave_o_int(i);
+ end generate gen_real_masters;
+
+ gen_dummy_masters : for i in g_num_slaves to 7 generate
+ slave_i_int(i).cyc <= '0';
+ slave_i_int(i).stb <= '0';
+ slave_i_int(i).we <= '0';
+ slave_i_int(i).adr <= (others => '0');
+ slave_i_int(i).dat <= (others => '0');
+ end generate gen_dummy_masters;
+
+ gen_master_ifs : for i in 0 to 7 generate
+ U_Master_IF : wb_conmax_master_if
+ generic map (
+ g_adr_width => g_adr_width,
+ g_sel_width => g_sel_width,
+ g_dat_width => g_dat_width)
+ port map(
+ clk_i => clk_sys_i,
+ rst_i => rst,
+
+ --Master interface
+ wb_master_i => slave_i_int(i),
+ wb_master_o => slave_o_int(i),
+ --Slaves(0 to 15) interface
+ wb_slaves_i => m_slaves_in(i),
+ wb_slaves_o => m_slaves_out(i)
+ );
+ end generate gen_master_ifs;
+
+ gen_slave_ifs : for i in 0 to 14 generate
+ U_Slave_IF : wb_conmax_slave_if
+ generic map(
+ g_pri_sel => g_priority_sel(i)
+ )
+ port map(
+ clk_i => clk_sys_i,
+ rst_i => rst,
+ conf_i => s_conf(i),
+
+ --Slave interface
+ wb_slave_i => master_i_int(I),
+ wb_slave_o => master_o_int(I),
+
+ --Interfaces to masters
+ wb_masters_i(0) => m_slaves_out(0)(I),
+ wb_masters_i(1) => m_slaves_out(1)(I),
+ wb_masters_i(2) => m_slaves_out(2)(I),
+ wb_masters_i(3) => m_slaves_out(3)(I),
+ wb_masters_i(4) => m_slaves_out(4)(I),
+ wb_masters_i(5) => m_slaves_out(5)(I),
+ wb_masters_i(6) => m_slaves_out(6)(I),
+ wb_masters_i(7) => m_slaves_out(7)(I),
+
+ wb_masters_o(0) => m_slaves_in(0)(i),
+ wb_masters_o(1) => m_slaves_in(1)(I),
+ wb_masters_o(2) => m_slaves_in(2)(I),
+ wb_masters_o(3) => m_slaves_in(3)(I),
+ wb_masters_o(4) => m_slaves_in(4)(I),
+ wb_masters_o(5) => m_slaves_in(5)(I),
+ wb_masters_o(6) => m_slaves_in(6)(I),
+ wb_masters_o(7) => m_slaves_in(7)(I)
+ );
+
+ end generate gen_slave_ifs;
+
+ s15_wb_masters_i(0) <= m_slaves_out(0)(15);
+ s15_wb_masters_i(1) <= m_slaves_out(1)(15);
+ s15_wb_masters_i(2) <= m_slaves_out(2)(15);
+ s15_wb_masters_i(3) <= m_slaves_out(3)(15);
+ s15_wb_masters_i(4) <= m_slaves_out(4)(15);
+ s15_wb_masters_i(5) <= m_slaves_out(5)(15);
+ s15_wb_masters_i(6) <= m_slaves_out(6)(15);
+ s15_wb_masters_i(7) <= m_slaves_out(7)(15);
+
+ m_slaves_in(0)(15) <= s15_wb_masters_o(0);
+ m_slaves_in(1)(15) <= s15_wb_masters_o(1);
+ m_slaves_in(2)(15) <= s15_wb_masters_o(2);
+ m_slaves_in(3)(15) <= s15_wb_masters_o(3);
+ m_slaves_in(4)(15) <= s15_wb_masters_o(4);
+ m_slaves_in(5)(15) <= s15_wb_masters_o(5);
+ m_slaves_in(6)(15) <= s15_wb_masters_o(6);
+ m_slaves_in(7)(15) <= s15_wb_masters_o(7);
+
+ U_Slave15 : wb_conmax_slave_if
+ generic map(
+ g_pri_sel => g_priority_sel(15)
+ )
+ port map(
+ clk_i => clk_sys_i,
+ rst_i => rst,
+ conf_i => s_conf(15),
+
+ --Slave interface
+ wb_slave_i => intwb_s15_i,
+ wb_slave_o => intwb_s15_o,
+
+ --Interfaces to masters
+ wb_masters_i => s15_wb_masters_i,
+ wb_masters_o => s15_wb_masters_o
+ );
+
+ U_Reg_File : wb_conmax_rf
+ generic map(
+ g_rf_addr => g_rf_addr,
+ g_adr_width => g_adr_width,
+ g_sel_width => g_sel_width,
+ g_dat_width => g_dat_width
+ )
+ port map(
+ clk_i => clk_sys_i,
+ rst_i => rst,
+
+ int_wb_i => intwb_s15_o,
+ int_wb_o => intwb_s15_i,
+ ext_wb_i => master_i_int(15),
+ ext_wb_o => master_o_int(15),
+
+ conf_o => s_conf
+ );
+
+
+ gen_slaves_ports : for i in 0 to g_num_masters-1 generate
+ master_o(i) <= master_o_int(i);
+ master_i_int(i) <= master_i(i);
+ end generate gen_slaves_ports;
+
+ gen_unused_slave_ports : for i in g_num_masters to 15 generate
+ master_i_int(i).ack <= '0';
+ master_i_int(i).err <= '0';
+ master_i_int(i).rty <= '0';
+ end generate gen_unused_slave_ports;
+
+
+end rtl;
+
--
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