From 5369d2d2232627a6327aae81551bda2ac265d205 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <w.terpstra@gsi.de>
Date: Wed, 2 Nov 2011 17:52:55 +0100
Subject: [PATCH] lm32_testsys: Detect when there is a bus error.
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
---
testbench/wishbone/lm32_testsys/lm32_test_system.vhd | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/testbench/wishbone/lm32_testsys/lm32_test_system.vhd b/testbench/wishbone/lm32_testsys/lm32_test_system.vhd
index 37e510e4..fef8b8fa 100644
--- a/testbench/wishbone/lm32_testsys/lm32_test_system.vhd
+++ b/testbench/wishbone/lm32_testsys/lm32_test_system.vhd
@@ -35,13 +35,13 @@ architecture rtl of lm32_test_system is
constant c_cfg_base_addr : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
- (0 => x"00000000", -- CPU I-mem
- 1 => x"10000000", -- CPU D-mem
+ (0 => x"00000000", -- 64KB of fpga memory
+ 1 => x"10000000", -- The second port to the same memory
2 => x"20000000"); -- Peripherals
constant c_cfg_base_mask : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
- (0 => x"f0000000",
- 1 => x"f0000000",
+ (0 => x"ffff0000",
+ 1 => x"ffff0000",
2 => x"f0000000");
signal owr_en_slv, owr_in_slv : std_logic_vector(0 downto 0);
--
GitLab