From 4b40d26422016a438b4a5afa68bc0457c0bc5531 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <w.terpstra@gsi.de>
Date: Mon, 12 Mar 2012 17:57:45 +0100
Subject: [PATCH] Switch all of my imported code to use Tom-style _i, _o, etc.
---
modules/common/gc_dual_clock_ram.vhd | 32 +++++-----
modules/common/gc_wfifo.vhd | 58 +++++++++----------
modules/common/gencores_pkg.vhd | 40 ++++++-------
.../wb_clock_crossing/xwb_clock_crossing.vhd | 38 ++++++------
modules/wishbone/wb_dma/xwb_dma.vhd | 28 ++++-----
modules/wishbone/wishbone_pkg.vhd | 32 +++++-----
6 files changed, 114 insertions(+), 114 deletions(-)
diff --git a/modules/common/gc_dual_clock_ram.vhd b/modules/common/gc_dual_clock_ram.vhd
index 6e27c223..1f6e28a8 100644
--- a/modules/common/gc_dual_clock_ram.vhd
+++ b/modules/common/gc_dual_clock_ram.vhd
@@ -9,15 +9,15 @@ entity gc_dual_clock_ram is
data_width : natural := 32);
port(
-- write port
- w_clk : in std_logic;
- w_en : in std_logic;
- w_addr : in std_logic_vector(addr_width-1 downto 0);
- w_data : in std_logic_vector(data_width-1 downto 0);
+ w_clk_i : in std_logic;
+ w_en_i : in std_logic;
+ w_addr_i : in std_logic_vector(addr_width-1 downto 0);
+ w_data_i : in std_logic_vector(data_width-1 downto 0);
-- read port
- r_clk : in std_logic;
- r_en : in std_logic;
- r_addr : in std_logic_vector(addr_width-1 downto 0);
- r_data : out std_logic_vector(data_width-1 downto 0));
+ r_clk_i : in std_logic;
+ r_en_i : in std_logic;
+ r_addr_i : in std_logic_vector(addr_width-1 downto 0);
+ r_data_o : out std_logic_vector(data_width-1 downto 0));
end gc_dual_clock_ram;
architecture rtl of gc_dual_clock_ram is
@@ -28,20 +28,20 @@ architecture rtl of gc_dual_clock_ram is
attribute ramstyle : string;
attribute ramstyle of ram : signal is "no_rw_check";
begin
- write : process(w_clk)
+ write : process(w_clk_i)
begin
- if rising_edge(w_clk) then
- if w_en = '1' then
- ram(to_integer(unsigned(w_addr))) <= w_data;
+ if rising_edge(w_clk_i) then
+ if w_en_i = '1' then
+ ram(to_integer(unsigned(w_addr_i))) <= w_data_i;
end if;
end if;
end process;
- read : process(r_clk)
+ read : process(r_clk_i)
begin
- if rising_edge(r_clk) then
- if r_en = '1' then
- r_data <= ram(to_integer(unsigned(r_addr)));
+ if rising_edge(r_clk_i) then
+ if r_en_i = '1' then
+ r_data_o <= ram(to_integer(unsigned(r_addr_i)));
end if;
end if;
end process;
diff --git a/modules/common/gc_wfifo.vhd b/modules/common/gc_wfifo.vhd
index 24982281..c457bef6 100644
--- a/modules/common/gc_wfifo.vhd
+++ b/modules/common/gc_wfifo.vhd
@@ -10,22 +10,22 @@ entity gc_wfifo is
addr_width : natural := 4;
data_width : natural := 32);
port(
- rst : in std_logic;
+ rst_n_i : in std_logic;
-- write port, only set w_en when w_rdy
- w_clk : in std_logic;
- w_rdy : out std_logic;
- w_en : in std_logic;
- w_data : in std_logic_vector(data_width-1 downto 0);
+ w_clk_i : in std_logic;
+ w_rdy_o : out std_logic;
+ w_en_i : in std_logic;
+ w_data_i : in std_logic_vector(data_width-1 downto 0);
-- (pre)alloc port, can be unused
- a_clk : in std_logic;
- a_rdy : out std_logic;
- a_en : in std_logic;
+ a_clk_i : in std_logic;
+ a_rdy_o : out std_logic;
+ a_en_i : in std_logic;
-- read port, only set r_en when r_rdy
-- data is valid the cycle after r_en raised
- r_clk : in std_logic;
- r_rdy : out std_logic;
- r_en : in std_logic;
- r_data : out std_logic_vector(data_width-1 downto 0));
+ r_clk_i : in std_logic;
+ r_rdy_o : out std_logic;
+ r_en_i : in std_logic;
+ r_data_o : out std_logic_vector(data_width-1 downto 0));
end gc_wfifo;
architecture rtl of gc_wfifo is
@@ -88,16 +88,16 @@ architecture rtl of gc_wfifo is
begin
ram : gc_dual_clock_ram
generic map(addr_width => addr_width, data_width => data_width)
- port map(w_clk => w_clk, w_en => w_en, w_addr => index(w_idx_bnry), w_data => w_data,
- r_clk => r_clk, r_en => r_en, r_addr => index(r_idx_bnry), r_data => r_data);
+ port map(w_clk_i => w_clk_i, w_en_i => w_en_i, w_addr_i => index(w_idx_bnry), w_data_i => w_data_i,
+ r_clk_i => r_clk_i, r_en_i => r_en_i, r_addr_i => index(r_idx_bnry), r_data_o => r_data_o);
- read : process(r_clk)
+ read : process(r_clk_i)
variable idx : counter;
begin
- if rising_edge(r_clk) then
- if rst = '1' then
+ if rising_edge(r_clk_i) then
+ if rst_n_i = '0' then
idx := (others => '0');
- elsif r_en = '1' then
+ elsif r_en_i = '1' then
idx := r_idx_bnry + 1;
else
idx := r_idx_bnry;
@@ -108,15 +108,15 @@ begin
end if;
end process;
w_idx_shift_r(0) <= w_idx_gray;
- r_rdy <= not empty(r_idx_gray, w_idx_shift_r(sync_depth));
+ r_rdy_o <= not empty(r_idx_gray, w_idx_shift_r(sync_depth));
- write : process(w_clk)
+ write : process(w_clk_i)
variable idx : counter;
begin
- if rising_edge(w_clk) then
- if rst = '1' then
+ if rising_edge(w_clk_i) then
+ if rst_n_i = '0' then
idx := (others => '0');
- elsif w_en = '1' then
+ elsif w_en_i = '1' then
idx := w_idx_bnry + 1;
else
idx := w_idx_bnry;
@@ -127,15 +127,15 @@ begin
end if;
end process;
r_idx_shift_w(0) <= r_idx_gray;
- w_rdy <= not full(w_idx_gray, r_idx_shift_w(sync_depth));
+ w_rdy_o <= not full(w_idx_gray, r_idx_shift_w(sync_depth));
- alloc : process(a_clk)
+ alloc : process(a_clk_i)
variable idx : counter;
begin
- if rising_edge(a_clk) then
- if rst = '1' then
+ if rising_edge(a_clk_i) then
+ if rst_n_i = '0' then
idx := (others => '0');
- elsif a_en = '1' then
+ elsif a_en_i = '1' then
idx := a_idx_bnry + 1;
else
idx := a_idx_bnry;
@@ -146,5 +146,5 @@ begin
end if;
end process;
r_idx_shift_a(0) <= r_idx_gray;
- a_rdy <= not full(a_idx_gray, r_idx_shift_a(sync_depth));
+ a_rdy_o <= not full(a_idx_gray, r_idx_shift_a(sync_depth));
end rtl;
diff --git a/modules/common/gencores_pkg.vhd b/modules/common/gencores_pkg.vhd
index ca86e993..29c718a9 100644
--- a/modules/common/gencores_pkg.vhd
+++ b/modules/common/gencores_pkg.vhd
@@ -178,15 +178,15 @@ package gencores_pkg is
data_width : natural := 32);
port(
-- write port
- w_clk : in std_logic;
- w_en : in std_logic;
- w_addr : in std_logic_vector(addr_width-1 downto 0);
- w_data : in std_logic_vector(data_width-1 downto 0);
+ w_clk_i : in std_logic;
+ w_en_i : in std_logic;
+ w_addr_i : in std_logic_vector(addr_width-1 downto 0);
+ w_data_i : in std_logic_vector(data_width-1 downto 0);
-- read port
- r_clk : in std_logic;
- r_en : in std_logic;
- r_addr : in std_logic_vector(addr_width-1 downto 0);
- r_data : out std_logic_vector(data_width-1 downto 0));
+ r_clk_i : in std_logic;
+ r_en_i : in std_logic;
+ r_addr_i : in std_logic_vector(addr_width-1 downto 0);
+ r_data_o : out std_logic_vector(data_width-1 downto 0));
end component;
-- A 'Wes' FIFO. Generic FIFO using inferred memory.
@@ -200,22 +200,22 @@ package gencores_pkg is
addr_width : natural := 4;
data_width : natural := 32);
port(
- rst : in std_logic;
+ rst_n_i : in std_logic;
-- write port, only set w_en when w_rdy
- w_clk : in std_logic;
- w_rdy : out std_logic;
- w_en : in std_logic;
- w_data : in std_logic_vector(data_width-1 downto 0);
+ w_clk_i : in std_logic;
+ w_rdy_o : out std_logic;
+ w_en_i : in std_logic;
+ w_data_i : in std_logic_vector(data_width-1 downto 0);
-- (pre)alloc port, can be unused
- a_clk : in std_logic;
- a_rdy : out std_logic;
- a_en : in std_logic;
+ a_clk_i : in std_logic;
+ a_rdy_o : out std_logic;
+ a_en_i : in std_logic;
-- read port, only set r_en when r_rdy
-- data is valid the cycle after r_en raised
- r_clk : in std_logic;
- r_rdy : out std_logic;
- r_en : in std_logic;
- r_data : out std_logic_vector(data_width-1 downto 0));
+ r_clk_i : in std_logic;
+ r_rdy_o : out std_logic;
+ r_en_i : in std_logic;
+ r_data_o : out std_logic_vector(data_width-1 downto 0));
end component;
procedure f_rr_arbitrate (
diff --git a/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd b/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
index 9de45e1f..575c6d36 100644
--- a/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
+++ b/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
@@ -10,15 +10,15 @@ entity xwb_clock_crossing is
log2fifo : natural := 4);
port(
-- Common wishbone signals
- rst : in std_logic;
+ rst_n_i : in std_logic;
-- Slave control port
- slave_clk : in std_logic;
- slave_i : in t_wishbone_slave_in;
- slave_o : out t_wishbone_slave_out;
+ slave_clk_i : in std_logic;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
-- Master reader port
- master_clk : in std_logic;
- master_i : in t_wishbone_master_in;
- master_o : out t_wishbone_master_out);
+ master_clk_i : in std_logic;
+ master_i : in t_wishbone_master_in;
+ master_o : out t_wishbone_master_out);
end xwb_clock_crossing;
architecture rtl of xwb_clock_crossing is
@@ -55,9 +55,9 @@ architecture rtl of xwb_clock_crossing is
begin
mfifo : gc_wfifo
generic map(addr_width => log2fifo, data_width => mlen, sync_depth => sync_depth, gray_code => true)
- port map(w_clk => slave_clk, w_rdy => mw_rdy, w_en => mw_en, w_data => msend_vect,
- r_clk => master_clk, r_rdy => mr_rdy, r_en => mr_en, r_data => mrecv_vect,
- a_clk => '0', a_rdy => open, a_en => '0', rst => rst);
+ port map(w_clk_i => slave_clk_i, w_rdy_o => mw_rdy, w_en_i => mw_en, w_data_i => msend_vect,
+ r_clk_i => master_clk_i, r_rdy_o => mr_rdy, r_en_i => mr_en, r_data_o => mrecv_vect,
+ a_clk_i => '0', a_rdy_o => open, a_en_i => '0', rst_n_i => rst_n_i);
msend_vect(mWE_start) <= msend.WE;
msend_vect(mADR_end downto mADR_start) <= msend.ADR;
@@ -71,9 +71,9 @@ begin
sfifo : gc_wfifo
generic map(addr_width => log2fifo, data_width => slen, sync_depth => sync_depth, gray_code => true)
- port map(w_clk => master_clk, w_rdy => open, w_en => sw_en, w_data => ssend_vect,
- r_clk => slave_clk, r_rdy => sr_rdy, r_en => sr_en, r_data => srecv_vect,
- a_clk => slave_clk, a_rdy => sa_rdy, a_en => sa_en, rst => rst);
+ port map(w_clk_i => master_clk_i, w_rdy_o => open, w_en_i => sw_en, w_data_i => ssend_vect,
+ r_clk_i => slave_clk_i, r_rdy_o => sr_rdy, r_en_i => sr_en, r_data_o => srecv_vect,
+ a_clk_i => slave_clk_i, a_rdy_o => sa_rdy, a_en_i => sa_en, rst_n_i => rst_n_i);
ssend_vect(sACK_start) <= ssend.ACK;
ssend_vect(sRTY_start) <= ssend.RTY;
@@ -103,10 +103,10 @@ begin
master_o.SEL <= mrecv.SEL;
master_o.DAT <= mrecv.DAT;
- drive_master_port : process(master_clk)
+ drive_master_port : process(master_clk_i)
begin
- if rising_edge(master_clk) then
- if rst = '1' then
+ if rising_edge(master_clk_i) then
+ if rst_n_i = '0' then
master_o_STB <= '0';
else
master_o_STB <= mr_en or (master_o_STB and master_i.STALL);
@@ -128,10 +128,10 @@ begin
slave_o.RTY <= srecv.RTY and slave_o_PUSH;
slave_o.ERR <= srecv.ERR and slave_o_PUSH;
- drive_slave_port : process(slave_clk)
+ drive_slave_port : process(slave_clk_i)
begin
- if rising_edge(slave_clk) then
- if rst = '1' then
+ if rising_edge(slave_clk_i) then
+ if rst_n_i = '0' then
slave_o_PUSH <= '0';
else
slave_o_PUSH <= sr_en;
diff --git a/modules/wishbone/wb_dma/xwb_dma.vhd b/modules/wishbone/wb_dma/xwb_dma.vhd
index bfaa5232..2430d7e1 100644
--- a/modules/wishbone/wb_dma/xwb_dma.vhd
+++ b/modules/wishbone/wb_dma/xwb_dma.vhd
@@ -39,19 +39,19 @@ entity xwb_dma is
);
port(
-- Common wishbone signals
- clk : in std_logic;
- rst : in std_logic;
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
-- Slave control port
- slave_i : in t_wishbone_slave_in;
- slave_o : out t_wishbone_slave_out;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
-- Master reader port
- r_master_i : in t_wishbone_master_in;
- r_master_o : out t_wishbone_master_out;
+ r_master_i : in t_wishbone_master_in;
+ r_master_o : out t_wishbone_master_out;
-- Master writer port
- w_master_i : in t_wishbone_master_in;
- w_master_o : out t_wishbone_master_out;
+ w_master_i : in t_wishbone_master_in;
+ w_master_o : out t_wishbone_master_out;
-- Pulsed high completion signal
- interrupt : out std_logic
+ interrupt_o : out std_logic
);
end xwb_dma;
@@ -137,7 +137,7 @@ begin
r_master_o.DAT <= (others => '0');
w_master_o.DAT <= ring(index(write_issue_offset));
- main : process(clk)
+ main : process(clk_i)
variable read_issue_progress : boolean;
variable read_result_progress : boolean;
variable write_issue_progress : boolean;
@@ -155,8 +155,8 @@ begin
variable ring_empty : boolean;
variable done_transfer : boolean;
begin
- if (rising_edge(clk)) then
- if (rst = '1') then
+ if (rising_edge(clk_i)) then
+ if (rst_n_i = '0') then
read_issue_offset <= (others => '0');
read_result_offset <= (others => '0');
write_issue_offset <= (others => '0');
@@ -174,7 +174,7 @@ begin
w_master_o_STB <= '0';
slave_o_ACK <= '0';
slave_o_DAT <= (others => '0');
- interrupt <= '0';
+ interrupt_o <= '0';
else
-- Output any read the user requests
case to_integer(unsigned(slave_i.ADR(4 downto 2))) is
@@ -236,7 +236,7 @@ begin
(new_read_result_offset /= new_read_issue_offset));
w_master_o_STB <= active_high (new_write_issue_offset /= new_read_result_offset);
w_master_o_CYC <= active_high (new_write_result_offset /= new_read_result_offset);
- interrupt <= active_high (write_result_progress and done_transfer and ring_empty);
+ interrupt_o <= active_high (write_result_progress and done_transfer and ring_empty);
transfer_count <= new_transfer_count;
read_issue_offset <= new_read_issue_offset;
diff --git a/modules/wishbone/wishbone_pkg.vhd b/modules/wishbone/wishbone_pkg.vhd
index 9c0a73da..1fed4e1e 100644
--- a/modules/wishbone/wishbone_pkg.vhd
+++ b/modules/wishbone/wishbone_pkg.vhd
@@ -269,19 +269,19 @@ package wishbone_pkg is
);
port(
-- Common wishbone signals
- clk : in std_logic;
- rst : in std_logic;
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
-- Slave control port
- slave_i : in t_wishbone_slave_in;
- slave_o : out t_wishbone_slave_out;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
-- Master reader port
- r_master_i : in t_wishbone_master_in;
- r_master_o : out t_wishbone_master_out;
+ r_master_i : in t_wishbone_master_in;
+ r_master_o : out t_wishbone_master_out;
-- Master writer port
- w_master_i : in t_wishbone_master_in;
- w_master_o : out t_wishbone_master_out;
+ w_master_i : in t_wishbone_master_in;
+ w_master_o : out t_wishbone_master_out;
-- Pulsed high completion signal
- interrupt : out std_logic
+ interrupt_o : out std_logic
);
end component;
@@ -291,15 +291,15 @@ package wishbone_pkg is
log2fifo : natural := 4);
port(
-- Common wishbone signals
- rst : in std_logic;
+ rst_n_i : in std_logic;
-- Slave control port
- slave_clk : in std_logic;
- slave_i : in t_wishbone_slave_in;
- slave_o : out t_wishbone_slave_out;
+ slave_clk_i : in std_logic;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
-- Master reader port
- master_clk : in std_logic;
- master_i : in t_wishbone_master_in;
- master_o : out t_wishbone_master_out);
+ master_clk_i : in std_logic;
+ master_i : in t_wishbone_master_in;
+ master_o : out t_wishbone_master_out);
end component;
-- g_size is in words
--
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