From 487570132532eafeb750945a2f0d81f38e33dd00 Mon Sep 17 00:00:00 2001
From: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
Date: Fri, 25 Aug 2017 18:13:32 +0200
Subject: [PATCH] genrams/xilinx: remove optimizations for ram initialization
They finally don't help much and they break simulation as Modelsim complains
about types conversion.
---
.../xilinx/generic_dpram_dualclock.vhd | 18 ---------
.../xilinx/generic_dpram_sameclock.vhd | 40 +------------------
2 files changed, 1 insertion(+), 57 deletions(-)
diff --git a/modules/genrams/xilinx/generic_dpram_dualclock.vhd b/modules/genrams/xilinx/generic_dpram_dualclock.vhd
index 7f1a4e43..9f3318d4 100644
--- a/modules/genrams/xilinx/generic_dpram_dualclock.vhd
+++ b/modules/genrams/xilinx/generic_dpram_dualclock.vhd
@@ -93,24 +93,6 @@ architecture syn of generic_dpram_dualclock is
return tmp;
end if;
- -- To speed-up most common cases, use dedicated functions
- -- 32-bit width
- if (g_data_width = 32) then
- mem32 := f_load_mem32_from_file(g_init_file, g_size, g_fail_if_file_not_found);
- return t_ram_type(mem32);
- end if;
- -- 16-bit width
- if (g_data_width = 16) then
- mem16 := f_load_mem16_from_file(g_init_file, g_size, g_fail_if_file_not_found);
- return t_ram_type(mem16);
- end if;
- -- 8-bit width
- if (g_data_width = 8) then
- mem8 := f_load_mem8_from_file(g_init_file, g_size, g_fail_if_file_not_found);
- return t_ram_type(mem8);
- end if;
-
- -- Only for "exotic" sizes do the lengthly (in Vivado 2016.4) copying
arr := f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
pos := 0;
while(pos < g_size)loop
diff --git a/modules/genrams/xilinx/generic_dpram_sameclock.vhd b/modules/genrams/xilinx/generic_dpram_sameclock.vhd
index ee4a7af5..49151486 100644
--- a/modules/genrams/xilinx/generic_dpram_sameclock.vhd
+++ b/modules/genrams/xilinx/generic_dpram_sameclock.vhd
@@ -92,24 +92,6 @@ architecture syn of generic_dpram_sameclock is
return tmp;
end if;
- -- To speed-up most common cases, use dedicated functions
- -- 32-bit width
- if (g_data_width = 32) then
- mem32 := f_load_mem32_from_file(g_init_file, g_size, g_fail_if_file_not_found);
- return t_ram_type(mem32);
- end if;
- -- 16-bit width
- if (g_data_width = 16) then
- mem16 := f_load_mem16_from_file(g_init_file, g_size, g_fail_if_file_not_found);
- return t_ram_type(mem16);
- end if;
- -- 8-bit width
- if (g_data_width = 8) then
- mem8 := f_load_mem8_from_file(g_init_file, g_size, g_fail_if_file_not_found);
- return t_ram_type(mem8);
- end if;
-
- -- Only for "exotic" sizes do the lengthly (in Vivado 2016.4) copying
arr := f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
pos := 0;
while(pos < g_size)loop
@@ -126,27 +108,6 @@ architecture syn of generic_dpram_sameclock is
return tmp;
end f_file_to_ramtype;
- --impure function InitRamFromFile(fname : in string) return t_ram_type is
- -- FILE RamFile : text;
- -- variable fline : line;
- -- variable RAM : t_ram_type;
- -- variable tmp_bv : bit_vector(g_data_width-1 downto 0);
- -- variable status : file_open_status;
- --begin
- -- if(fname = "" or fname = "none") then
- -- RAM := (others=>(others=>'0'));
- -- return RAM;
- -- end if;
-
- -- file_open(status, RamFile, fname, read_mode);
- -- for I in t_ram_type'range loop
- -- readline(RamFile, fline);
- -- read(fline, tmp_bv);
- -- RAM(I) := to_stdlogicvector(tmp_bv);
- -- end loop;
- -- return RAM;
- --end function;
-
function f_is_synthesis return boolean is
begin
-- synthesis translate_off
@@ -155,6 +116,7 @@ architecture syn of generic_dpram_sameclock is
return true;
end f_is_synthesis;
+
shared variable ram : t_ram_type := f_file_to_ramtype;
signal s_we_a : std_logic_vector(c_num_bytes-1 downto 0);
--
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