From 435046c28315f8e4302c7174824adb9786322286 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <w.terpstra@gsi.de>
Date: Thu, 22 Nov 2012 12:13:30 +0100
Subject: [PATCH] Make it possible to instantiate a PCIe-bridge without needing
interrupt generation.
---
modules/wishbone/wb_pcie/pcie_wb_pkg.vhd | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/modules/wishbone/wb_pcie/pcie_wb_pkg.vhd b/modules/wishbone/wb_pcie/pcie_wb_pkg.vhd
index 223d5f91..eb91aecb 100644
--- a/modules/wishbone/wb_pcie/pcie_wb_pkg.vhd
+++ b/modules/wishbone/wb_pcie/pcie_wb_pkg.vhd
@@ -20,7 +20,7 @@ package pcie_wb_pkg is
wb_rstn_i : in std_logic; -- Reset wishbone bus
master_o : out t_wishbone_master_out; -- Commands from PC to FPGA
master_i : in t_wishbone_master_in;
- slave_i : in t_wishbone_slave_in; -- Command to PC from FPGA
+ slave_i : in t_wishbone_slave_in := cc_dummy_slave_in; -- Command to PC from FPGA
slave_o : out t_wishbone_slave_out);
end component;
--
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