diff --git a/doc/gc_glitch_filt/Makefile b/doc/gc_glitch_filt/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..26ecf5376cfbd174330f0929daee3ea1cc8a6c96
--- /dev/null
+++ b/doc/gc_glitch_filt/Makefile
@@ -0,0 +1,14 @@
+FILE=gc_glitch_filt
+
+all:
+ $(MAKE) -C fig
+ pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
+ bibtex $(FILE).aux
+ pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
+ pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
+ evince $(FILE).pdf &
+
+clean:
+ $(MAKE) -C fig clean
+ rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
+
diff --git a/doc/gc_glitch_filt/README.txt b/doc/gc_glitch_filt/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..e69d1177f1e40e729e63801d1f69fcf7653bf564
--- /dev/null
+++ b/doc/gc_glitch_filt/README.txt
@@ -0,0 +1,4 @@
+Type 'make' to create your .pdf documentation file.
+
+You need Inkscape to make the documentation files:
+sudo apt-get install inkscape
\ No newline at end of file
diff --git a/doc/gc_glitch_filt/cern-title.tex b/doc/gc_glitch_filt/cern-title.tex
new file mode 100644
index 0000000000000000000000000000000000000000..adaf66abdc8a8b286fbcdb271db9d7af44c7b994
--- /dev/null
+++ b/doc/gc_glitch_filt/cern-title.tex
@@ -0,0 +1,25 @@
+\begin{titlepage}
+
+\vspace*{3cm}
+
+\noindent{\LARGE \textbf{Glitch filter}}
+
+\noindent \rule{\textwidth}{.1cm}
+
+\hfill March 3, 2014
+
+\vspace*{3cm}
+
+\begin{figure}[h]
+ \includegraphics[height=3cm]{fig/cern-logo}
+ \hfill
+ \includegraphics[height=3cm]{fig/ohwr-logo}
+\end{figure}
+
+\vfill
+
+\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
+
+\noindent \rule{\textwidth}{.05cm}
+
+\end{titlepage}
diff --git a/doc/gc_glitch_filt/fig/Makefile b/doc/gc_glitch_filt/fig/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..00fe82ab1dec0a92d0f8fbd96f7690b50f105166
--- /dev/null
+++ b/doc/gc_glitch_filt/fig/Makefile
@@ -0,0 +1,11 @@
+SRC = $(wildcard *.svg)
+OBJS = $(SRC:.svg=.pdf)
+
+all: $(OBJS)
+ echo $(OBJS)
+
+%.pdf : %.svg
+ inkscape -f $< -A $@
+
+clean :
+ rm -f *.pdf
diff --git a/doc/gc_glitch_filt/fig/cern-logo.svg b/doc/gc_glitch_filt/fig/cern-logo.svg
new file mode 100644
index 0000000000000000000000000000000000000000..470c7b0a157435f6443c68c4dd45248e68624585
--- /dev/null
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diff --git a/doc/gc_glitch_filt/gc_glitch_filt.bib b/doc/gc_glitch_filt/gc_glitch_filt.bib
new file mode 100644
index 0000000000000000000000000000000000000000..5b05ec0b62e231aedfa20c06e8374cfe6be7410c
--- /dev/null
+++ b/doc/gc_glitch_filt/gc_glitch_filt.bib
@@ -0,0 +1,9 @@
+@misc{ohwr,
+ title = {{Open Hardware Repository}},
+ howpublished = {\url{http://www.ohwr.org/}}
+}
+
+@misc{gencores-ohwr,
+ title = {{Platform-independent Core Collection webage on Open Hardware Repository}},
+ howpublished = {\url{http://www.ohwr.org/projects/general-cores/wiki}}
+}
diff --git a/doc/gc_glitch_filt/gc_glitch_filt.tex b/doc/gc_glitch_filt/gc_glitch_filt.tex
new file mode 100644
index 0000000000000000000000000000000000000000..2e372d4f4ab0ce2b9af851ecfcdcaefbd8a4963d
--- /dev/null
+++ b/doc/gc_glitch_filt/gc_glitch_filt.tex
@@ -0,0 +1,167 @@
+%==============================================================================
+% Document header
+%==============================================================================
+\documentclass[a4paper,11pt]{article}
+
+% Color package
+\usepackage[usenames,dvipsnames]{color}
+
+% Hyperrefs
+\usepackage[
+ colorlinks = true,
+ linkcolor = Mahogany,
+ citecolor = Mahogany,
+ urlcolor = blue,
+]{hyperref}
+
+\usepackage{graphicx}
+\usepackage{rotating}
+\usepackage{multirow}
+
+\usepackage{longtable}
+
+% Header and footer customization
+\usepackage{fancyhdr}
+\pagestyle{fancy}
+\fancyhead[L]{\nouppercase{\leftmark}}
+\fancyhead[R]{}
+\renewcommand{\footrulewidth}{0.4pt}
+
+%==============================================================================
+% Start of document
+%==============================================================================
+\begin{document}
+
+%------------------------------------------------------------------------------
+% Title
+%------------------------------------------------------------------------------
+\include{cern-title}
+
+%------------------------------------------------------------------------------
+% Revision history
+%------------------------------------------------------------------------------
+\thispagestyle{empty}
+\section*{Revision history}
+
+\centerline
+{
+ \begin{tabular}{l c p{.6\textwidth}}
+ \hline
+ \multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
+ \hline
+ 03-03-2014 & 0.01 & First draft \\
+ \hline
+ \end{tabular}
+}
+
+%------------------------------------------------------------------------------
+% Generate TOC and pagebreak after it
+%------------------------------------------------------------------------------
+\pagebreak
+\pagenumbering{roman}
+\setcounter{page}{1}
+\tableofcontents
+
+%------------------------------------------------------------------------------
+% List of figs, tables, abbrevs
+%------------------------------------------------------------------------------
+\listoffigures
+\listoftables
+
+%------------------------------------------------------------------------------
+% List of abbreviations
+%------------------------------------------------------------------------------
+\pagebreak
+\section*{List of Abbreviations}
+\begin{tabular}{l l}
+FF & Flip-Flop \\
+\end{tabular}
+
+%==============================================================================
+% SEC: Intro
+%==============================================================================
+\pagebreak
+\pagenumbering{arabic}
+\setcounter{page}{1}
+\section{Introduction}
+\label{sec:intro}
+
+This document presents the \textit{gc\_glitch\_filt} component, a modular glitch
+filter open-hardware~\cite{ohwr} design for FPGA or ASIC implementation. It is
+implemented as one short VHDL file which can be found under the following folder
+of the \textit{general-cores} repository~\cite{gencores-ohwr}:
+
+\begin{itemize}
+\item \textit{modules/common/}
+\end{itemize}
+
+%==============================================================================
+% SEC: Instantiation
+%==============================================================================
+\section{Instantiation}
+\label{sec:instantiation}
+
+Table~\ref{tbl:ports} shows the instantiation template for the \textit{gc\_glitch\_filt}
+component. It can be directly instantiated in a VHDL or Verilog design.
+
+The data to be filtered should be connected to the \textit{dat\_i} input. Note that
+the data is not synchronized internally to the \textit{clk\_i} signal, if metastability
+is a concern, a synchronization chain should be provided outside the component.
+
+The deglitched data is presented at the \textit{dat\_o} output a number of \textit{g\_len+1}
+clock cycles later.
+
+\begin{table}[h]
+ \caption{Ports and generics of \textit{gc\_i2c\_slave} module}
+ \label{tbl:ports}
+ \centerline
+ {
+ \begin{tabular}{l p{.7\textwidth}}
+ \hline
+ \multicolumn{1}{c}{\textbf{Name}} & \multicolumn{1}{c}{\textbf{Description}} \\
+ \hline
+ g\_len & Glitch filter length generic (in \textit{clk\_i} cycles) \newline
+ 1 -- glitches narrower than 1 \textit{clk\_i} cycle are filtered \newline
+ 2 -- glitches narrower than 2 \textit{clk\_i} cycles are filtered \newline
+ etc.\\
+ clk\_i & Clock input \\
+ rst\_n\_i & Active-low reset input \\
+ dat\_i & Data input (should be synchronous to \textit{clk\_i})\\
+ dat\_o & Deglitched data output (synchronous to \textit{clk\_i}) \\
+ \hline
+ \end{tabular}
+ }
+\end{table}
+
+%==============================================================================
+% SEC: implem
+%==============================================================================
+\pagebreak
+\section{Implementation and operation}
+
+Figure~\ref{fig:implem} shows the implementation of the \textit{gc\_glitch\_filt}
+block.
+
+\begin{figure}[h]
+ \centerline{\includegraphics[width=\textwidth]{fig/implem}}
+ \caption{Implementation of the \textit{gc\_glitch\_filt} block}
+ \label{fig:implem}
+\end{figure}
+
+The block's operation is very simple and can be summarized as follows. At synthesis
+time, \textit{g\_len} FFs are generated. If the \textit{dat\_i} is stable for a number
+of \textit{g\_len} cycles, all FFs in the deglitching stage have the same value,
+and the \textit{dat\_o} output changes to reflect the state of \textit{dat\_i}.
+Should a glitch occur at any time on the \textit{dat\_i} signal, it is filtered
+by the AND (or NAND) gate at the output.
+
+All the FFs are cleared ('0') on reset.
+
+%==============================================================================
+% Bibliography
+%==============================================================================
+\pagebreak
+\bibliographystyle{ieeetr}
+\bibliography{gc_glitch_filt}
+
+\end{document}
diff --git a/doc/gc_i2c_slave/cern-title.tex b/doc/gc_i2c_slave/cern-title.tex
index 8f5dbe8b4d93648f99b9297428c5da35a6410240..b24f03be714d88cd7dea8f27893e5848b61b3cf8 100644
--- a/doc/gc_i2c_slave/cern-title.tex
+++ b/doc/gc_i2c_slave/cern-title.tex
@@ -6,7 +6,7 @@
\noindent \rule{\textwidth}{.1cm}
-\hfill\today
+\hfill February 12, 2014
\vspace*{3cm}
diff --git a/doc/gc_i2c_slave/gc_i2c_slave.tex b/doc/gc_i2c_slave/gc_i2c_slave.tex
index 76fb546487e42b71a7898b1d519ec363602702a1..c38c0603f43695cae347bd4c994020cde04de901 100644
--- a/doc/gc_i2c_slave/gc_i2c_slave.tex
+++ b/doc/gc_i2c_slave/gc_i2c_slave.tex
@@ -51,6 +51,7 @@
\hline
26-06-2013 & 0.01 & First draft \\
28-10-2013 & 0.02 & Changed PDF link colors \\
+ 12-02-2014 & 0.03 & Updated block implementation \\
\hline
\end{tabular}
}
diff --git a/doc/wb_i2c_bridge/cern-title.tex b/doc/wb_i2c_bridge/cern-title.tex
index 0ca0388704b08a7bb7ae17261fbf5614e57dfee8..575e86246e82c737930b57f3f90651b9498bb158 100644
--- a/doc/wb_i2c_bridge/cern-title.tex
+++ b/doc/wb_i2c_bridge/cern-title.tex
@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
-\hfill 18 Dec. 2013
+\hfill February 12, 2014
\vspace*{3cm}
diff --git a/doc/wb_i2c_bridge/wb_i2c_bridge.tex b/doc/wb_i2c_bridge/wb_i2c_bridge.tex
index 4a0f58c468a981019c4231be842d12e29a0f7774..9dc62e153358a410d778c080d367c4efc4684af5 100644
--- a/doc/wb_i2c_bridge/wb_i2c_bridge.tex
+++ b/doc/wb_i2c_bridge/wb_i2c_bridge.tex
@@ -59,6 +59,7 @@
changes in protocol \\
29-10-2013 & 0.04 & Changed PDF link colors \\
18-12-2013 & 1.00 & Finite version with watchdog timer and robust communication \\
+ 12-02-2014 & 1.01 & Removed SIM_WB_TRANSFER state in FSM \\
\hline
\end{tabular}
}
diff --git a/doc/wb_xil_multiboot/wb_xil_multiboot.tex b/doc/wb_xil_multiboot/wb_xil_multiboot.tex
index 7ce33d07f76104ef2543b588a8d26ec70c3c8182..1672bcb1f69a953cebb0beae7b47c94e489810cc 100644
--- a/doc/wb_xil_multiboot/wb_xil_multiboot.tex
+++ b/doc/wb_xil_multiboot/wb_xil_multiboot.tex
@@ -65,7 +65,7 @@
28-10-2013 & 0.1 & First draft \\
18-12-2013 & 1.0 & Added WDTO bit to status register and information about the FSM watchdog
mechanism \\
- 13-12-2013 & 1.1 & Made memory map prettier \\
+ 13-02-2014 & 1.1 & Made memory map prettier \\
\hline
\end{tabular}
}
diff --git a/modules/common/gc_glitch_filt.vhd b/modules/common/gc_glitch_filt.vhd
index bbd8fbb7f09c2229e99c993069465e0ac10c8e91..de4627c71145a23180b8f7a42defab178233bc68 100644
--- a/modules/common/gc_glitch_filt.vhd
+++ b/modules/common/gc_glitch_filt.vhd
@@ -10,6 +10,9 @@
-- version: 1.0
--
-- description:
+-- Glitch filter consisting of a set of chained flip-flops followed by a
+-- comparator. The comparator toggles to '1' when all FFs in the chain are
+-- '1' and respectively to '0' when all the FFS in the chain are '0'.
--
-- dependencies:
--
@@ -54,7 +57,7 @@ entity gc_glitch_filt is
clk_i : in std_logic;
rst_n_i : in std_logic;
- -- Data input
+ -- Data input, synchronous to clk_i
dat_i : in std_logic;
-- Data output
@@ -70,7 +73,6 @@ architecture behav of gc_glitch_filt is
-- Signal declarations
--============================================================================
signal glitch_filt : std_logic_vector(g_len downto 0);
- signal dat_synced : std_logic;
--==============================================================================
-- architecture begin
@@ -80,20 +82,7 @@ begin
--============================================================================
-- Glitch filtration logic
--============================================================================
- -- First, synchronize the data input in the clk_i domain
- cmp_sync : gc_sync_ffs
- port map
- (
- clk_i => clk_i,
- rst_n_i => rst_n_i,
- data_i => dat_i,
- synced_o => dat_synced,
- npulse_o => open,
- ppulse_o => open
- );
-
- -- Then, assign the current sample of the glitch filter
- glitch_filt(0) <= dat_synced;
+ glitch_filt(0) <= dat_i;
-- Generate glitch filter FFs when the filter length is > 0
gen_glitch_filt: if (g_len > 0) generate
diff --git a/modules/common/gc_i2c_slave.vhd b/modules/common/gc_i2c_slave.vhd
index 68daa1181a90a30cf82a574658c0b8a5dd3a93f5..ad415d4236748d0c8f18a32ecf5141859a2c6b00 100644
--- a/modules/common/gc_i2c_slave.vhd
+++ b/modules/common/gc_i2c_slave.vhd
@@ -138,8 +138,10 @@ architecture behav of gc_i2c_slave is
-- Signal declarations
--============================================================================
-- Deglitched signals and delays for SCL and SDA lines
+ signal scl_synced : std_logic;
signal scl_deglitched : std_logic;
signal scl_deglitched_d0 : std_logic;
+ signal sda_synced : std_logic;
signal sda_deglitched : std_logic;
signal sda_deglitched_d0 : std_logic;
signal scl_r_edge_p : std_logic;
@@ -185,7 +187,21 @@ begin
--============================================================================
-- Deglitching logic
--============================================================================
- -- Generate deglitched SCL signal with 54-ns max. glitch width
+ -- First, synchronize the SCL signal in the clk_i domain
+ cmp_sync_scl : gc_sync_ffs
+ generic map
+ (
+ g_sync_edge => "positive"
+ )
+ port map
+ (
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ data_i => scl_i,
+ synced_o => scl_synced
+ );
+
+ -- Generate deglitched SCL signal
cmp_scl_deglitch : gc_glitch_filt
generic map
(
@@ -195,7 +211,7 @@ begin
(
clk_i => clk_i,
rst_n_i => rst_n_i,
- dat_i => scl_i,
+ dat_i => scl_synced,
dat_o => scl_deglitched
);
@@ -216,7 +232,21 @@ begin
end if;
end process p_scl_degl_d0;
- -- Generate deglitched SDA signal with 54-ns max. glitch width
+ -- Synchronize SDA signal in clk_i domain
+ cmp_sda_sync : gc_sync_ffs
+ generic map
+ (
+ g_sync_edge => "positive"
+ )
+ port map
+ (
+ clk_i => clk_i,
+ rst_n_i => rst_n_i,
+ data_i => sda_i,
+ synced_o => sda_synced
+ );
+
+ -- Generate deglitched SDA signal
cmp_sda_deglitch : gc_glitch_filt
generic map
(
@@ -226,7 +256,7 @@ begin
(
clk_i => clk_i,
rst_n_i => rst_n_i,
- dat_i => sda_i,
+ dat_i => sda_synced,
dat_o => sda_deglitched
);