diff --git a/modules/common/gc_arbitrated_mux.vhd b/modules/common/gc_arbitrated_mux.vhd
index 3e43a245167f57b09bd1b647bf5db043b7604c27..25e66bbc666c7494e59d240e3681341440f9a44f 100644
--- a/modules/common/gc_arbitrated_mux.vhd
+++ b/modules/common/gc_arbitrated_mux.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2011-08-24
--- Last update: 2019-09-09
+-- Last update: 2020-09-18
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -38,7 +38,6 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 use work.gencores_pkg.all;
-use work.genram_pkg.all;
 
 entity gc_arbitrated_mux is
   
@@ -67,7 +66,7 @@ entity gc_arbitrated_mux is
     q_valid_o    : out std_logic;
 
     -- Index of the input, to which came the currently outputted data word.
-    q_input_id_o : out std_logic_vector(f_log2_size(g_num_inputs)-1 downto 0)
+    q_input_id_o : out std_logic_vector(f_log2_ceil(g_num_inputs)-1 downto 0)
     );
 
 end gc_arbitrated_mux;  
@@ -130,7 +129,7 @@ begin  -- rtl
 
         if(unsigned(grant) /= 0) then
           q_o          <= dregs(f_onehot_decode(grant));
-          q_input_id_o <= std_logic_vector(to_unsigned(f_onehot_decode(grant), f_log2_size(g_num_inputs)));
+          q_input_id_o <= std_logic_vector(to_unsigned(f_onehot_decode(grant), f_log2_ceil(g_num_inputs)));
           q_valid_o <= '1';
         else
           q_o <= (others => 'X');
diff --git a/modules/common/gc_big_adder.vhd b/modules/common/gc_big_adder.vhd
index 6df186cf5496cbf4caf977a4c872834457edd3ba..5452382b861022b874323494b4499e186a669fcc 100644
--- a/modules/common/gc_big_adder.vhd
+++ b/modules/common/gc_big_adder.vhd
@@ -31,7 +31,6 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-use work.wishbone_pkg.all;
 use work.gencores_pkg.all;
 
 -- Expects registers for inputs. Async outputs.
diff --git a/modules/common/gc_dyn_extend_pulse.vhd b/modules/common/gc_dyn_extend_pulse.vhd
index a5761dd3edc6b60d8770529ae2cbfcd0866e1ef4..e19703d66e967ac905f467183caf75046471858f 100644
--- a/modules/common/gc_dyn_extend_pulse.vhd
+++ b/modules/common/gc_dyn_extend_pulse.vhd
@@ -29,7 +29,6 @@ use ieee.NUMERIC_STD.all;
 
 library work;
 use work.gencores_pkg.all;
-use work.genram_pkg.all;
 
 entity gc_dyn_extend_pulse is
   generic
diff --git a/modules/common/gc_fsm_watchdog.vhd b/modules/common/gc_fsm_watchdog.vhd
index 9d57d80d5a0b9b08121bbc0b61516f2c79cb2086..7a0f0cda4de342d840d06dd41ea75393f3557e5e 100644
--- a/modules/common/gc_fsm_watchdog.vhd
+++ b/modules/common/gc_fsm_watchdog.vhd
@@ -38,7 +38,7 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-use work.genram_pkg.all;
+use work.gencores_pkg.all;
 
 entity gc_fsm_watchdog is
   generic
@@ -66,7 +66,7 @@ architecture behav of gc_fsm_watchdog is
   --============================================================================
   -- Signal declarations
   --============================================================================
-  signal wdt                : unsigned(f_log2_size(g_wdt_max)-1 downto 0);
+  signal wdt                : unsigned(f_log2_ceil(g_wdt_max)-1 downto 0);
 
 --==============================================================================
 --  architecture begin
diff --git a/modules/common/gc_moving_average.vhd b/modules/common/gc_moving_average.vhd
index 9ddb215fb60cf4c2170182cf3090097507fbc03e..df0b121fd16d777dafb4938d2ea6b22f95f8dba0 100644
--- a/modules/common/gc_moving_average.vhd
+++ b/modules/common/gc_moving_average.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2009-09-01
--- Last update: 2017-10-11
+-- Last update: 2020-04-07
 -- Platform   : FPGA-generic
 -- Standard   : VHDL '93
 -------------------------------------------------------------------------------
@@ -46,7 +46,6 @@ use ieee.NUMERIC_STD.all;
 
 library work;
 use work.gencores_pkg.all;
-use work.genram_pkg.all;
 
 entity gc_moving_average is
 
diff --git a/modules/common/gc_word_packer.vhd b/modules/common/gc_word_packer.vhd
index d0e86dbe5ebfc54236d31ceb2ef44cca25725281..03badd36ce2d6a8ed1cab10883fae2acb2e22f96 100644
--- a/modules/common/gc_word_packer.vhd
+++ b/modules/common/gc_word_packer.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2012-09-13
--- Last update: 2012-09-13
+-- Last update: 2020-09-18
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -39,7 +39,7 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-use work.genram_pkg.all;
+use work.gencores_pkg.all;
 
 entity gc_word_packer is
 
@@ -101,7 +101,7 @@ architecture rtl of gc_word_packer is
   constant c_sreg_entries : integer := c_sreg_size / f_min(g_input_width, g_output_width);
 
   signal sreg  : std_logic_vector(c_sreg_size-1 downto 0);
-  signal count : unsigned(f_log2_size(c_sreg_entries + 1) - 1 downto 0);
+  signal count : unsigned(f_log2_ceil(c_sreg_entries + 1) - 1 downto 0);
   signal empty : std_logic;
 
   signal q_valid_comb, q_valid_reg, q_req_d0 : std_logic;